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LINE 67
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T138,T214,T215 |
1 | 1 | Covered | T1,T2,T3 |
LINE 79
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T13,T14,T15 |
1 | 0 | Covered | T263,T264,T265 |
LINE 86
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T13,T14,T15 |
0 | 1 | 0 | Covered | T263,T264,T265 |
1 | 0 | 0 | Covered | T13,T14,T15 |
LINE 136
EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[432:435]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[436:439]}) ? 2'b1 : 2'd2))
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T4,T10 |
LINE 136
SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[436:439]}) ? 2'b1 : 2'd2)
-----------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T5 |
LINE 175
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T263,T264,T265 |
0 | 1 | 0 | Covered | T134,T138,T214 |
1 | 0 | 0 | Covered | T138,T214,T215 |
LINE 1638
EXPRESSION (control_we & ctrl_regwen_qs)
-----1---- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T20,T7 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1832
EXPRESSION (addr_we & ctrl_regwen_qs)
---1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T6,T7,T18 |
1 | 1 | Covered | T1,T2,T3 |
LINE 1863
EXPRESSION (prog_type_en_we & ctrl_regwen_qs)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T110,T111,T112 |
LINE 2183
EXPRESSION (mp_region_cfg_0_we & region_cfg_regwen_0_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 2378
EXPRESSION (mp_region_cfg_1_we & region_cfg_regwen_1_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T253,T268 |
1 | 1 | Covered | T1,T2,T3 |
LINE 2573
EXPRESSION (mp_region_cfg_2_we & region_cfg_regwen_2_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T136,T269 |
1 | 1 | Covered | T1,T2,T3 |
LINE 2768
EXPRESSION (mp_region_cfg_3_we & region_cfg_regwen_3_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T267,T270 |
1 | 1 | Covered | T1,T2,T3 |
LINE 2963
EXPRESSION (mp_region_cfg_4_we & region_cfg_regwen_4_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3158
EXPRESSION (mp_region_cfg_5_we & region_cfg_regwen_5_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3353
EXPRESSION (mp_region_cfg_6_we & region_cfg_regwen_6_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T267 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3548
EXPRESSION (mp_region_cfg_7_we & region_cfg_regwen_7_qs)
---------1-------- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T252,T253,T271 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3743
EXPRESSION (mp_region_0_we & region_cfg_regwen_0_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3803
EXPRESSION (mp_region_1_we & region_cfg_regwen_1_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T253,T268 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3863
EXPRESSION (mp_region_2_we & region_cfg_regwen_2_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T74,T75 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3923
EXPRESSION (mp_region_3_we & region_cfg_regwen_3_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T270,T251 |
1 | 1 | Covered | T1,T2,T3 |
LINE 3983
EXPRESSION (mp_region_4_we & region_cfg_regwen_4_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 4043
EXPRESSION (mp_region_5_we & region_cfg_regwen_5_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T135,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 4103
EXPRESSION (mp_region_6_we & region_cfg_regwen_6_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 4163
EXPRESSION (mp_region_7_we & region_cfg_regwen_7_qs)
-------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T136,T252,T271 |
1 | 1 | Covered | T1,T2,T3 |
LINE 4677
EXPRESSION (bank0_info0_page_cfg_0_we & bank0_info0_regwen_0_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T267 |
1 | 1 | Covered | T1,T2,T3 |
LINE 4872
EXPRESSION (bank0_info0_page_cfg_1_we & bank0_info0_regwen_1_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 5067
EXPRESSION (bank0_info0_page_cfg_2_we & bank0_info0_regwen_2_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 5262
EXPRESSION (bank0_info0_page_cfg_3_we & bank0_info0_regwen_3_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T270,T136 |
1 | 1 | Covered | T1,T2,T3 |
LINE 5457
EXPRESSION (bank0_info0_page_cfg_4_we & bank0_info0_regwen_4_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T135,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 5652
EXPRESSION (bank0_info0_page_cfg_5_we & bank0_info0_regwen_5_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T267 |
1 | 1 | Covered | T1,T2,T3 |
LINE 5847
EXPRESSION (bank0_info0_page_cfg_6_we & bank0_info0_regwen_6_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T135,T267,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 6042
EXPRESSION (bank0_info0_page_cfg_7_we & bank0_info0_regwen_7_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T250,T251 |
1 | 1 | Covered | T1,T2,T3 |
LINE 6237
EXPRESSION (bank0_info0_page_cfg_8_we & bank0_info0_regwen_8_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T75,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 6432
EXPRESSION (bank0_info0_page_cfg_9_we & bank0_info0_regwen_9_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 6656
EXPRESSION (bank0_info1_page_cfg_we & bank0_info1_regwen_qs)
-----------1----------- ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T270 |
1 | 1 | Covered | T1,T2,T3 |
LINE 6909
EXPRESSION (bank0_info2_page_cfg_0_we & bank0_info2_regwen_0_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T74,T75 |
1 | 1 | Covered | T1,T2,T3 |
LINE 7104
EXPRESSION (bank0_info2_page_cfg_1_we & bank0_info2_regwen_1_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T135,T267 |
1 | 1 | Covered | T1,T2,T3 |
LINE 7589
EXPRESSION (bank1_info0_page_cfg_0_we & bank1_info0_regwen_0_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T135,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 7784
EXPRESSION (bank1_info0_page_cfg_1_we & bank1_info0_regwen_1_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T250,T251 |
1 | 1 | Covered | T1,T2,T3 |
LINE 7979
EXPRESSION (bank1_info0_page_cfg_2_we & bank1_info0_regwen_2_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T74,T75 |
1 | 1 | Covered | T1,T2,T3 |
LINE 8174
EXPRESSION (bank1_info0_page_cfg_3_we & bank1_info0_regwen_3_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 8369
EXPRESSION (bank1_info0_page_cfg_4_we & bank1_info0_regwen_4_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T135,T267,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 8564
EXPRESSION (bank1_info0_page_cfg_5_we & bank1_info0_regwen_5_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T75,T267 |
1 | 1 | Covered | T1,T2,T3 |
LINE 8759
EXPRESSION (bank1_info0_page_cfg_6_we & bank1_info0_regwen_6_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T74,T75,T135 |
1 | 1 | Covered | T1,T2,T3 |
LINE 8954
EXPRESSION (bank1_info0_page_cfg_7_we & bank1_info0_regwen_7_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T135,T270 |
1 | 1 | Covered | T1,T2,T3 |
LINE 9149
EXPRESSION (bank1_info0_page_cfg_8_we & bank1_info0_regwen_8_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T74,T75 |
1 | 1 | Covered | T1,T2,T3 |
LINE 9344
EXPRESSION (bank1_info0_page_cfg_9_we & bank1_info0_regwen_9_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T136,T251 |
1 | 1 | Covered | T1,T2,T3 |
LINE 9568
EXPRESSION (bank1_info1_page_cfg_we & bank1_info1_regwen_qs)
-----------1----------- ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T74,T250 |
1 | 1 | Covered | T1,T2,T3 |
LINE 9821
EXPRESSION (bank1_info2_page_cfg_0_we & bank1_info2_regwen_0_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T267,T250,T136 |
1 | 1 | Covered | T1,T2,T3 |
LINE 10016
EXPRESSION (bank1_info2_page_cfg_1_we & bank1_info2_regwen_1_qs)
------------1------------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T135,T269 |
1 | 1 | Covered | T1,T2,T3 |
LINE 10295
EXPRESSION (mp_bank_cfg_shadowed_we & bank_cfg_regwen_qs)
-----------1----------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T73,T75,T267 |
1 | 1 | Covered | T8,T32,T33 |
LINE 11824
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INTR_STATE_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11825
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INTR_ENABLE_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T31,T25 |
LINE 11826
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INTR_TEST_OFFSET)
------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11827
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ALERT_TEST_OFFSET)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T120,T67 |
LINE 11828
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_DIS_OFFSET)
---------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11829
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_EXEC_OFFSET)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9,T12 |
LINE 11830
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_INIT_OFFSET)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11831
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CTRL_REGWEN_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11832
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CONTROL_OFFSET)
-----------------------------1-----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11833
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ADDR_OFFSET)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11834
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_PROG_TYPE_EN_OFFSET)
--------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11835
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_ERASE_SUSPEND_OFFSET)
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11836
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11837
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11838
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11839
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11840
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11841
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11842
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11843
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET)
-----------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11844
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_0_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11845
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_1_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11846
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_2_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11847
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_3_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11848
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_4_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11849
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_5_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11850
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_6_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11851
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_CFG_7_OFFSET)
---------------------------------1---------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11852
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_0_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11853
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_1_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11854
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_2_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11855
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_3_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11856
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_4_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11857
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_5_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11858
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_6_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11859
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_MP_REGION_7_OFFSET)
-------------------------------1-------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11860
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_DEFAULT_REGION_OFFSET)
---------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11861
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11862
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11863
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11864
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11865
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11866
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11867
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11868
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11869
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11870
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11871
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11872
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11873
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11874
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11875
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11876
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11877
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11878
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11879
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11880
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11881
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET)
-----------------------------------1----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11882
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11883
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11884
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T20 |
LINE 11885
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11886
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET)
-------------------------------------1------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 11887
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11888
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11889
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T20 |
LINE 11890
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11891
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T9,T12,T53 |
LINE 11892
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T20,T67 |
LINE 11893
EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET)
------------------------------------1-----------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T12,T53,T67 |