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 LINE       11938
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T15,T10,T11
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T15,T9
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T3,T15,T10
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Covered	T2,T3,T15
1	1	Covered	T3,T9,T16

 LINE       11938
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T18,T11
1	1	Covered	T10,T11,T5

 LINE       11938
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T10,T11
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T10,T11
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T76
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T15,T10,T11

 LINE       11938
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       11938
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T55
1	1	Covered	T10,T11,T55

 LINE       12050
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T134,T230,T233
1	1	1	Covered	T2,T3,T15

 LINE       12055
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T77,T134,T230
1	1	1	Covered	T40,T41,T42

 LINE       12068
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T233,T267,T268
1	1	1	Covered	T262,T263,T269

 LINE       12081
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T55
1	1	0	Covered	T77,T134,T233
1	1	1	Covered	T120,T121,T122

 LINE       12092
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T4
1	1	0	Covered	T77,T230,T233
1	1	1	Covered	T4,T5,T33

 LINE       12095
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T10,T11
1	1	0	Covered	T77,T230,T233
1	1	1	Covered	T3,T58,T65

 LINE       12098
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T230,T233
1	1	1	Covered	T1,T2,T3

 LINE       12101
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T79,T263,T132

 LINE       12102
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T77,T134,T230
1	1	1	Covered	T2,T3,T15

 LINE       12117
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T231,T233,T270
1	1	1	Covered	T2,T3,T15

 LINE       12120
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T230,T231,T233
1	1	1	Covered	T113,T114,T115

 LINE       12125
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T26,T11
1	1	0	Covered	T77,T230,T231
1	1	1	Covered	T26,T71,T34

 LINE       12128
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T77,T134,T230
1	1	1	Covered	T78,T79,T80

 LINE       12131
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T55
1	1	0	Covered	T233,T270,T271
1	1	1	Covered	T78,T79,T80

 LINE       12134
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T55
1	1	0	Covered	T231,T233,T243
1	1	1	Covered	T78,T79,T80

 LINE       12137
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T230,T231,T233
1	1	1	Covered	T78,T79,T80

 LINE       12140
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T55
1	1	0	Covered	T77,T230,T243
1	1	1	Covered	T78,T79,T80

 LINE       12143
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T10,T11,T55
1	1	0	Covered	T233,T243,T271
1	1	1	Covered	T78,T79,T80

 LINE       12146
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T77,T230,T231
1	1	1	Covered	T78,T79,T80

 LINE       12149
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T15,T10,T11
1	1	0	Covered	T231,T233,T270
1	1	1	Covered	T78,T79,T80

 LINE       12152
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T77,T230,T233
1	1	1	Covered	T1,T2,T3

 LINE       12167
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T77,T230,T243
1	1	1	Covered	T2,T3,T15

 LINE       12182
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T230,T233,T243
1	1	1	Covered	T2,T3,T15

 LINE       12197
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T230,T233,T267
1	1	1	Covered	T2,T3,T15

 LINE       12212
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T77,T134,T230
1	1	1	Covered	T2,T3,T15

 LINE       12227
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T134,T270,T267
1	1	1	Covered	T2,T3,T15