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76 always_ff @(posedge clk_i or negedge rst_ni) begin
77 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
78 1/1 err_q <= '0;
Tests: T1 T2 T3
79 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
80 1/1 err_q <= 1'b1;
Tests: T13 T14 T15
81 end
MISSING_ELSE
82 end
83
84 // integrity error output is permanent and should be used for alert generation
85 // register errors are transactional
86 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
87
88 // outgoing integrity generation
89 tlul_pkg::tl_d2h_t tl_o_pre;
90 tlul_rsp_intg_gen #(
91 .EnableRspIntgGen(1),
92 .EnableDataIntgGen(0)
93 ) u_rsp_intg_gen (
94 .tl_i(tl_o_pre),
95 .tl_o(tl_o)
96 );
97
98 tlul_pkg::tl_h2d_t tl_socket_h2d [3];
99 tlul_pkg::tl_d2h_t tl_socket_d2h [3];
100
101 logic [1:0] reg_steer;
102
103 // socket_1n connection
104 1/1 assign tl_reg_h2d = tl_socket_h2d[2];
Tests: T1 T2 T3
105 1/1 assign tl_socket_d2h[2] = tl_reg_d2h;
Tests: T1 T2 T3
106
107 1/1 assign tl_win_o[0] = tl_socket_h2d[0];
Tests: T1 T2 T3
108 1/1 assign tl_socket_d2h[0] = tl_win_i[0];
Tests: T1 T2 T3
109 1/1 assign tl_win_o[1] = tl_socket_h2d[1];
Tests: T1 T2 T3
110 1/1 assign tl_socket_d2h[1] = tl_win_i[1];
Tests: T1 T2 T3
111
112 // Create Socket_1n
113 tlul_socket_1n #(
114 .N (3),
115 .HReqPass (1'b1),
116 .HRspPass (1'b1),
117 .DReqPass ({3{1'b1}}),
118 .DRspPass ({3{1'b1}}),
119 .HReqDepth (4'h0),
120 .HRspDepth (4'h0),
121 .DReqDepth ({3{4'h0}}),
122 .DRspDepth ({3{4'h0}}),
123 .ExplicitErrs (1'b0)
124 ) u_socket (
125 .clk_i (clk_i),
126 .rst_ni (rst_ni),
127 .tl_h_i (tl_i),
128 .tl_h_o (tl_o_pre),
129 .tl_d_o (tl_socket_h2d),
130 .tl_d_i (tl_socket_d2h),
131 .dev_select_i (reg_steer)
132 );
133
134 // Create steering logic
135 always_comb begin
136 1/1 reg_steer =
Tests: T1 T2 T3
137 tl_i.a_address[AW-1:0] inside {[432:435]} ? 2'd0 :
138 tl_i.a_address[AW-1:0] inside {[436:439]} ? 2'd1 :
139 // Default set to register
140 2'd2;
141
142 // Override this in case of an integrity error
143 1/1 if (intg_err) begin
Tests: T1 T2 T3
144 1/1 reg_steer = 2'd2;
Tests: T263 T264 T265
145 end
MISSING_ELSE
146 end
147
148 tlul_adapter_reg #(
149 .RegAw(AW),
150 .RegDw(DW),
151 .EnableDataIntgGen(1)
152 ) u_reg_if (
153 .clk_i (clk_i),
154 .rst_ni (rst_ni),
155
156 .tl_i (tl_reg_h2d),
157 .tl_o (tl_reg_d2h),
158
159 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
160 .intg_error_o(),
161
162 .we_o (reg_we),
163 .re_o (reg_re),
164 .addr_o (reg_addr),
165 .wdata_o (reg_wdata),
166 .be_o (reg_be),
167 .busy_i (reg_busy),
168 .rdata_i (reg_rdata),
169 .error_i (reg_error)
170 );
171
172 // cdc oversampling signals
173
174 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
175 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T1 T2 T3
176
177 // Define SW related signals
178 // Format: <reg>_<field>_{wd|we|qs}
179 // or <reg>_{wd|we|qs} if field == 1 or 0
180 logic intr_state_we;
181 logic intr_state_prog_empty_qs;
182 logic intr_state_prog_lvl_qs;
183 logic intr_state_rd_full_qs;
184 logic intr_state_rd_lvl_qs;
185 logic intr_state_op_done_qs;
186 logic intr_state_op_done_wd;
187 logic intr_state_corr_err_qs;
188 logic intr_state_corr_err_wd;
189 logic intr_enable_we;
190 logic intr_enable_prog_empty_qs;
191 logic intr_enable_prog_empty_wd;
192 logic intr_enable_prog_lvl_qs;
193 logic intr_enable_prog_lvl_wd;
194 logic intr_enable_rd_full_qs;
195 logic intr_enable_rd_full_wd;
196 logic intr_enable_rd_lvl_qs;
197 logic intr_enable_rd_lvl_wd;
198 logic intr_enable_op_done_qs;
199 logic intr_enable_op_done_wd;
200 logic intr_enable_corr_err_qs;
201 logic intr_enable_corr_err_wd;
202 logic intr_test_we;
203 logic intr_test_prog_empty_wd;
204 logic intr_test_prog_lvl_wd;
205 logic intr_test_rd_full_wd;
206 logic intr_test_rd_lvl_wd;
207 logic intr_test_op_done_wd;
208 logic intr_test_corr_err_wd;
209 logic alert_test_we;
210 logic alert_test_recov_err_wd;
211 logic alert_test_fatal_std_err_wd;
212 logic alert_test_fatal_err_wd;
213 logic alert_test_fatal_prim_flash_alert_wd;
214 logic alert_test_recov_prim_flash_alert_wd;
215 logic dis_we;
216 logic [3:0] dis_qs;
217 logic [3:0] dis_wd;
218 logic exec_we;
219 logic [31:0] exec_qs;
220 logic [31:0] exec_wd;
221 logic init_we;
222 logic init_qs;
223 logic init_wd;
224 logic ctrl_regwen_re;
225 logic ctrl_regwen_qs;
226 logic control_we;
227 logic control_start_qs;
228 logic control_start_wd;
229 logic [1:0] control_op_qs;
230 logic [1:0] control_op_wd;
231 logic control_prog_sel_qs;
232 logic control_prog_sel_wd;
233 logic control_erase_sel_qs;
234 logic control_erase_sel_wd;
235 logic control_partition_sel_qs;
236 logic control_partition_sel_wd;
237 logic [1:0] control_info_sel_qs;
238 logic [1:0] control_info_sel_wd;
239 logic [11:0] control_num_qs;
240 logic [11:0] control_num_wd;
241 logic addr_we;
242 logic [19:0] addr_qs;
243 logic [19:0] addr_wd;
244 logic prog_type_en_we;
245 logic prog_type_en_normal_qs;
246 logic prog_type_en_normal_wd;
247 logic prog_type_en_repair_qs;
248 logic prog_type_en_repair_wd;
249 logic erase_suspend_we;
250 logic erase_suspend_qs;
251 logic erase_suspend_wd;
252 logic region_cfg_regwen_0_we;
253 logic region_cfg_regwen_0_qs;
254 logic region_cfg_regwen_0_wd;
255 logic region_cfg_regwen_1_we;
256 logic region_cfg_regwen_1_qs;
257 logic region_cfg_regwen_1_wd;
258 logic region_cfg_regwen_2_we;
259 logic region_cfg_regwen_2_qs;
260 logic region_cfg_regwen_2_wd;
261 logic region_cfg_regwen_3_we;
262 logic region_cfg_regwen_3_qs;
263 logic region_cfg_regwen_3_wd;
264 logic region_cfg_regwen_4_we;
265 logic region_cfg_regwen_4_qs;
266 logic region_cfg_regwen_4_wd;
267 logic region_cfg_regwen_5_we;
268 logic region_cfg_regwen_5_qs;
269 logic region_cfg_regwen_5_wd;
270 logic region_cfg_regwen_6_we;
271 logic region_cfg_regwen_6_qs;
272 logic region_cfg_regwen_6_wd;
273 logic region_cfg_regwen_7_we;
274 logic region_cfg_regwen_7_qs;
275 logic region_cfg_regwen_7_wd;
276 logic mp_region_cfg_0_we;
277 logic [3:0] mp_region_cfg_0_en_0_qs;
278 logic [3:0] mp_region_cfg_0_en_0_wd;
279 logic [3:0] mp_region_cfg_0_rd_en_0_qs;
280 logic [3:0] mp_region_cfg_0_rd_en_0_wd;
281 logic [3:0] mp_region_cfg_0_prog_en_0_qs;
282 logic [3:0] mp_region_cfg_0_prog_en_0_wd;
283 logic [3:0] mp_region_cfg_0_erase_en_0_qs;
284 logic [3:0] mp_region_cfg_0_erase_en_0_wd;
285 logic [3:0] mp_region_cfg_0_scramble_en_0_qs;
286 logic [3:0] mp_region_cfg_0_scramble_en_0_wd;
287 logic [3:0] mp_region_cfg_0_ecc_en_0_qs;
288 logic [3:0] mp_region_cfg_0_ecc_en_0_wd;
289 logic [3:0] mp_region_cfg_0_he_en_0_qs;
290 logic [3:0] mp_region_cfg_0_he_en_0_wd;
291 logic mp_region_cfg_1_we;
292 logic [3:0] mp_region_cfg_1_en_1_qs;
293 logic [3:0] mp_region_cfg_1_en_1_wd;
294 logic [3:0] mp_region_cfg_1_rd_en_1_qs;
295 logic [3:0] mp_region_cfg_1_rd_en_1_wd;
296 logic [3:0] mp_region_cfg_1_prog_en_1_qs;
297 logic [3:0] mp_region_cfg_1_prog_en_1_wd;
298 logic [3:0] mp_region_cfg_1_erase_en_1_qs;
299 logic [3:0] mp_region_cfg_1_erase_en_1_wd;
300 logic [3:0] mp_region_cfg_1_scramble_en_1_qs;
301 logic [3:0] mp_region_cfg_1_scramble_en_1_wd;
302 logic [3:0] mp_region_cfg_1_ecc_en_1_qs;
303 logic [3:0] mp_region_cfg_1_ecc_en_1_wd;
304 logic [3:0] mp_region_cfg_1_he_en_1_qs;
305 logic [3:0] mp_region_cfg_1_he_en_1_wd;
306 logic mp_region_cfg_2_we;
307 logic [3:0] mp_region_cfg_2_en_2_qs;
308 logic [3:0] mp_region_cfg_2_en_2_wd;
309 logic [3:0] mp_region_cfg_2_rd_en_2_qs;
310 logic [3:0] mp_region_cfg_2_rd_en_2_wd;
311 logic [3:0] mp_region_cfg_2_prog_en_2_qs;
312 logic [3:0] mp_region_cfg_2_prog_en_2_wd;
313 logic [3:0] mp_region_cfg_2_erase_en_2_qs;
314 logic [3:0] mp_region_cfg_2_erase_en_2_wd;
315 logic [3:0] mp_region_cfg_2_scramble_en_2_qs;
316 logic [3:0] mp_region_cfg_2_scramble_en_2_wd;
317 logic [3:0] mp_region_cfg_2_ecc_en_2_qs;
318 logic [3:0] mp_region_cfg_2_ecc_en_2_wd;
319 logic [3:0] mp_region_cfg_2_he_en_2_qs;
320 logic [3:0] mp_region_cfg_2_he_en_2_wd;
321 logic mp_region_cfg_3_we;
322 logic [3:0] mp_region_cfg_3_en_3_qs;
323 logic [3:0] mp_region_cfg_3_en_3_wd;
324 logic [3:0] mp_region_cfg_3_rd_en_3_qs;
325 logic [3:0] mp_region_cfg_3_rd_en_3_wd;
326 logic [3:0] mp_region_cfg_3_prog_en_3_qs;
327 logic [3:0] mp_region_cfg_3_prog_en_3_wd;
328 logic [3:0] mp_region_cfg_3_erase_en_3_qs;
329 logic [3:0] mp_region_cfg_3_erase_en_3_wd;
330 logic [3:0] mp_region_cfg_3_scramble_en_3_qs;
331 logic [3:0] mp_region_cfg_3_scramble_en_3_wd;
332 logic [3:0] mp_region_cfg_3_ecc_en_3_qs;
333 logic [3:0] mp_region_cfg_3_ecc_en_3_wd;
334 logic [3:0] mp_region_cfg_3_he_en_3_qs;
335 logic [3:0] mp_region_cfg_3_he_en_3_wd;
336 logic mp_region_cfg_4_we;
337 logic [3:0] mp_region_cfg_4_en_4_qs;
338 logic [3:0] mp_region_cfg_4_en_4_wd;
339 logic [3:0] mp_region_cfg_4_rd_en_4_qs;
340 logic [3:0] mp_region_cfg_4_rd_en_4_wd;
341 logic [3:0] mp_region_cfg_4_prog_en_4_qs;
342 logic [3:0] mp_region_cfg_4_prog_en_4_wd;
343 logic [3:0] mp_region_cfg_4_erase_en_4_qs;
344 logic [3:0] mp_region_cfg_4_erase_en_4_wd;
345 logic [3:0] mp_region_cfg_4_scramble_en_4_qs;
346 logic [3:0] mp_region_cfg_4_scramble_en_4_wd;
347 logic [3:0] mp_region_cfg_4_ecc_en_4_qs;
348 logic [3:0] mp_region_cfg_4_ecc_en_4_wd;
349 logic [3:0] mp_region_cfg_4_he_en_4_qs;
350 logic [3:0] mp_region_cfg_4_he_en_4_wd;
351 logic mp_region_cfg_5_we;
352 logic [3:0] mp_region_cfg_5_en_5_qs;
353 logic [3:0] mp_region_cfg_5_en_5_wd;
354 logic [3:0] mp_region_cfg_5_rd_en_5_qs;
355 logic [3:0] mp_region_cfg_5_rd_en_5_wd;
356 logic [3:0] mp_region_cfg_5_prog_en_5_qs;
357 logic [3:0] mp_region_cfg_5_prog_en_5_wd;
358 logic [3:0] mp_region_cfg_5_erase_en_5_qs;
359 logic [3:0] mp_region_cfg_5_erase_en_5_wd;
360 logic [3:0] mp_region_cfg_5_scramble_en_5_qs;
361 logic [3:0] mp_region_cfg_5_scramble_en_5_wd;
362 logic [3:0] mp_region_cfg_5_ecc_en_5_qs;
363 logic [3:0] mp_region_cfg_5_ecc_en_5_wd;
364 logic [3:0] mp_region_cfg_5_he_en_5_qs;
365 logic [3:0] mp_region_cfg_5_he_en_5_wd;
366 logic mp_region_cfg_6_we;
367 logic [3:0] mp_region_cfg_6_en_6_qs;
368 logic [3:0] mp_region_cfg_6_en_6_wd;
369 logic [3:0] mp_region_cfg_6_rd_en_6_qs;
370 logic [3:0] mp_region_cfg_6_rd_en_6_wd;
371 logic [3:0] mp_region_cfg_6_prog_en_6_qs;
372 logic [3:0] mp_region_cfg_6_prog_en_6_wd;
373 logic [3:0] mp_region_cfg_6_erase_en_6_qs;
374 logic [3:0] mp_region_cfg_6_erase_en_6_wd;
375 logic [3:0] mp_region_cfg_6_scramble_en_6_qs;
376 logic [3:0] mp_region_cfg_6_scramble_en_6_wd;
377 logic [3:0] mp_region_cfg_6_ecc_en_6_qs;
378 logic [3:0] mp_region_cfg_6_ecc_en_6_wd;
379 logic [3:0] mp_region_cfg_6_he_en_6_qs;
380 logic [3:0] mp_region_cfg_6_he_en_6_wd;
381 logic mp_region_cfg_7_we;
382 logic [3:0] mp_region_cfg_7_en_7_qs;
383 logic [3:0] mp_region_cfg_7_en_7_wd;
384 logic [3:0] mp_region_cfg_7_rd_en_7_qs;
385 logic [3:0] mp_region_cfg_7_rd_en_7_wd;
386 logic [3:0] mp_region_cfg_7_prog_en_7_qs;
387 logic [3:0] mp_region_cfg_7_prog_en_7_wd;
388 logic [3:0] mp_region_cfg_7_erase_en_7_qs;
389 logic [3:0] mp_region_cfg_7_erase_en_7_wd;
390 logic [3:0] mp_region_cfg_7_scramble_en_7_qs;
391 logic [3:0] mp_region_cfg_7_scramble_en_7_wd;
392 logic [3:0] mp_region_cfg_7_ecc_en_7_qs;
393 logic [3:0] mp_region_cfg_7_ecc_en_7_wd;
394 logic [3:0] mp_region_cfg_7_he_en_7_qs;
395 logic [3:0] mp_region_cfg_7_he_en_7_wd;
396 logic mp_region_0_we;
397 logic [8:0] mp_region_0_base_0_qs;
398 logic [8:0] mp_region_0_base_0_wd;
399 logic [9:0] mp_region_0_size_0_qs;
400 logic [9:0] mp_region_0_size_0_wd;
401 logic mp_region_1_we;
402 logic [8:0] mp_region_1_base_1_qs;
403 logic [8:0] mp_region_1_base_1_wd;
404 logic [9:0] mp_region_1_size_1_qs;
405 logic [9:0] mp_region_1_size_1_wd;
406 logic mp_region_2_we;
407 logic [8:0] mp_region_2_base_2_qs;
408 logic [8:0] mp_region_2_base_2_wd;
409 logic [9:0] mp_region_2_size_2_qs;
410 logic [9:0] mp_region_2_size_2_wd;
411 logic mp_region_3_we;
412 logic [8:0] mp_region_3_base_3_qs;
413 logic [8:0] mp_region_3_base_3_wd;
414 logic [9:0] mp_region_3_size_3_qs;
415 logic [9:0] mp_region_3_size_3_wd;
416 logic mp_region_4_we;
417 logic [8:0] mp_region_4_base_4_qs;
418 logic [8:0] mp_region_4_base_4_wd;
419 logic [9:0] mp_region_4_size_4_qs;
420 logic [9:0] mp_region_4_size_4_wd;
421 logic mp_region_5_we;
422 logic [8:0] mp_region_5_base_5_qs;
423 logic [8:0] mp_region_5_base_5_wd;
424 logic [9:0] mp_region_5_size_5_qs;
425 logic [9:0] mp_region_5_size_5_wd;
426 logic mp_region_6_we;
427 logic [8:0] mp_region_6_base_6_qs;
428 logic [8:0] mp_region_6_base_6_wd;
429 logic [9:0] mp_region_6_size_6_qs;
430 logic [9:0] mp_region_6_size_6_wd;
431 logic mp_region_7_we;
432 logic [8:0] mp_region_7_base_7_qs;
433 logic [8:0] mp_region_7_base_7_wd;
434 logic [9:0] mp_region_7_size_7_qs;
435 logic [9:0] mp_region_7_size_7_wd;
436 logic default_region_we;
437 logic [3:0] default_region_rd_en_qs;
438 logic [3:0] default_region_rd_en_wd;
439 logic [3:0] default_region_prog_en_qs;
440 logic [3:0] default_region_prog_en_wd;
441 logic [3:0] default_region_erase_en_qs;
442 logic [3:0] default_region_erase_en_wd;
443 logic [3:0] default_region_scramble_en_qs;
444 logic [3:0] default_region_scramble_en_wd;
445 logic [3:0] default_region_ecc_en_qs;
446 logic [3:0] default_region_ecc_en_wd;
447 logic [3:0] default_region_he_en_qs;
448 logic [3:0] default_region_he_en_wd;
449 logic bank0_info0_regwen_0_we;
450 logic bank0_info0_regwen_0_qs;
451 logic bank0_info0_regwen_0_wd;
452 logic bank0_info0_regwen_1_we;
453 logic bank0_info0_regwen_1_qs;
454 logic bank0_info0_regwen_1_wd;
455 logic bank0_info0_regwen_2_we;
456 logic bank0_info0_regwen_2_qs;
457 logic bank0_info0_regwen_2_wd;
458 logic bank0_info0_regwen_3_we;
459 logic bank0_info0_regwen_3_qs;
460 logic bank0_info0_regwen_3_wd;
461 logic bank0_info0_regwen_4_we;
462 logic bank0_info0_regwen_4_qs;
463 logic bank0_info0_regwen_4_wd;
464 logic bank0_info0_regwen_5_we;
465 logic bank0_info0_regwen_5_qs;
466 logic bank0_info0_regwen_5_wd;
467 logic bank0_info0_regwen_6_we;
468 logic bank0_info0_regwen_6_qs;
469 logic bank0_info0_regwen_6_wd;
470 logic bank0_info0_regwen_7_we;
471 logic bank0_info0_regwen_7_qs;
472 logic bank0_info0_regwen_7_wd;
473 logic bank0_info0_regwen_8_we;
474 logic bank0_info0_regwen_8_qs;
475 logic bank0_info0_regwen_8_wd;
476 logic bank0_info0_regwen_9_we;
477 logic bank0_info0_regwen_9_qs;
478 logic bank0_info0_regwen_9_wd;
479 logic bank0_info0_page_cfg_0_we;
480 logic [3:0] bank0_info0_page_cfg_0_en_0_qs;
481 logic [3:0] bank0_info0_page_cfg_0_en_0_wd;
482 logic [3:0] bank0_info0_page_cfg_0_rd_en_0_qs;
483 logic [3:0] bank0_info0_page_cfg_0_rd_en_0_wd;
484 logic [3:0] bank0_info0_page_cfg_0_prog_en_0_qs;
485 logic [3:0] bank0_info0_page_cfg_0_prog_en_0_wd;
486 logic [3:0] bank0_info0_page_cfg_0_erase_en_0_qs;
487 logic [3:0] bank0_info0_page_cfg_0_erase_en_0_wd;
488 logic [3:0] bank0_info0_page_cfg_0_scramble_en_0_qs;
489 logic [3:0] bank0_info0_page_cfg_0_scramble_en_0_wd;
490 logic [3:0] bank0_info0_page_cfg_0_ecc_en_0_qs;
491 logic [3:0] bank0_info0_page_cfg_0_ecc_en_0_wd;
492 logic [3:0] bank0_info0_page_cfg_0_he_en_0_qs;
493 logic [3:0] bank0_info0_page_cfg_0_he_en_0_wd;
494 logic bank0_info0_page_cfg_1_we;
495 logic [3:0] bank0_info0_page_cfg_1_en_1_qs;
496 logic [3:0] bank0_info0_page_cfg_1_en_1_wd;
497 logic [3:0] bank0_info0_page_cfg_1_rd_en_1_qs;
498 logic [3:0] bank0_info0_page_cfg_1_rd_en_1_wd;
499 logic [3:0] bank0_info0_page_cfg_1_prog_en_1_qs;
500 logic [3:0] bank0_info0_page_cfg_1_prog_en_1_wd;
501 logic [3:0] bank0_info0_page_cfg_1_erase_en_1_qs;
502 logic [3:0] bank0_info0_page_cfg_1_erase_en_1_wd;
503 logic [3:0] bank0_info0_page_cfg_1_scramble_en_1_qs;
504 logic [3:0] bank0_info0_page_cfg_1_scramble_en_1_wd;
505 logic [3:0] bank0_info0_page_cfg_1_ecc_en_1_qs;
506 logic [3:0] bank0_info0_page_cfg_1_ecc_en_1_wd;
507 logic [3:0] bank0_info0_page_cfg_1_he_en_1_qs;
508 logic [3:0] bank0_info0_page_cfg_1_he_en_1_wd;
509 logic bank0_info0_page_cfg_2_we;
510 logic [3:0] bank0_info0_page_cfg_2_en_2_qs;
511 logic [3:0] bank0_info0_page_cfg_2_en_2_wd;
512 logic [3:0] bank0_info0_page_cfg_2_rd_en_2_qs;
513 logic [3:0] bank0_info0_page_cfg_2_rd_en_2_wd;
514 logic [3:0] bank0_info0_page_cfg_2_prog_en_2_qs;
515 logic [3:0] bank0_info0_page_cfg_2_prog_en_2_wd;
516 logic [3:0] bank0_info0_page_cfg_2_erase_en_2_qs;
517 logic [3:0] bank0_info0_page_cfg_2_erase_en_2_wd;
518 logic [3:0] bank0_info0_page_cfg_2_scramble_en_2_qs;
519 logic [3:0] bank0_info0_page_cfg_2_scramble_en_2_wd;
520 logic [3:0] bank0_info0_page_cfg_2_ecc_en_2_qs;
521 logic [3:0] bank0_info0_page_cfg_2_ecc_en_2_wd;
522 logic [3:0] bank0_info0_page_cfg_2_he_en_2_qs;
523 logic [3:0] bank0_info0_page_cfg_2_he_en_2_wd;
524 logic bank0_info0_page_cfg_3_we;
525 logic [3:0] bank0_info0_page_cfg_3_en_3_qs;
526 logic [3:0] bank0_info0_page_cfg_3_en_3_wd;
527 logic [3:0] bank0_info0_page_cfg_3_rd_en_3_qs;
528 logic [3:0] bank0_info0_page_cfg_3_rd_en_3_wd;
529 logic [3:0] bank0_info0_page_cfg_3_prog_en_3_qs;
530 logic [3:0] bank0_info0_page_cfg_3_prog_en_3_wd;
531 logic [3:0] bank0_info0_page_cfg_3_erase_en_3_qs;
532 logic [3:0] bank0_info0_page_cfg_3_erase_en_3_wd;
533 logic [3:0] bank0_info0_page_cfg_3_scramble_en_3_qs;
534 logic [3:0] bank0_info0_page_cfg_3_scramble_en_3_wd;
535 logic [3:0] bank0_info0_page_cfg_3_ecc_en_3_qs;
536 logic [3:0] bank0_info0_page_cfg_3_ecc_en_3_wd;
537 logic [3:0] bank0_info0_page_cfg_3_he_en_3_qs;
538 logic [3:0] bank0_info0_page_cfg_3_he_en_3_wd;
539 logic bank0_info0_page_cfg_4_we;
540 logic [3:0] bank0_info0_page_cfg_4_en_4_qs;
541 logic [3:0] bank0_info0_page_cfg_4_en_4_wd;
542 logic [3:0] bank0_info0_page_cfg_4_rd_en_4_qs;
543 logic [3:0] bank0_info0_page_cfg_4_rd_en_4_wd;
544 logic [3:0] bank0_info0_page_cfg_4_prog_en_4_qs;
545 logic [3:0] bank0_info0_page_cfg_4_prog_en_4_wd;
546 logic [3:0] bank0_info0_page_cfg_4_erase_en_4_qs;
547 logic [3:0] bank0_info0_page_cfg_4_erase_en_4_wd;
548 logic [3:0] bank0_info0_page_cfg_4_scramble_en_4_qs;
549 logic [3:0] bank0_info0_page_cfg_4_scramble_en_4_wd;
550 logic [3:0] bank0_info0_page_cfg_4_ecc_en_4_qs;
551 logic [3:0] bank0_info0_page_cfg_4_ecc_en_4_wd;
552 logic [3:0] bank0_info0_page_cfg_4_he_en_4_qs;
553 logic [3:0] bank0_info0_page_cfg_4_he_en_4_wd;
554 logic bank0_info0_page_cfg_5_we;
555 logic [3:0] bank0_info0_page_cfg_5_en_5_qs;
556 logic [3:0] bank0_info0_page_cfg_5_en_5_wd;
557 logic [3:0] bank0_info0_page_cfg_5_rd_en_5_qs;
558 logic [3:0] bank0_info0_page_cfg_5_rd_en_5_wd;
559 logic [3:0] bank0_info0_page_cfg_5_prog_en_5_qs;
560 logic [3:0] bank0_info0_page_cfg_5_prog_en_5_wd;
561 logic [3:0] bank0_info0_page_cfg_5_erase_en_5_qs;
562 logic [3:0] bank0_info0_page_cfg_5_erase_en_5_wd;
563 logic [3:0] bank0_info0_page_cfg_5_scramble_en_5_qs;
564 logic [3:0] bank0_info0_page_cfg_5_scramble_en_5_wd;
565 logic [3:0] bank0_info0_page_cfg_5_ecc_en_5_qs;
566 logic [3:0] bank0_info0_page_cfg_5_ecc_en_5_wd;
567 logic [3:0] bank0_info0_page_cfg_5_he_en_5_qs;
568 logic [3:0] bank0_info0_page_cfg_5_he_en_5_wd;
569 logic bank0_info0_page_cfg_6_we;
570 logic [3:0] bank0_info0_page_cfg_6_en_6_qs;
571 logic [3:0] bank0_info0_page_cfg_6_en_6_wd;
572 logic [3:0] bank0_info0_page_cfg_6_rd_en_6_qs;
573 logic [3:0] bank0_info0_page_cfg_6_rd_en_6_wd;
574 logic [3:0] bank0_info0_page_cfg_6_prog_en_6_qs;
575 logic [3:0] bank0_info0_page_cfg_6_prog_en_6_wd;
576 logic [3:0] bank0_info0_page_cfg_6_erase_en_6_qs;
577 logic [3:0] bank0_info0_page_cfg_6_erase_en_6_wd;
578 logic [3:0] bank0_info0_page_cfg_6_scramble_en_6_qs;
579 logic [3:0] bank0_info0_page_cfg_6_scramble_en_6_wd;
580 logic [3:0] bank0_info0_page_cfg_6_ecc_en_6_qs;
581 logic [3:0] bank0_info0_page_cfg_6_ecc_en_6_wd;
582 logic [3:0] bank0_info0_page_cfg_6_he_en_6_qs;
583 logic [3:0] bank0_info0_page_cfg_6_he_en_6_wd;
584 logic bank0_info0_page_cfg_7_we;
585 logic [3:0] bank0_info0_page_cfg_7_en_7_qs;
586 logic [3:0] bank0_info0_page_cfg_7_en_7_wd;
587 logic [3:0] bank0_info0_page_cfg_7_rd_en_7_qs;
588 logic [3:0] bank0_info0_page_cfg_7_rd_en_7_wd;
589 logic [3:0] bank0_info0_page_cfg_7_prog_en_7_qs;
590 logic [3:0] bank0_info0_page_cfg_7_prog_en_7_wd;
591 logic [3:0] bank0_info0_page_cfg_7_erase_en_7_qs;
592 logic [3:0] bank0_info0_page_cfg_7_erase_en_7_wd;
593 logic [3:0] bank0_info0_page_cfg_7_scramble_en_7_qs;
594 logic [3:0] bank0_info0_page_cfg_7_scramble_en_7_wd;
595 logic [3:0] bank0_info0_page_cfg_7_ecc_en_7_qs;
596 logic [3:0] bank0_info0_page_cfg_7_ecc_en_7_wd;
597 logic [3:0] bank0_info0_page_cfg_7_he_en_7_qs;
598 logic [3:0] bank0_info0_page_cfg_7_he_en_7_wd;
599 logic bank0_info0_page_cfg_8_we;
600 logic [3:0] bank0_info0_page_cfg_8_en_8_qs;
601 logic [3:0] bank0_info0_page_cfg_8_en_8_wd;
602 logic [3:0] bank0_info0_page_cfg_8_rd_en_8_qs;
603 logic [3:0] bank0_info0_page_cfg_8_rd_en_8_wd;
604 logic [3:0] bank0_info0_page_cfg_8_prog_en_8_qs;
605 logic [3:0] bank0_info0_page_cfg_8_prog_en_8_wd;
606 logic [3:0] bank0_info0_page_cfg_8_erase_en_8_qs;
607 logic [3:0] bank0_info0_page_cfg_8_erase_en_8_wd;
608 logic [3:0] bank0_info0_page_cfg_8_scramble_en_8_qs;
609 logic [3:0] bank0_info0_page_cfg_8_scramble_en_8_wd;
610 logic [3:0] bank0_info0_page_cfg_8_ecc_en_8_qs;
611 logic [3:0] bank0_info0_page_cfg_8_ecc_en_8_wd;
612 logic [3:0] bank0_info0_page_cfg_8_he_en_8_qs;
613 logic [3:0] bank0_info0_page_cfg_8_he_en_8_wd;
614 logic bank0_info0_page_cfg_9_we;
615 logic [3:0] bank0_info0_page_cfg_9_en_9_qs;
616 logic [3:0] bank0_info0_page_cfg_9_en_9_wd;
617 logic [3:0] bank0_info0_page_cfg_9_rd_en_9_qs;
618 logic [3:0] bank0_info0_page_cfg_9_rd_en_9_wd;
619 logic [3:0] bank0_info0_page_cfg_9_prog_en_9_qs;
620 logic [3:0] bank0_info0_page_cfg_9_prog_en_9_wd;
621 logic [3:0] bank0_info0_page_cfg_9_erase_en_9_qs;
622 logic [3:0] bank0_info0_page_cfg_9_erase_en_9_wd;
623 logic [3:0] bank0_info0_page_cfg_9_scramble_en_9_qs;
624 logic [3:0] bank0_info0_page_cfg_9_scramble_en_9_wd;
625 logic [3:0] bank0_info0_page_cfg_9_ecc_en_9_qs;
626 logic [3:0] bank0_info0_page_cfg_9_ecc_en_9_wd;
627 logic [3:0] bank0_info0_page_cfg_9_he_en_9_qs;
628 logic [3:0] bank0_info0_page_cfg_9_he_en_9_wd;
629 logic bank0_info1_regwen_we;
630 logic bank0_info1_regwen_qs;
631 logic bank0_info1_regwen_wd;
632 logic bank0_info1_page_cfg_we;
633 logic [3:0] bank0_info1_page_cfg_en_0_qs;
634 logic [3:0] bank0_info1_page_cfg_en_0_wd;
635 logic [3:0] bank0_info1_page_cfg_rd_en_0_qs;
636 logic [3:0] bank0_info1_page_cfg_rd_en_0_wd;
637 logic [3:0] bank0_info1_page_cfg_prog_en_0_qs;
638 logic [3:0] bank0_info1_page_cfg_prog_en_0_wd;
639 logic [3:0] bank0_info1_page_cfg_erase_en_0_qs;
640 logic [3:0] bank0_info1_page_cfg_erase_en_0_wd;
641 logic [3:0] bank0_info1_page_cfg_scramble_en_0_qs;
642 logic [3:0] bank0_info1_page_cfg_scramble_en_0_wd;
643 logic [3:0] bank0_info1_page_cfg_ecc_en_0_qs;
644 logic [3:0] bank0_info1_page_cfg_ecc_en_0_wd;
645 logic [3:0] bank0_info1_page_cfg_he_en_0_qs;
646 logic [3:0] bank0_info1_page_cfg_he_en_0_wd;
647 logic bank0_info2_regwen_0_we;
648 logic bank0_info2_regwen_0_qs;
649 logic bank0_info2_regwen_0_wd;
650 logic bank0_info2_regwen_1_we;
651 logic bank0_info2_regwen_1_qs;
652 logic bank0_info2_regwen_1_wd;
653 logic bank0_info2_page_cfg_0_we;
654 logic [3:0] bank0_info2_page_cfg_0_en_0_qs;
655 logic [3:0] bank0_info2_page_cfg_0_en_0_wd;
656 logic [3:0] bank0_info2_page_cfg_0_rd_en_0_qs;
657 logic [3:0] bank0_info2_page_cfg_0_rd_en_0_wd;
658 logic [3:0] bank0_info2_page_cfg_0_prog_en_0_qs;
659 logic [3:0] bank0_info2_page_cfg_0_prog_en_0_wd;
660 logic [3:0] bank0_info2_page_cfg_0_erase_en_0_qs;
661 logic [3:0] bank0_info2_page_cfg_0_erase_en_0_wd;
662 logic [3:0] bank0_info2_page_cfg_0_scramble_en_0_qs;
663 logic [3:0] bank0_info2_page_cfg_0_scramble_en_0_wd;
664 logic [3:0] bank0_info2_page_cfg_0_ecc_en_0_qs;
665 logic [3:0] bank0_info2_page_cfg_0_ecc_en_0_wd;
666 logic [3:0] bank0_info2_page_cfg_0_he_en_0_qs;
667 logic [3:0] bank0_info2_page_cfg_0_he_en_0_wd;
668 logic bank0_info2_page_cfg_1_we;
669 logic [3:0] bank0_info2_page_cfg_1_en_1_qs;
670 logic [3:0] bank0_info2_page_cfg_1_en_1_wd;
671 logic [3:0] bank0_info2_page_cfg_1_rd_en_1_qs;
672 logic [3:0] bank0_info2_page_cfg_1_rd_en_1_wd;
673 logic [3:0] bank0_info2_page_cfg_1_prog_en_1_qs;
674 logic [3:0] bank0_info2_page_cfg_1_prog_en_1_wd;
675 logic [3:0] bank0_info2_page_cfg_1_erase_en_1_qs;
676 logic [3:0] bank0_info2_page_cfg_1_erase_en_1_wd;
677 logic [3:0] bank0_info2_page_cfg_1_scramble_en_1_qs;
678 logic [3:0] bank0_info2_page_cfg_1_scramble_en_1_wd;
679 logic [3:0] bank0_info2_page_cfg_1_ecc_en_1_qs;
680 logic [3:0] bank0_info2_page_cfg_1_ecc_en_1_wd;
681 logic [3:0] bank0_info2_page_cfg_1_he_en_1_qs;
682 logic [3:0] bank0_info2_page_cfg_1_he_en_1_wd;
683 logic bank1_info0_regwen_0_we;
684 logic bank1_info0_regwen_0_qs;
685 logic bank1_info0_regwen_0_wd;
686 logic bank1_info0_regwen_1_we;
687 logic bank1_info0_regwen_1_qs;
688 logic bank1_info0_regwen_1_wd;
689 logic bank1_info0_regwen_2_we;
690 logic bank1_info0_regwen_2_qs;
691 logic bank1_info0_regwen_2_wd;
692 logic bank1_info0_regwen_3_we;
693 logic bank1_info0_regwen_3_qs;
694 logic bank1_info0_regwen_3_wd;
695 logic bank1_info0_regwen_4_we;
696 logic bank1_info0_regwen_4_qs;
697 logic bank1_info0_regwen_4_wd;
698 logic bank1_info0_regwen_5_we;
699 logic bank1_info0_regwen_5_qs;
700 logic bank1_info0_regwen_5_wd;
701 logic bank1_info0_regwen_6_we;
702 logic bank1_info0_regwen_6_qs;
703 logic bank1_info0_regwen_6_wd;
704 logic bank1_info0_regwen_7_we;
705 logic bank1_info0_regwen_7_qs;
706 logic bank1_info0_regwen_7_wd;
707 logic bank1_info0_regwen_8_we;
708 logic bank1_info0_regwen_8_qs;
709 logic bank1_info0_regwen_8_wd;
710 logic bank1_info0_regwen_9_we;
711 logic bank1_info0_regwen_9_qs;
712 logic bank1_info0_regwen_9_wd;
713 logic bank1_info0_page_cfg_0_we;
714 logic [3:0] bank1_info0_page_cfg_0_en_0_qs;
715 logic [3:0] bank1_info0_page_cfg_0_en_0_wd;
716 logic [3:0] bank1_info0_page_cfg_0_rd_en_0_qs;
717 logic [3:0] bank1_info0_page_cfg_0_rd_en_0_wd;
718 logic [3:0] bank1_info0_page_cfg_0_prog_en_0_qs;
719 logic [3:0] bank1_info0_page_cfg_0_prog_en_0_wd;
720 logic [3:0] bank1_info0_page_cfg_0_erase_en_0_qs;
721 logic [3:0] bank1_info0_page_cfg_0_erase_en_0_wd;
722 logic [3:0] bank1_info0_page_cfg_0_scramble_en_0_qs;
723 logic [3:0] bank1_info0_page_cfg_0_scramble_en_0_wd;
724 logic [3:0] bank1_info0_page_cfg_0_ecc_en_0_qs;
725 logic [3:0] bank1_info0_page_cfg_0_ecc_en_0_wd;
726 logic [3:0] bank1_info0_page_cfg_0_he_en_0_qs;
727 logic [3:0] bank1_info0_page_cfg_0_he_en_0_wd;
728 logic bank1_info0_page_cfg_1_we;
729 logic [3:0] bank1_info0_page_cfg_1_en_1_qs;
730 logic [3:0] bank1_info0_page_cfg_1_en_1_wd;
731 logic [3:0] bank1_info0_page_cfg_1_rd_en_1_qs;
732 logic [3:0] bank1_info0_page_cfg_1_rd_en_1_wd;
733 logic [3:0] bank1_info0_page_cfg_1_prog_en_1_qs;
734 logic [3:0] bank1_info0_page_cfg_1_prog_en_1_wd;
735 logic [3:0] bank1_info0_page_cfg_1_erase_en_1_qs;
736 logic [3:0] bank1_info0_page_cfg_1_erase_en_1_wd;
737 logic [3:0] bank1_info0_page_cfg_1_scramble_en_1_qs;
738 logic [3:0] bank1_info0_page_cfg_1_scramble_en_1_wd;
739 logic [3:0] bank1_info0_page_cfg_1_ecc_en_1_qs;
740 logic [3:0] bank1_info0_page_cfg_1_ecc_en_1_wd;
741 logic [3:0] bank1_info0_page_cfg_1_he_en_1_qs;
742 logic [3:0] bank1_info0_page_cfg_1_he_en_1_wd;
743 logic bank1_info0_page_cfg_2_we;
744 logic [3:0] bank1_info0_page_cfg_2_en_2_qs;
745 logic [3:0] bank1_info0_page_cfg_2_en_2_wd;
746 logic [3:0] bank1_info0_page_cfg_2_rd_en_2_qs;
747 logic [3:0] bank1_info0_page_cfg_2_rd_en_2_wd;
748 logic [3:0] bank1_info0_page_cfg_2_prog_en_2_qs;
749 logic [3:0] bank1_info0_page_cfg_2_prog_en_2_wd;
750 logic [3:0] bank1_info0_page_cfg_2_erase_en_2_qs;
751 logic [3:0] bank1_info0_page_cfg_2_erase_en_2_wd;
752 logic [3:0] bank1_info0_page_cfg_2_scramble_en_2_qs;
753 logic [3:0] bank1_info0_page_cfg_2_scramble_en_2_wd;
754 logic [3:0] bank1_info0_page_cfg_2_ecc_en_2_qs;
755 logic [3:0] bank1_info0_page_cfg_2_ecc_en_2_wd;
756 logic [3:0] bank1_info0_page_cfg_2_he_en_2_qs;
757 logic [3:0] bank1_info0_page_cfg_2_he_en_2_wd;
758 logic bank1_info0_page_cfg_3_we;
759 logic [3:0] bank1_info0_page_cfg_3_en_3_qs;
760 logic [3:0] bank1_info0_page_cfg_3_en_3_wd;
761 logic [3:0] bank1_info0_page_cfg_3_rd_en_3_qs;
762 logic [3:0] bank1_info0_page_cfg_3_rd_en_3_wd;
763 logic [3:0] bank1_info0_page_cfg_3_prog_en_3_qs;
764 logic [3:0] bank1_info0_page_cfg_3_prog_en_3_wd;
765 logic [3:0] bank1_info0_page_cfg_3_erase_en_3_qs;
766 logic [3:0] bank1_info0_page_cfg_3_erase_en_3_wd;
767 logic [3:0] bank1_info0_page_cfg_3_scramble_en_3_qs;
768 logic [3:0] bank1_info0_page_cfg_3_scramble_en_3_wd;
769 logic [3:0] bank1_info0_page_cfg_3_ecc_en_3_qs;
770 logic [3:0] bank1_info0_page_cfg_3_ecc_en_3_wd;
771 logic [3:0] bank1_info0_page_cfg_3_he_en_3_qs;
772 logic [3:0] bank1_info0_page_cfg_3_he_en_3_wd;
773 logic bank1_info0_page_cfg_4_we;
774 logic [3:0] bank1_info0_page_cfg_4_en_4_qs;
775 logic [3:0] bank1_info0_page_cfg_4_en_4_wd;
776 logic [3:0] bank1_info0_page_cfg_4_rd_en_4_qs;
777 logic [3:0] bank1_info0_page_cfg_4_rd_en_4_wd;
778 logic [3:0] bank1_info0_page_cfg_4_prog_en_4_qs;
779 logic [3:0] bank1_info0_page_cfg_4_prog_en_4_wd;
780 logic [3:0] bank1_info0_page_cfg_4_erase_en_4_qs;
781 logic [3:0] bank1_info0_page_cfg_4_erase_en_4_wd;
782 logic [3:0] bank1_info0_page_cfg_4_scramble_en_4_qs;
783 logic [3:0] bank1_info0_page_cfg_4_scramble_en_4_wd;
784 logic [3:0] bank1_info0_page_cfg_4_ecc_en_4_qs;
785 logic [3:0] bank1_info0_page_cfg_4_ecc_en_4_wd;
786 logic [3:0] bank1_info0_page_cfg_4_he_en_4_qs;
787 logic [3:0] bank1_info0_page_cfg_4_he_en_4_wd;
788 logic bank1_info0_page_cfg_5_we;
789 logic [3:0] bank1_info0_page_cfg_5_en_5_qs;
790 logic [3:0] bank1_info0_page_cfg_5_en_5_wd;
791 logic [3:0] bank1_info0_page_cfg_5_rd_en_5_qs;
792 logic [3:0] bank1_info0_page_cfg_5_rd_en_5_wd;
793 logic [3:0] bank1_info0_page_cfg_5_prog_en_5_qs;
794 logic [3:0] bank1_info0_page_cfg_5_prog_en_5_wd;
795 logic [3:0] bank1_info0_page_cfg_5_erase_en_5_qs;
796 logic [3:0] bank1_info0_page_cfg_5_erase_en_5_wd;
797 logic [3:0] bank1_info0_page_cfg_5_scramble_en_5_qs;
798 logic [3:0] bank1_info0_page_cfg_5_scramble_en_5_wd;
799 logic [3:0] bank1_info0_page_cfg_5_ecc_en_5_qs;
800 logic [3:0] bank1_info0_page_cfg_5_ecc_en_5_wd;
801 logic [3:0] bank1_info0_page_cfg_5_he_en_5_qs;
802 logic [3:0] bank1_info0_page_cfg_5_he_en_5_wd;
803 logic bank1_info0_page_cfg_6_we;
804 logic [3:0] bank1_info0_page_cfg_6_en_6_qs;
805 logic [3:0] bank1_info0_page_cfg_6_en_6_wd;
806 logic [3:0] bank1_info0_page_cfg_6_rd_en_6_qs;
807 logic [3:0] bank1_info0_page_cfg_6_rd_en_6_wd;
808 logic [3:0] bank1_info0_page_cfg_6_prog_en_6_qs;
809 logic [3:0] bank1_info0_page_cfg_6_prog_en_6_wd;
810 logic [3:0] bank1_info0_page_cfg_6_erase_en_6_qs;
811 logic [3:0] bank1_info0_page_cfg_6_erase_en_6_wd;
812 logic [3:0] bank1_info0_page_cfg_6_scramble_en_6_qs;
813 logic [3:0] bank1_info0_page_cfg_6_scramble_en_6_wd;
814 logic [3:0] bank1_info0_page_cfg_6_ecc_en_6_qs;
815 logic [3:0] bank1_info0_page_cfg_6_ecc_en_6_wd;
816 logic [3:0] bank1_info0_page_cfg_6_he_en_6_qs;
817 logic [3:0] bank1_info0_page_cfg_6_he_en_6_wd;
818 logic bank1_info0_page_cfg_7_we;
819 logic [3:0] bank1_info0_page_cfg_7_en_7_qs;
820 logic [3:0] bank1_info0_page_cfg_7_en_7_wd;
821 logic [3:0] bank1_info0_page_cfg_7_rd_en_7_qs;
822 logic [3:0] bank1_info0_page_cfg_7_rd_en_7_wd;
823 logic [3:0] bank1_info0_page_cfg_7_prog_en_7_qs;
824 logic [3:0] bank1_info0_page_cfg_7_prog_en_7_wd;
825 logic [3:0] bank1_info0_page_cfg_7_erase_en_7_qs;
826 logic [3:0] bank1_info0_page_cfg_7_erase_en_7_wd;
827 logic [3:0] bank1_info0_page_cfg_7_scramble_en_7_qs;
828 logic [3:0] bank1_info0_page_cfg_7_scramble_en_7_wd;
829 logic [3:0] bank1_info0_page_cfg_7_ecc_en_7_qs;
830 logic [3:0] bank1_info0_page_cfg_7_ecc_en_7_wd;
831 logic [3:0] bank1_info0_page_cfg_7_he_en_7_qs;
832 logic [3:0] bank1_info0_page_cfg_7_he_en_7_wd;
833 logic bank1_info0_page_cfg_8_we;
834 logic [3:0] bank1_info0_page_cfg_8_en_8_qs;
835 logic [3:0] bank1_info0_page_cfg_8_en_8_wd;
836 logic [3:0] bank1_info0_page_cfg_8_rd_en_8_qs;
837 logic [3:0] bank1_info0_page_cfg_8_rd_en_8_wd;
838 logic [3:0] bank1_info0_page_cfg_8_prog_en_8_qs;
839 logic [3:0] bank1_info0_page_cfg_8_prog_en_8_wd;
840 logic [3:0] bank1_info0_page_cfg_8_erase_en_8_qs;
841 logic [3:0] bank1_info0_page_cfg_8_erase_en_8_wd;
842 logic [3:0] bank1_info0_page_cfg_8_scramble_en_8_qs;
843 logic [3:0] bank1_info0_page_cfg_8_scramble_en_8_wd;
844 logic [3:0] bank1_info0_page_cfg_8_ecc_en_8_qs;
845 logic [3:0] bank1_info0_page_cfg_8_ecc_en_8_wd;
846 logic [3:0] bank1_info0_page_cfg_8_he_en_8_qs;
847 logic [3:0] bank1_info0_page_cfg_8_he_en_8_wd;
848 logic bank1_info0_page_cfg_9_we;
849 logic [3:0] bank1_info0_page_cfg_9_en_9_qs;
850 logic [3:0] bank1_info0_page_cfg_9_en_9_wd;
851 logic [3:0] bank1_info0_page_cfg_9_rd_en_9_qs;
852 logic [3:0] bank1_info0_page_cfg_9_rd_en_9_wd;
853 logic [3:0] bank1_info0_page_cfg_9_prog_en_9_qs;
854 logic [3:0] bank1_info0_page_cfg_9_prog_en_9_wd;
855 logic [3:0] bank1_info0_page_cfg_9_erase_en_9_qs;
856 logic [3:0] bank1_info0_page_cfg_9_erase_en_9_wd;
857 logic [3:0] bank1_info0_page_cfg_9_scramble_en_9_qs;
858 logic [3:0] bank1_info0_page_cfg_9_scramble_en_9_wd;
859 logic [3:0] bank1_info0_page_cfg_9_ecc_en_9_qs;
860 logic [3:0] bank1_info0_page_cfg_9_ecc_en_9_wd;
861 logic [3:0] bank1_info0_page_cfg_9_he_en_9_qs;
862 logic [3:0] bank1_info0_page_cfg_9_he_en_9_wd;
863 logic bank1_info1_regwen_we;
864 logic bank1_info1_regwen_qs;
865 logic bank1_info1_regwen_wd;
866 logic bank1_info1_page_cfg_we;
867 logic [3:0] bank1_info1_page_cfg_en_0_qs;
868 logic [3:0] bank1_info1_page_cfg_en_0_wd;
869 logic [3:0] bank1_info1_page_cfg_rd_en_0_qs;
870 logic [3:0] bank1_info1_page_cfg_rd_en_0_wd;
871 logic [3:0] bank1_info1_page_cfg_prog_en_0_qs;
872 logic [3:0] bank1_info1_page_cfg_prog_en_0_wd;
873 logic [3:0] bank1_info1_page_cfg_erase_en_0_qs;
874 logic [3:0] bank1_info1_page_cfg_erase_en_0_wd;
875 logic [3:0] bank1_info1_page_cfg_scramble_en_0_qs;
876 logic [3:0] bank1_info1_page_cfg_scramble_en_0_wd;
877 logic [3:0] bank1_info1_page_cfg_ecc_en_0_qs;
878 logic [3:0] bank1_info1_page_cfg_ecc_en_0_wd;
879 logic [3:0] bank1_info1_page_cfg_he_en_0_qs;
880 logic [3:0] bank1_info1_page_cfg_he_en_0_wd;
881 logic bank1_info2_regwen_0_we;
882 logic bank1_info2_regwen_0_qs;
883 logic bank1_info2_regwen_0_wd;
884 logic bank1_info2_regwen_1_we;
885 logic bank1_info2_regwen_1_qs;
886 logic bank1_info2_regwen_1_wd;
887 logic bank1_info2_page_cfg_0_we;
888 logic [3:0] bank1_info2_page_cfg_0_en_0_qs;
889 logic [3:0] bank1_info2_page_cfg_0_en_0_wd;
890 logic [3:0] bank1_info2_page_cfg_0_rd_en_0_qs;
891 logic [3:0] bank1_info2_page_cfg_0_rd_en_0_wd;
892 logic [3:0] bank1_info2_page_cfg_0_prog_en_0_qs;
893 logic [3:0] bank1_info2_page_cfg_0_prog_en_0_wd;
894 logic [3:0] bank1_info2_page_cfg_0_erase_en_0_qs;
895 logic [3:0] bank1_info2_page_cfg_0_erase_en_0_wd;
896 logic [3:0] bank1_info2_page_cfg_0_scramble_en_0_qs;
897 logic [3:0] bank1_info2_page_cfg_0_scramble_en_0_wd;
898 logic [3:0] bank1_info2_page_cfg_0_ecc_en_0_qs;
899 logic [3:0] bank1_info2_page_cfg_0_ecc_en_0_wd;
900 logic [3:0] bank1_info2_page_cfg_0_he_en_0_qs;
901 logic [3:0] bank1_info2_page_cfg_0_he_en_0_wd;
902 logic bank1_info2_page_cfg_1_we;
903 logic [3:0] bank1_info2_page_cfg_1_en_1_qs;
904 logic [3:0] bank1_info2_page_cfg_1_en_1_wd;
905 logic [3:0] bank1_info2_page_cfg_1_rd_en_1_qs;
906 logic [3:0] bank1_info2_page_cfg_1_rd_en_1_wd;
907 logic [3:0] bank1_info2_page_cfg_1_prog_en_1_qs;
908 logic [3:0] bank1_info2_page_cfg_1_prog_en_1_wd;
909 logic [3:0] bank1_info2_page_cfg_1_erase_en_1_qs;
910 logic [3:0] bank1_info2_page_cfg_1_erase_en_1_wd;
911 logic [3:0] bank1_info2_page_cfg_1_scramble_en_1_qs;
912 logic [3:0] bank1_info2_page_cfg_1_scramble_en_1_wd;
913 logic [3:0] bank1_info2_page_cfg_1_ecc_en_1_qs;
914 logic [3:0] bank1_info2_page_cfg_1_ecc_en_1_wd;
915 logic [3:0] bank1_info2_page_cfg_1_he_en_1_qs;
916 logic [3:0] bank1_info2_page_cfg_1_he_en_1_wd;
917 logic hw_info_cfg_override_we;
918 logic [3:0] hw_info_cfg_override_scramble_dis_qs;
919 logic [3:0] hw_info_cfg_override_scramble_dis_wd;
920 logic [3:0] hw_info_cfg_override_ecc_dis_qs;
921 logic [3:0] hw_info_cfg_override_ecc_dis_wd;
922 logic bank_cfg_regwen_we;
923 logic bank_cfg_regwen_qs;
924 logic bank_cfg_regwen_wd;
925 logic mp_bank_cfg_shadowed_re;
926 logic mp_bank_cfg_shadowed_we;
927 logic mp_bank_cfg_shadowed_erase_en_0_qs;
928 logic mp_bank_cfg_shadowed_erase_en_0_wd;
929 logic mp_bank_cfg_shadowed_erase_en_0_storage_err;
930 logic mp_bank_cfg_shadowed_erase_en_0_update_err;
931 logic mp_bank_cfg_shadowed_erase_en_1_qs;
932 logic mp_bank_cfg_shadowed_erase_en_1_wd;
933 logic mp_bank_cfg_shadowed_erase_en_1_storage_err;
934 logic mp_bank_cfg_shadowed_erase_en_1_update_err;
935 logic op_status_we;
936 logic op_status_done_qs;
937 logic op_status_done_wd;
938 logic op_status_err_qs;
939 logic op_status_err_wd;
940 logic status_rd_full_qs;
941 logic status_rd_empty_qs;
942 logic status_prog_full_qs;
943 logic status_prog_empty_qs;
944 logic status_init_wip_qs;
945 logic status_initialized_qs;
946 logic debug_state_re;
947 logic [10:0] debug_state_qs;
948 logic err_code_we;
949 logic err_code_op_err_qs;
950 logic err_code_op_err_wd;
951 logic err_code_mp_err_qs;
952 logic err_code_mp_err_wd;
953 logic err_code_rd_err_qs;
954 logic err_code_rd_err_wd;
955 logic err_code_prog_err_qs;
956 logic err_code_prog_err_wd;
957 logic err_code_prog_win_err_qs;
958 logic err_code_prog_win_err_wd;
959 logic err_code_prog_type_err_qs;
960 logic err_code_prog_type_err_wd;
961 logic err_code_update_err_qs;
962 logic err_code_update_err_wd;
963 logic err_code_macro_err_qs;
964 logic err_code_macro_err_wd;
965 logic std_fault_status_reg_intg_err_qs;
966 logic std_fault_status_prog_intg_err_qs;
967 logic std_fault_status_lcmgr_err_qs;
968 logic std_fault_status_lcmgr_intg_err_qs;
969 logic std_fault_status_arb_fsm_err_qs;
970 logic std_fault_status_storage_err_qs;
971 logic std_fault_status_phy_fsm_err_qs;
972 logic std_fault_status_ctrl_cnt_err_qs;
973 logic std_fault_status_fifo_err_qs;
974 logic fault_status_we;
975 logic fault_status_op_err_qs;
976 logic fault_status_mp_err_qs;
977 logic fault_status_rd_err_qs;
978 logic fault_status_prog_err_qs;
979 logic fault_status_prog_win_err_qs;
980 logic fault_status_prog_type_err_qs;
981 logic fault_status_seed_err_qs;
982 logic fault_status_phy_relbl_err_qs;
983 logic fault_status_phy_relbl_err_wd;
984 logic fault_status_phy_storage_err_qs;
985 logic fault_status_phy_storage_err_wd;
986 logic fault_status_spurious_ack_qs;
987 logic fault_status_arb_err_qs;
988 logic fault_status_host_gnt_err_qs;
989 logic [19:0] err_addr_qs;
990 logic ecc_single_err_cnt_we;
991 logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
992 logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_0_wd;
993 logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
994 logic [7:0] ecc_single_err_cnt_ecc_single_err_cnt_1_wd;
995 logic [19:0] ecc_single_err_addr_0_qs;
996 logic [19:0] ecc_single_err_addr_1_qs;
997 logic phy_alert_cfg_we;
998 logic phy_alert_cfg_alert_ack_qs;
999 logic phy_alert_cfg_alert_ack_wd;
1000 logic phy_alert_cfg_alert_trig_qs;
1001 logic phy_alert_cfg_alert_trig_wd;
1002 logic phy_status_init_wip_qs;
1003 logic phy_status_prog_normal_avail_qs;
1004 logic phy_status_prog_repair_avail_qs;
1005 logic scratch_we;
1006 logic [31:0] scratch_qs;
1007 logic [31:0] scratch_wd;
1008 logic fifo_lvl_we;
1009 logic [4:0] fifo_lvl_prog_qs;
1010 logic [4:0] fifo_lvl_prog_wd;
1011 logic [4:0] fifo_lvl_rd_qs;
1012 logic [4:0] fifo_lvl_rd_wd;
1013 logic fifo_rst_we;
1014 logic fifo_rst_qs;
1015 logic fifo_rst_wd;
1016 logic curr_fifo_lvl_re;
1017 logic [4:0] curr_fifo_lvl_prog_qs;
1018 logic [4:0] curr_fifo_lvl_rd_qs;
1019
1020 // Register instances
1021 // R[intr_state]: V(False)
1022 // F[prog_empty]: 0:0
1023 prim_subreg #(
1024 .DW (1),
1025 .SwAccess(prim_subreg_pkg::SwAccessRO),
1026 .RESVAL (1'h1),
1027 .Mubi (1'b0)
1028 ) u_intr_state_prog_empty (
1029 .clk_i (clk_i),
1030 .rst_ni (rst_ni),
1031
1032 // from register interface
1033 .we (1'b0),
1034 .wd ('0),
1035
1036 // from internal hardware
1037 .de (hw2reg.intr_state.prog_empty.de),
1038 .d (hw2reg.intr_state.prog_empty.d),
1039
1040 // to internal hardware
1041 .qe (),
1042 .q (reg2hw.intr_state.prog_empty.q),
1043 .ds (),
1044
1045 // to register interface (read)
1046 .qs (intr_state_prog_empty_qs)
1047 );
1048
1049 // F[prog_lvl]: 1:1
1050 prim_subreg #(
1051 .DW (1),
1052 .SwAccess(prim_subreg_pkg::SwAccessRO),
1053 .RESVAL (1'h1),
1054 .Mubi (1'b0)
1055 ) u_intr_state_prog_lvl (
1056 .clk_i (clk_i),
1057 .rst_ni (rst_ni),
1058
1059 // from register interface
1060 .we (1'b0),
1061 .wd ('0),
1062
1063 // from internal hardware
1064 .de (hw2reg.intr_state.prog_lvl.de),
1065 .d (hw2reg.intr_state.prog_lvl.d),
1066
1067 // to internal hardware
1068 .qe (),
1069 .q (reg2hw.intr_state.prog_lvl.q),
1070 .ds (),
1071
1072 // to register interface (read)
1073 .qs (intr_state_prog_lvl_qs)
1074 );
1075
1076 // F[rd_full]: 2:2
1077 prim_subreg #(
1078 .DW (1),
1079 .SwAccess(prim_subreg_pkg::SwAccessRO),
1080 .RESVAL (1'h0),
1081 .Mubi (1'b0)
1082 ) u_intr_state_rd_full (
1083 .clk_i (clk_i),
1084 .rst_ni (rst_ni),
1085
1086 // from register interface
1087 .we (1'b0),
1088 .wd ('0),
1089
1090 // from internal hardware
1091 .de (hw2reg.intr_state.rd_full.de),
1092 .d (hw2reg.intr_state.rd_full.d),
1093
1094 // to internal hardware
1095 .qe (),
1096 .q (reg2hw.intr_state.rd_full.q),
1097 .ds (),
1098
1099 // to register interface (read)
1100 .qs (intr_state_rd_full_qs)
1101 );
1102
1103 // F[rd_lvl]: 3:3
1104 prim_subreg #(
1105 .DW (1),
1106 .SwAccess(prim_subreg_pkg::SwAccessRO),
1107 .RESVAL (1'h0),
1108 .Mubi (1'b0)
1109 ) u_intr_state_rd_lvl (
1110 .clk_i (clk_i),
1111 .rst_ni (rst_ni),
1112
1113 // from register interface
1114 .we (1'b0),
1115 .wd ('0),
1116
1117 // from internal hardware
1118 .de (hw2reg.intr_state.rd_lvl.de),
1119 .d (hw2reg.intr_state.rd_lvl.d),
1120
1121 // to internal hardware
1122 .qe (),
1123 .q (reg2hw.intr_state.rd_lvl.q),
1124 .ds (),
1125
1126 // to register interface (read)
1127 .qs (intr_state_rd_lvl_qs)
1128 );
1129
1130 // F[op_done]: 4:4
1131 prim_subreg #(
1132 .DW (1),
1133 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1134 .RESVAL (1'h0),
1135 .Mubi (1'b0)
1136 ) u_intr_state_op_done (
1137 .clk_i (clk_i),
1138 .rst_ni (rst_ni),
1139
1140 // from register interface
1141 .we (intr_state_we),
1142 .wd (intr_state_op_done_wd),
1143
1144 // from internal hardware
1145 .de (hw2reg.intr_state.op_done.de),
1146 .d (hw2reg.intr_state.op_done.d),
1147
1148 // to internal hardware
1149 .qe (),
1150 .q (reg2hw.intr_state.op_done.q),
1151 .ds (),
1152
1153 // to register interface (read)
1154 .qs (intr_state_op_done_qs)
1155 );
1156
1157 // F[corr_err]: 5:5
1158 prim_subreg #(
1159 .DW (1),
1160 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1161 .RESVAL (1'h0),
1162 .Mubi (1'b0)
1163 ) u_intr_state_corr_err (
1164 .clk_i (clk_i),
1165 .rst_ni (rst_ni),
1166
1167 // from register interface
1168 .we (intr_state_we),
1169 .wd (intr_state_corr_err_wd),
1170
1171 // from internal hardware
1172 .de (hw2reg.intr_state.corr_err.de),
1173 .d (hw2reg.intr_state.corr_err.d),
1174
1175 // to internal hardware
1176 .qe (),
1177 .q (reg2hw.intr_state.corr_err.q),
1178 .ds (),
1179
1180 // to register interface (read)
1181 .qs (intr_state_corr_err_qs)
1182 );
1183
1184
1185 // R[intr_enable]: V(False)
1186 // F[prog_empty]: 0:0
1187 prim_subreg #(
1188 .DW (1),
1189 .SwAccess(prim_subreg_pkg::SwAccessRW),
1190 .RESVAL (1'h0),
1191 .Mubi (1'b0)
1192 ) u_intr_enable_prog_empty (
1193 .clk_i (clk_i),
1194 .rst_ni (rst_ni),
1195
1196 // from register interface
1197 .we (intr_enable_we),
1198 .wd (intr_enable_prog_empty_wd),
1199
1200 // from internal hardware
1201 .de (1'b0),
1202 .d ('0),
1203
1204 // to internal hardware
1205 .qe (),
1206 .q (reg2hw.intr_enable.prog_empty.q),
1207 .ds (),
1208
1209 // to register interface (read)
1210 .qs (intr_enable_prog_empty_qs)
1211 );
1212
1213 // F[prog_lvl]: 1:1
1214 prim_subreg #(
1215 .DW (1),
1216 .SwAccess(prim_subreg_pkg::SwAccessRW),
1217 .RESVAL (1'h0),
1218 .Mubi (1'b0)
1219 ) u_intr_enable_prog_lvl (
1220 .clk_i (clk_i),
1221 .rst_ni (rst_ni),
1222
1223 // from register interface
1224 .we (intr_enable_we),
1225 .wd (intr_enable_prog_lvl_wd),
1226
1227 // from internal hardware
1228 .de (1'b0),
1229 .d ('0),
1230
1231 // to internal hardware
1232 .qe (),
1233 .q (reg2hw.intr_enable.prog_lvl.q),
1234 .ds (),
1235
1236 // to register interface (read)
1237 .qs (intr_enable_prog_lvl_qs)
1238 );
1239
1240 // F[rd_full]: 2:2
1241 prim_subreg #(
1242 .DW (1),
1243 .SwAccess(prim_subreg_pkg::SwAccessRW),
1244 .RESVAL (1'h0),
1245 .Mubi (1'b0)
1246 ) u_intr_enable_rd_full (
1247 .clk_i (clk_i),
1248 .rst_ni (rst_ni),
1249
1250 // from register interface
1251 .we (intr_enable_we),
1252 .wd (intr_enable_rd_full_wd),
1253
1254 // from internal hardware
1255 .de (1'b0),
1256 .d ('0),
1257
1258 // to internal hardware
1259 .qe (),
1260 .q (reg2hw.intr_enable.rd_full.q),
1261 .ds (),
1262
1263 // to register interface (read)
1264 .qs (intr_enable_rd_full_qs)
1265 );
1266
1267 // F[rd_lvl]: 3:3
1268 prim_subreg #(
1269 .DW (1),
1270 .SwAccess(prim_subreg_pkg::SwAccessRW),
1271 .RESVAL (1'h0),
1272 .Mubi (1'b0)
1273 ) u_intr_enable_rd_lvl (
1274 .clk_i (clk_i),
1275 .rst_ni (rst_ni),
1276
1277 // from register interface
1278 .we (intr_enable_we),
1279 .wd (intr_enable_rd_lvl_wd),
1280
1281 // from internal hardware
1282 .de (1'b0),
1283 .d ('0),
1284
1285 // to internal hardware
1286 .qe (),
1287 .q (reg2hw.intr_enable.rd_lvl.q),
1288 .ds (),
1289
1290 // to register interface (read)
1291 .qs (intr_enable_rd_lvl_qs)
1292 );
1293
1294 // F[op_done]: 4:4
1295 prim_subreg #(
1296 .DW (1),
1297 .SwAccess(prim_subreg_pkg::SwAccessRW),
1298 .RESVAL (1'h0),
1299 .Mubi (1'b0)
1300 ) u_intr_enable_op_done (
1301 .clk_i (clk_i),
1302 .rst_ni (rst_ni),
1303
1304 // from register interface
1305 .we (intr_enable_we),
1306 .wd (intr_enable_op_done_wd),
1307
1308 // from internal hardware
1309 .de (1'b0),
1310 .d ('0),
1311
1312 // to internal hardware
1313 .qe (),
1314 .q (reg2hw.intr_enable.op_done.q),
1315 .ds (),
1316
1317 // to register interface (read)
1318 .qs (intr_enable_op_done_qs)
1319 );
1320
1321 // F[corr_err]: 5:5
1322 prim_subreg #(
1323 .DW (1),
1324 .SwAccess(prim_subreg_pkg::SwAccessRW),
1325 .RESVAL (1'h0),
1326 .Mubi (1'b0)
1327 ) u_intr_enable_corr_err (
1328 .clk_i (clk_i),
1329 .rst_ni (rst_ni),
1330
1331 // from register interface
1332 .we (intr_enable_we),
1333 .wd (intr_enable_corr_err_wd),
1334
1335 // from internal hardware
1336 .de (1'b0),
1337 .d ('0),
1338
1339 // to internal hardware
1340 .qe (),
1341 .q (reg2hw.intr_enable.corr_err.q),
1342 .ds (),
1343
1344 // to register interface (read)
1345 .qs (intr_enable_corr_err_qs)
1346 );
1347
1348
1349 // R[intr_test]: V(True)
1350 logic intr_test_qe;
1351 logic [5:0] intr_test_flds_we;
1352 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T266 T134 T267
1353 // F[prog_empty]: 0:0
1354 prim_subreg_ext #(
1355 .DW (1)
1356 ) u_intr_test_prog_empty (
1357 .re (1'b0),
1358 .we (intr_test_we),
1359 .wd (intr_test_prog_empty_wd),
1360 .d ('0),
1361 .qre (),
1362 .qe (intr_test_flds_we[0]),
1363 .q (reg2hw.intr_test.prog_empty.q),
1364 .ds (),
1365 .qs ()
1366 );
1367 1/1 assign reg2hw.intr_test.prog_empty.qe = intr_test_qe;
Tests: T266 T134 T267
1368
1369 // F[prog_lvl]: 1:1
1370 prim_subreg_ext #(
1371 .DW (1)
1372 ) u_intr_test_prog_lvl (
1373 .re (1'b0),
1374 .we (intr_test_we),
1375 .wd (intr_test_prog_lvl_wd),
1376 .d ('0),
1377 .qre (),
1378 .qe (intr_test_flds_we[1]),
1379 .q (reg2hw.intr_test.prog_lvl.q),
1380 .ds (),
1381 .qs ()
1382 );
1383 1/1 assign reg2hw.intr_test.prog_lvl.qe = intr_test_qe;
Tests: T266 T134 T267
1384
1385 // F[rd_full]: 2:2
1386 prim_subreg_ext #(
1387 .DW (1)
1388 ) u_intr_test_rd_full (
1389 .re (1'b0),
1390 .we (intr_test_we),
1391 .wd (intr_test_rd_full_wd),
1392 .d ('0),
1393 .qre (),
1394 .qe (intr_test_flds_we[2]),
1395 .q (reg2hw.intr_test.rd_full.q),
1396 .ds (),
1397 .qs ()
1398 );
1399 1/1 assign reg2hw.intr_test.rd_full.qe = intr_test_qe;
Tests: T266 T134 T267
1400
1401 // F[rd_lvl]: 3:3
1402 prim_subreg_ext #(
1403 .DW (1)
1404 ) u_intr_test_rd_lvl (
1405 .re (1'b0),
1406 .we (intr_test_we),
1407 .wd (intr_test_rd_lvl_wd),
1408 .d ('0),
1409 .qre (),
1410 .qe (intr_test_flds_we[3]),
1411 .q (reg2hw.intr_test.rd_lvl.q),
1412 .ds (),
1413 .qs ()
1414 );
1415 1/1 assign reg2hw.intr_test.rd_lvl.qe = intr_test_qe;
Tests: T266 T134 T267
1416
1417 // F[op_done]: 4:4
1418 prim_subreg_ext #(
1419 .DW (1)
1420 ) u_intr_test_op_done (
1421 .re (1'b0),
1422 .we (intr_test_we),
1423 .wd (intr_test_op_done_wd),
1424 .d ('0),
1425 .qre (),
1426 .qe (intr_test_flds_we[4]),
1427 .q (reg2hw.intr_test.op_done.q),
1428 .ds (),
1429 .qs ()
1430 );
1431 1/1 assign reg2hw.intr_test.op_done.qe = intr_test_qe;
Tests: T266 T134 T267
1432
1433 // F[corr_err]: 5:5
1434 prim_subreg_ext #(
1435 .DW (1)
1436 ) u_intr_test_corr_err (
1437 .re (1'b0),
1438 .we (intr_test_we),
1439 .wd (intr_test_corr_err_wd),
1440 .d ('0),
1441 .qre (),
1442 .qe (intr_test_flds_we[5]),
1443 .q (reg2hw.intr_test.corr_err.q),
1444 .ds (),
1445 .qs ()
1446 );
1447 1/1 assign reg2hw.intr_test.corr_err.qe = intr_test_qe;
Tests: T266 T134 T267
1448
1449
1450 // R[alert_test]: V(True)
1451 logic alert_test_qe;
1452 logic [4:0] alert_test_flds_we;
1453 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T120 T121 T122
1454 // F[recov_err]: 0:0
1455 prim_subreg_ext #(
1456 .DW (1)
1457 ) u_alert_test_recov_err (
1458 .re (1'b0),
1459 .we (alert_test_we),
1460 .wd (alert_test_recov_err_wd),
1461 .d ('0),
1462 .qre (),
1463 .qe (alert_test_flds_we[0]),
1464 .q (reg2hw.alert_test.recov_err.q),
1465 .ds (),
1466 .qs ()
1467 );
1468 1/1 assign reg2hw.alert_test.recov_err.qe = alert_test_qe;
Tests: T120 T121 T122
1469
1470 // F[fatal_std_err]: 1:1
1471 prim_subreg_ext #(
1472 .DW (1)
1473 ) u_alert_test_fatal_std_err (
1474 .re (1'b0),
1475 .we (alert_test_we),
1476 .wd (alert_test_fatal_std_err_wd),
1477 .d ('0),
1478 .qre (),
1479 .qe (alert_test_flds_we[1]),
1480 .q (reg2hw.alert_test.fatal_std_err.q),
1481 .ds (),
1482 .qs ()
1483 );
1484 1/1 assign reg2hw.alert_test.fatal_std_err.qe = alert_test_qe;
Tests: T120 T121 T122
1485
1486 // F[fatal_err]: 2:2
1487 prim_subreg_ext #(
1488 .DW (1)
1489 ) u_alert_test_fatal_err (
1490 .re (1'b0),
1491 .we (alert_test_we),
1492 .wd (alert_test_fatal_err_wd),
1493 .d ('0),
1494 .qre (),
1495 .qe (alert_test_flds_we[2]),
1496 .q (reg2hw.alert_test.fatal_err.q),
1497 .ds (),
1498 .qs ()
1499 );
1500 1/1 assign reg2hw.alert_test.fatal_err.qe = alert_test_qe;
Tests: T120 T121 T122
1501
1502 // F[fatal_prim_flash_alert]: 3:3
1503 prim_subreg_ext #(
1504 .DW (1)
1505 ) u_alert_test_fatal_prim_flash_alert (
1506 .re (1'b0),
1507 .we (alert_test_we),
1508 .wd (alert_test_fatal_prim_flash_alert_wd),
1509 .d ('0),
1510 .qre (),
1511 .qe (alert_test_flds_we[3]),
1512 .q (reg2hw.alert_test.fatal_prim_flash_alert.q),
1513 .ds (),
1514 .qs ()
1515 );
1516 1/1 assign reg2hw.alert_test.fatal_prim_flash_alert.qe = alert_test_qe;
Tests: T120 T121 T122
1517
1518 // F[recov_prim_flash_alert]: 4:4
1519 prim_subreg_ext #(
1520 .DW (1)
1521 ) u_alert_test_recov_prim_flash_alert (
1522 .re (1'b0),
1523 .we (alert_test_we),
1524 .wd (alert_test_recov_prim_flash_alert_wd),
1525 .d ('0),
1526 .qre (),
1527 .qe (alert_test_flds_we[4]),
1528 .q (reg2hw.alert_test.recov_prim_flash_alert.q),
1529 .ds (),
1530 .qs ()
1531 );
1532 1/1 assign reg2hw.alert_test.recov_prim_flash_alert.qe = alert_test_qe;
Tests: T120 T121 T122
1533
1534
1535 // R[dis]: V(False)
1536 prim_subreg #(
1537 .DW (4),
1538 .SwAccess(prim_subreg_pkg::SwAccessW1S),
1539 .RESVAL (4'h9),
1540 .Mubi (1'b1)
1541 ) u_dis (
1542 .clk_i (clk_i),
1543 .rst_ni (rst_ni),
1544
1545 // from register interface
1546 .we (dis_we),
1547 .wd (dis_wd),
1548
1549 // from internal hardware
1550 .de (1'b0),
1551 .d ('0),
1552
1553 // to internal hardware
1554 .qe (),
1555 .q (reg2hw.dis.q),
1556 .ds (),
1557
1558 // to register interface (read)
1559 .qs (dis_qs)
1560 );
1561
1562
1563 // R[exec]: V(False)
1564 prim_subreg #(
1565 .DW (32),
1566 .SwAccess(prim_subreg_pkg::SwAccessRW),
1567 .RESVAL (32'h0),
1568 .Mubi (1'b0)
1569 ) u_exec (
1570 .clk_i (clk_i),
1571 .rst_ni (rst_ni),
1572
1573 // from register interface
1574 .we (exec_we),
1575 .wd (exec_wd),
1576
1577 // from internal hardware
1578 .de (1'b0),
1579 .d ('0),
1580
1581 // to internal hardware
1582 .qe (),
1583 .q (reg2hw.exec.q),
1584 .ds (),
1585
1586 // to register interface (read)
1587 .qs (exec_qs)
1588 );
1589
1590
1591 // R[init]: V(False)
1592 prim_subreg #(
1593 .DW (1),
1594 .SwAccess(prim_subreg_pkg::SwAccessW1S),
1595 .RESVAL (1'h0),
1596 .Mubi (1'b0)
1597 ) u_init (
1598 .clk_i (clk_i),
1599 .rst_ni (rst_ni),
1600
1601 // from register interface
1602 .we (init_we),
1603 .wd (init_wd),
1604
1605 // from internal hardware
1606 .de (1'b0),
1607 .d ('0),
1608
1609 // to internal hardware
1610 .qe (),
1611 .q (reg2hw.init.q),
1612 .ds (),
1613
1614 // to register interface (read)
1615 .qs (init_qs)
1616 );
1617
1618
1619 // R[ctrl_regwen]: V(True)
1620 prim_subreg_ext #(
1621 .DW (1)
1622 ) u_ctrl_regwen (
1623 .re (ctrl_regwen_re),
1624 .we (1'b0),
1625 .wd ('0),
1626 .d (hw2reg.ctrl_regwen.d),
1627 .qre (),
1628 .qe (),
1629 .q (),
1630 .ds (),
1631 .qs (ctrl_regwen_qs)
1632 );
1633
1634
1635 // R[control]: V(False)
1636 // Create REGWEN-gated WE signal
1637 logic control_gated_we;
1638 1/1 assign control_gated_we = control_we & ctrl_regwen_qs;
Tests: T1 T2 T3
1639 // F[start]: 0:0
1640 prim_subreg #(
1641 .DW (1),
1642 .SwAccess(prim_subreg_pkg::SwAccessRW),
1643 .RESVAL (1'h0),
1644 .Mubi (1'b0)
1645 ) u_control_start (
1646 .clk_i (clk_i),
1647 .rst_ni (rst_ni),
1648
1649 // from register interface
1650 .we (control_gated_we),
1651 .wd (control_start_wd),
1652
1653 // from internal hardware
1654 .de (hw2reg.control.start.de),
1655 .d (hw2reg.control.start.d),
1656
1657 // to internal hardware
1658 .qe (),
1659 .q (reg2hw.control.start.q),
1660 .ds (),
1661
1662 // to register interface (read)
1663 .qs (control_start_qs)
1664 );
1665
1666 // F[op]: 5:4
1667 prim_subreg #(
1668 .DW (2),
1669 .SwAccess(prim_subreg_pkg::SwAccessRW),
1670 .RESVAL (2'h0),
1671 .Mubi (1'b0)
1672 ) u_control_op (
1673 .clk_i (clk_i),
1674 .rst_ni (rst_ni),
1675
1676 // from register interface
1677 .we (control_gated_we),
1678 .wd (control_op_wd),
1679
1680 // from internal hardware
1681 .de (1'b0),
1682 .d ('0),
1683
1684 // to internal hardware
1685 .qe (),
1686 .q (reg2hw.control.op.q),
1687 .ds (),
1688
1689 // to register interface (read)
1690 .qs (control_op_qs)
1691 );
1692
1693 // F[prog_sel]: 6:6
1694 prim_subreg #(
1695 .DW (1),
1696 .SwAccess(prim_subreg_pkg::SwAccessRW),
1697 .RESVAL (1'h0),
1698 .Mubi (1'b0)
1699 ) u_control_prog_sel (
1700 .clk_i (clk_i),
1701 .rst_ni (rst_ni),
1702
1703 // from register interface
1704 .we (control_gated_we),
1705 .wd (control_prog_sel_wd),
1706
1707 // from internal hardware
1708 .de (1'b0),
1709 .d ('0),
1710
1711 // to internal hardware
1712 .qe (),
1713 .q (reg2hw.control.prog_sel.q),
1714 .ds (),
1715
1716 // to register interface (read)
1717 .qs (control_prog_sel_qs)
1718 );
1719
1720 // F[erase_sel]: 7:7
1721 prim_subreg #(
1722 .DW (1),
1723 .SwAccess(prim_subreg_pkg::SwAccessRW),
1724 .RESVAL (1'h0),
1725 .Mubi (1'b0)
1726 ) u_control_erase_sel (
1727 .clk_i (clk_i),
1728 .rst_ni (rst_ni),
1729
1730 // from register interface
1731 .we (control_gated_we),
1732 .wd (control_erase_sel_wd),
1733
1734 // from internal hardware
1735 .de (1'b0),
1736 .d ('0),
1737
1738 // to internal hardware
1739 .qe (),
1740 .q (reg2hw.control.erase_sel.q),
1741 .ds (),
1742
1743 // to register interface (read)
1744 .qs (control_erase_sel_qs)
1745 );
1746
1747 // F[partition_sel]: 8:8
1748 prim_subreg #(
1749 .DW (1),
1750 .SwAccess(prim_subreg_pkg::SwAccessRW),
1751 .RESVAL (1'h0),
1752 .Mubi (1'b0)
1753 ) u_control_partition_sel (
1754 .clk_i (clk_i),
1755 .rst_ni (rst_ni),
1756
1757 // from register interface
1758 .we (control_gated_we),
1759 .wd (control_partition_sel_wd),
1760
1761 // from internal hardware
1762 .de (1'b0),
1763 .d ('0),
1764
1765 // to internal hardware
1766 .qe (),
1767 .q (reg2hw.control.partition_sel.q),
1768 .ds (),
1769
1770 // to register interface (read)
1771 .qs (control_partition_sel_qs)
1772 );
1773
1774 // F[info_sel]: 10:9
1775 prim_subreg #(
1776 .DW (2),
1777 .SwAccess(prim_subreg_pkg::SwAccessRW),
1778 .RESVAL (2'h0),
1779 .Mubi (1'b0)
1780 ) u_control_info_sel (
1781 .clk_i (clk_i),
1782 .rst_ni (rst_ni),
1783
1784 // from register interface
1785 .we (control_gated_we),
1786 .wd (control_info_sel_wd),
1787
1788 // from internal hardware
1789 .de (1'b0),
1790 .d ('0),
1791
1792 // to internal hardware
1793 .qe (),
1794 .q (reg2hw.control.info_sel.q),
1795 .ds (),
1796
1797 // to register interface (read)
1798 .qs (control_info_sel_qs)
1799 );
1800
1801 // F[num]: 27:16
1802 prim_subreg #(
1803 .DW (12),
1804 .SwAccess(prim_subreg_pkg::SwAccessRW),
1805 .RESVAL (12'h0),
1806 .Mubi (1'b0)
1807 ) u_control_num (
1808 .clk_i (clk_i),
1809 .rst_ni (rst_ni),
1810
1811 // from register interface
1812 .we (control_gated_we),
1813 .wd (control_num_wd),
1814
1815 // from internal hardware
1816 .de (1'b0),
1817 .d ('0),
1818
1819 // to internal hardware
1820 .qe (),
1821 .q (reg2hw.control.num.q),
1822 .ds (),
1823
1824 // to register interface (read)
1825 .qs (control_num_qs)
1826 );
1827
1828
1829 // R[addr]: V(False)
1830 // Create REGWEN-gated WE signal
1831 logic addr_gated_we;
1832 1/1 assign addr_gated_we = addr_we & ctrl_regwen_qs;
Tests: T1 T2 T3
1833 prim_subreg #(
1834 .DW (20),
1835 .SwAccess(prim_subreg_pkg::SwAccessRW),
1836 .RESVAL (20'h0),
1837 .Mubi (1'b0)
1838 ) u_addr (
1839 .clk_i (clk_i),
1840 .rst_ni (rst_ni),
1841
1842 // from register interface
1843 .we (addr_gated_we),
1844 .wd (addr_wd),
1845
1846 // from internal hardware
1847 .de (1'b0),
1848 .d ('0),
1849
1850 // to internal hardware
1851 .qe (),
1852 .q (reg2hw.addr.q),
1853 .ds (),
1854
1855 // to register interface (read)
1856 .qs (addr_qs)
1857 );
1858
1859
1860 // R[prog_type_en]: V(False)
1861 // Create REGWEN-gated WE signal
1862 logic prog_type_en_gated_we;
1863 1/1 assign prog_type_en_gated_we = prog_type_en_we & ctrl_regwen_qs;
Tests: T1 T2 T3
1864 // F[normal]: 0:0
1865 prim_subreg #(
1866 .DW (1),
1867 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1868 .RESVAL (1'h1),
1869 .Mubi (1'b0)
1870 ) u_prog_type_en_normal (
1871 .clk_i (clk_i),
1872 .rst_ni (rst_ni),
1873
1874 // from register interface
1875 .we (prog_type_en_gated_we),
1876 .wd (prog_type_en_normal_wd),
1877
1878 // from internal hardware
1879 .de (1'b0),
1880 .d ('0),
1881
1882 // to internal hardware
1883 .qe (),
1884 .q (reg2hw.prog_type_en.normal.q),
1885 .ds (),
1886
1887 // to register interface (read)
1888 .qs (prog_type_en_normal_qs)
1889 );
1890
1891 // F[repair]: 1:1
1892 prim_subreg #(
1893 .DW (1),
1894 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1895 .RESVAL (1'h1),
1896 .Mubi (1'b0)
1897 ) u_prog_type_en_repair (
1898 .clk_i (clk_i),
1899 .rst_ni (rst_ni),
1900
1901 // from register interface
1902 .we (prog_type_en_gated_we),
1903 .wd (prog_type_en_repair_wd),
1904
1905 // from internal hardware
1906 .de (1'b0),
1907 .d ('0),
1908
1909 // to internal hardware
1910 .qe (),
1911 .q (reg2hw.prog_type_en.repair.q),
1912 .ds (),
1913
1914 // to register interface (read)
1915 .qs (prog_type_en_repair_qs)
1916 );
1917
1918
1919 // R[erase_suspend]: V(False)
1920 prim_subreg #(
1921 .DW (1),
1922 .SwAccess(prim_subreg_pkg::SwAccessRW),
1923 .RESVAL (1'h0),
1924 .Mubi (1'b0)
1925 ) u_erase_suspend (
1926 .clk_i (clk_i),
1927 .rst_ni (rst_ni),
1928
1929 // from register interface
1930 .we (erase_suspend_we),
1931 .wd (erase_suspend_wd),
1932
1933 // from internal hardware
1934 .de (hw2reg.erase_suspend.de),
1935 .d (hw2reg.erase_suspend.d),
1936
1937 // to internal hardware
1938 .qe (),
1939 .q (reg2hw.erase_suspend.q),
1940 .ds (),
1941
1942 // to register interface (read)
1943 .qs (erase_suspend_qs)
1944 );
1945
1946
1947 // Subregister 0 of Multireg region_cfg_regwen
1948 // R[region_cfg_regwen_0]: V(False)
1949 prim_subreg #(
1950 .DW (1),
1951 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1952 .RESVAL (1'h1),
1953 .Mubi (1'b0)
1954 ) u_region_cfg_regwen_0 (
1955 .clk_i (clk_i),
1956 .rst_ni (rst_ni),
1957
1958 // from register interface
1959 .we (region_cfg_regwen_0_we),
1960 .wd (region_cfg_regwen_0_wd),
1961
1962 // from internal hardware
1963 .de (1'b0),
1964 .d ('0),
1965
1966 // to internal hardware
1967 .qe (),
1968 .q (),
1969 .ds (),
1970
1971 // to register interface (read)
1972 .qs (region_cfg_regwen_0_qs)
1973 );
1974
1975
1976 // Subregister 1 of Multireg region_cfg_regwen
1977 // R[region_cfg_regwen_1]: V(False)
1978 prim_subreg #(
1979 .DW (1),
1980 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1981 .RESVAL (1'h1),
1982 .Mubi (1'b0)
1983 ) u_region_cfg_regwen_1 (
1984 .clk_i (clk_i),
1985 .rst_ni (rst_ni),
1986
1987 // from register interface
1988 .we (region_cfg_regwen_1_we),
1989 .wd (region_cfg_regwen_1_wd),
1990
1991 // from internal hardware
1992 .de (1'b0),
1993 .d ('0),
1994
1995 // to internal hardware
1996 .qe (),
1997 .q (),
1998 .ds (),
1999
2000 // to register interface (read)
2001 .qs (region_cfg_regwen_1_qs)
2002 );
2003
2004
2005 // Subregister 2 of Multireg region_cfg_regwen
2006 // R[region_cfg_regwen_2]: V(False)
2007 prim_subreg #(
2008 .DW (1),
2009 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2010 .RESVAL (1'h1),
2011 .Mubi (1'b0)
2012 ) u_region_cfg_regwen_2 (
2013 .clk_i (clk_i),
2014 .rst_ni (rst_ni),
2015
2016 // from register interface
2017 .we (region_cfg_regwen_2_we),
2018 .wd (region_cfg_regwen_2_wd),
2019
2020 // from internal hardware
2021 .de (1'b0),
2022 .d ('0),
2023
2024 // to internal hardware
2025 .qe (),
2026 .q (),
2027 .ds (),
2028
2029 // to register interface (read)
2030 .qs (region_cfg_regwen_2_qs)
2031 );
2032
2033
2034 // Subregister 3 of Multireg region_cfg_regwen
2035 // R[region_cfg_regwen_3]: V(False)
2036 prim_subreg #(
2037 .DW (1),
2038 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2039 .RESVAL (1'h1),
2040 .Mubi (1'b0)
2041 ) u_region_cfg_regwen_3 (
2042 .clk_i (clk_i),
2043 .rst_ni (rst_ni),
2044
2045 // from register interface
2046 .we (region_cfg_regwen_3_we),
2047 .wd (region_cfg_regwen_3_wd),
2048
2049 // from internal hardware
2050 .de (1'b0),
2051 .d ('0),
2052
2053 // to internal hardware
2054 .qe (),
2055 .q (),
2056 .ds (),
2057
2058 // to register interface (read)
2059 .qs (region_cfg_regwen_3_qs)
2060 );
2061
2062
2063 // Subregister 4 of Multireg region_cfg_regwen
2064 // R[region_cfg_regwen_4]: V(False)
2065 prim_subreg #(
2066 .DW (1),
2067 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2068 .RESVAL (1'h1),
2069 .Mubi (1'b0)
2070 ) u_region_cfg_regwen_4 (
2071 .clk_i (clk_i),
2072 .rst_ni (rst_ni),
2073
2074 // from register interface
2075 .we (region_cfg_regwen_4_we),
2076 .wd (region_cfg_regwen_4_wd),
2077
2078 // from internal hardware
2079 .de (1'b0),
2080 .d ('0),
2081
2082 // to internal hardware
2083 .qe (),
2084 .q (),
2085 .ds (),
2086
2087 // to register interface (read)
2088 .qs (region_cfg_regwen_4_qs)
2089 );
2090
2091
2092 // Subregister 5 of Multireg region_cfg_regwen
2093 // R[region_cfg_regwen_5]: V(False)
2094 prim_subreg #(
2095 .DW (1),
2096 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2097 .RESVAL (1'h1),
2098 .Mubi (1'b0)
2099 ) u_region_cfg_regwen_5 (
2100 .clk_i (clk_i),
2101 .rst_ni (rst_ni),
2102
2103 // from register interface
2104 .we (region_cfg_regwen_5_we),
2105 .wd (region_cfg_regwen_5_wd),
2106
2107 // from internal hardware
2108 .de (1'b0),
2109 .d ('0),
2110
2111 // to internal hardware
2112 .qe (),
2113 .q (),
2114 .ds (),
2115
2116 // to register interface (read)
2117 .qs (region_cfg_regwen_5_qs)
2118 );
2119
2120
2121 // Subregister 6 of Multireg region_cfg_regwen
2122 // R[region_cfg_regwen_6]: V(False)
2123 prim_subreg #(
2124 .DW (1),
2125 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2126 .RESVAL (1'h1),
2127 .Mubi (1'b0)
2128 ) u_region_cfg_regwen_6 (
2129 .clk_i (clk_i),
2130 .rst_ni (rst_ni),
2131
2132 // from register interface
2133 .we (region_cfg_regwen_6_we),
2134 .wd (region_cfg_regwen_6_wd),
2135
2136 // from internal hardware
2137 .de (1'b0),
2138 .d ('0),
2139
2140 // to internal hardware
2141 .qe (),
2142 .q (),
2143 .ds (),
2144
2145 // to register interface (read)
2146 .qs (region_cfg_regwen_6_qs)
2147 );
2148
2149
2150 // Subregister 7 of Multireg region_cfg_regwen
2151 // R[region_cfg_regwen_7]: V(False)
2152 prim_subreg #(
2153 .DW (1),
2154 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2155 .RESVAL (1'h1),
2156 .Mubi (1'b0)
2157 ) u_region_cfg_regwen_7 (
2158 .clk_i (clk_i),
2159 .rst_ni (rst_ni),
2160
2161 // from register interface
2162 .we (region_cfg_regwen_7_we),
2163 .wd (region_cfg_regwen_7_wd),
2164
2165 // from internal hardware
2166 .de (1'b0),
2167 .d ('0),
2168
2169 // to internal hardware
2170 .qe (),
2171 .q (),
2172 .ds (),
2173
2174 // to register interface (read)
2175 .qs (region_cfg_regwen_7_qs)
2176 );
2177
2178
2179 // Subregister 0 of Multireg mp_region_cfg
2180 // R[mp_region_cfg_0]: V(False)
2181 // Create REGWEN-gated WE signal
2182 logic mp_region_cfg_0_gated_we;
2183 1/1 assign mp_region_cfg_0_gated_we = mp_region_cfg_0_we & region_cfg_regwen_0_qs;
Tests: T1 T2 T3
2184 // F[en_0]: 3:0
2185 prim_subreg #(
2186 .DW (4),
2187 .SwAccess(prim_subreg_pkg::SwAccessRW),
2188 .RESVAL (4'h9),
2189 .Mubi (1'b1)
2190 ) u_mp_region_cfg_0_en_0 (
2191 .clk_i (clk_i),
2192 .rst_ni (rst_ni),
2193
2194 // from register interface
2195 .we (mp_region_cfg_0_gated_we),
2196 .wd (mp_region_cfg_0_en_0_wd),
2197
2198 // from internal hardware
2199 .de (1'b0),
2200 .d ('0),
2201
2202 // to internal hardware
2203 .qe (),
2204 .q (reg2hw.mp_region_cfg[0].en.q),
2205 .ds (),
2206
2207 // to register interface (read)
2208 .qs (mp_region_cfg_0_en_0_qs)
2209 );
2210
2211 // F[rd_en_0]: 7:4
2212 prim_subreg #(
2213 .DW (4),
2214 .SwAccess(prim_subreg_pkg::SwAccessRW),
2215 .RESVAL (4'h9),
2216 .Mubi (1'b1)
2217 ) u_mp_region_cfg_0_rd_en_0 (
2218 .clk_i (clk_i),
2219 .rst_ni (rst_ni),
2220
2221 // from register interface
2222 .we (mp_region_cfg_0_gated_we),
2223 .wd (mp_region_cfg_0_rd_en_0_wd),
2224
2225 // from internal hardware
2226 .de (1'b0),
2227 .d ('0),
2228
2229 // to internal hardware
2230 .qe (),
2231 .q (reg2hw.mp_region_cfg[0].rd_en.q),
2232 .ds (),
2233
2234 // to register interface (read)
2235 .qs (mp_region_cfg_0_rd_en_0_qs)
2236 );
2237
2238 // F[prog_en_0]: 11:8
2239 prim_subreg #(
2240 .DW (4),
2241 .SwAccess(prim_subreg_pkg::SwAccessRW),
2242 .RESVAL (4'h9),
2243 .Mubi (1'b1)
2244 ) u_mp_region_cfg_0_prog_en_0 (
2245 .clk_i (clk_i),
2246 .rst_ni (rst_ni),
2247
2248 // from register interface
2249 .we (mp_region_cfg_0_gated_we),
2250 .wd (mp_region_cfg_0_prog_en_0_wd),
2251
2252 // from internal hardware
2253 .de (1'b0),
2254 .d ('0),
2255
2256 // to internal hardware
2257 .qe (),
2258 .q (reg2hw.mp_region_cfg[0].prog_en.q),
2259 .ds (),
2260
2261 // to register interface (read)
2262 .qs (mp_region_cfg_0_prog_en_0_qs)
2263 );
2264
2265 // F[erase_en_0]: 15:12
2266 prim_subreg #(
2267 .DW (4),
2268 .SwAccess(prim_subreg_pkg::SwAccessRW),
2269 .RESVAL (4'h9),
2270 .Mubi (1'b1)
2271 ) u_mp_region_cfg_0_erase_en_0 (
2272 .clk_i (clk_i),
2273 .rst_ni (rst_ni),
2274
2275 // from register interface
2276 .we (mp_region_cfg_0_gated_we),
2277 .wd (mp_region_cfg_0_erase_en_0_wd),
2278
2279 // from internal hardware
2280 .de (1'b0),
2281 .d ('0),
2282
2283 // to internal hardware
2284 .qe (),
2285 .q (reg2hw.mp_region_cfg[0].erase_en.q),
2286 .ds (),
2287
2288 // to register interface (read)
2289 .qs (mp_region_cfg_0_erase_en_0_qs)
2290 );
2291
2292 // F[scramble_en_0]: 19:16
2293 prim_subreg #(
2294 .DW (4),
2295 .SwAccess(prim_subreg_pkg::SwAccessRW),
2296 .RESVAL (4'h9),
2297 .Mubi (1'b1)
2298 ) u_mp_region_cfg_0_scramble_en_0 (
2299 .clk_i (clk_i),
2300 .rst_ni (rst_ni),
2301
2302 // from register interface
2303 .we (mp_region_cfg_0_gated_we),
2304 .wd (mp_region_cfg_0_scramble_en_0_wd),
2305
2306 // from internal hardware
2307 .de (1'b0),
2308 .d ('0),
2309
2310 // to internal hardware
2311 .qe (),
2312 .q (reg2hw.mp_region_cfg[0].scramble_en.q),
2313 .ds (),
2314
2315 // to register interface (read)
2316 .qs (mp_region_cfg_0_scramble_en_0_qs)
2317 );
2318
2319 // F[ecc_en_0]: 23:20
2320 prim_subreg #(
2321 .DW (4),
2322 .SwAccess(prim_subreg_pkg::SwAccessRW),
2323 .RESVAL (4'h9),
2324 .Mubi (1'b1)
2325 ) u_mp_region_cfg_0_ecc_en_0 (
2326 .clk_i (clk_i),
2327 .rst_ni (rst_ni),
2328
2329 // from register interface
2330 .we (mp_region_cfg_0_gated_we),
2331 .wd (mp_region_cfg_0_ecc_en_0_wd),
2332
2333 // from internal hardware
2334 .de (1'b0),
2335 .d ('0),
2336
2337 // to internal hardware
2338 .qe (),
2339 .q (reg2hw.mp_region_cfg[0].ecc_en.q),
2340 .ds (),
2341
2342 // to register interface (read)
2343 .qs (mp_region_cfg_0_ecc_en_0_qs)
2344 );
2345
2346 // F[he_en_0]: 27:24
2347 prim_subreg #(
2348 .DW (4),
2349 .SwAccess(prim_subreg_pkg::SwAccessRW),
2350 .RESVAL (4'h9),
2351 .Mubi (1'b1)
2352 ) u_mp_region_cfg_0_he_en_0 (
2353 .clk_i (clk_i),
2354 .rst_ni (rst_ni),
2355
2356 // from register interface
2357 .we (mp_region_cfg_0_gated_we),
2358 .wd (mp_region_cfg_0_he_en_0_wd),
2359
2360 // from internal hardware
2361 .de (1'b0),
2362 .d ('0),
2363
2364 // to internal hardware
2365 .qe (),
2366 .q (reg2hw.mp_region_cfg[0].he_en.q),
2367 .ds (),
2368
2369 // to register interface (read)
2370 .qs (mp_region_cfg_0_he_en_0_qs)
2371 );
2372
2373
2374 // Subregister 1 of Multireg mp_region_cfg
2375 // R[mp_region_cfg_1]: V(False)
2376 // Create REGWEN-gated WE signal
2377 logic mp_region_cfg_1_gated_we;
2378 1/1 assign mp_region_cfg_1_gated_we = mp_region_cfg_1_we & region_cfg_regwen_1_qs;
Tests: T1 T2 T3
2379 // F[en_1]: 3:0
2380 prim_subreg #(
2381 .DW (4),
2382 .SwAccess(prim_subreg_pkg::SwAccessRW),
2383 .RESVAL (4'h9),
2384 .Mubi (1'b1)
2385 ) u_mp_region_cfg_1_en_1 (
2386 .clk_i (clk_i),
2387 .rst_ni (rst_ni),
2388
2389 // from register interface
2390 .we (mp_region_cfg_1_gated_we),
2391 .wd (mp_region_cfg_1_en_1_wd),
2392
2393 // from internal hardware
2394 .de (1'b0),
2395 .d ('0),
2396
2397 // to internal hardware
2398 .qe (),
2399 .q (reg2hw.mp_region_cfg[1].en.q),
2400 .ds (),
2401
2402 // to register interface (read)
2403 .qs (mp_region_cfg_1_en_1_qs)
2404 );
2405
2406 // F[rd_en_1]: 7:4
2407 prim_subreg #(
2408 .DW (4),
2409 .SwAccess(prim_subreg_pkg::SwAccessRW),
2410 .RESVAL (4'h9),
2411 .Mubi (1'b1)
2412 ) u_mp_region_cfg_1_rd_en_1 (
2413 .clk_i (clk_i),
2414 .rst_ni (rst_ni),
2415
2416 // from register interface
2417 .we (mp_region_cfg_1_gated_we),
2418 .wd (mp_region_cfg_1_rd_en_1_wd),
2419
2420 // from internal hardware
2421 .de (1'b0),
2422 .d ('0),
2423
2424 // to internal hardware
2425 .qe (),
2426 .q (reg2hw.mp_region_cfg[1].rd_en.q),
2427 .ds (),
2428
2429 // to register interface (read)
2430 .qs (mp_region_cfg_1_rd_en_1_qs)
2431 );
2432
2433 // F[prog_en_1]: 11:8
2434 prim_subreg #(
2435 .DW (4),
2436 .SwAccess(prim_subreg_pkg::SwAccessRW),
2437 .RESVAL (4'h9),
2438 .Mubi (1'b1)
2439 ) u_mp_region_cfg_1_prog_en_1 (
2440 .clk_i (clk_i),
2441 .rst_ni (rst_ni),
2442
2443 // from register interface
2444 .we (mp_region_cfg_1_gated_we),
2445 .wd (mp_region_cfg_1_prog_en_1_wd),
2446
2447 // from internal hardware
2448 .de (1'b0),
2449 .d ('0),
2450
2451 // to internal hardware
2452 .qe (),
2453 .q (reg2hw.mp_region_cfg[1].prog_en.q),
2454 .ds (),
2455
2456 // to register interface (read)
2457 .qs (mp_region_cfg_1_prog_en_1_qs)
2458 );
2459
2460 // F[erase_en_1]: 15:12
2461 prim_subreg #(
2462 .DW (4),
2463 .SwAccess(prim_subreg_pkg::SwAccessRW),
2464 .RESVAL (4'h9),
2465 .Mubi (1'b1)
2466 ) u_mp_region_cfg_1_erase_en_1 (
2467 .clk_i (clk_i),
2468 .rst_ni (rst_ni),
2469
2470 // from register interface
2471 .we (mp_region_cfg_1_gated_we),
2472 .wd (mp_region_cfg_1_erase_en_1_wd),
2473
2474 // from internal hardware
2475 .de (1'b0),
2476 .d ('0),
2477
2478 // to internal hardware
2479 .qe (),
2480 .q (reg2hw.mp_region_cfg[1].erase_en.q),
2481 .ds (),
2482
2483 // to register interface (read)
2484 .qs (mp_region_cfg_1_erase_en_1_qs)
2485 );
2486
2487 // F[scramble_en_1]: 19:16
2488 prim_subreg #(
2489 .DW (4),
2490 .SwAccess(prim_subreg_pkg::SwAccessRW),
2491 .RESVAL (4'h9),
2492 .Mubi (1'b1)
2493 ) u_mp_region_cfg_1_scramble_en_1 (
2494 .clk_i (clk_i),
2495 .rst_ni (rst_ni),
2496
2497 // from register interface
2498 .we (mp_region_cfg_1_gated_we),
2499 .wd (mp_region_cfg_1_scramble_en_1_wd),
2500
2501 // from internal hardware
2502 .de (1'b0),
2503 .d ('0),
2504
2505 // to internal hardware
2506 .qe (),
2507 .q (reg2hw.mp_region_cfg[1].scramble_en.q),
2508 .ds (),
2509
2510 // to register interface (read)
2511 .qs (mp_region_cfg_1_scramble_en_1_qs)
2512 );
2513
2514 // F[ecc_en_1]: 23:20
2515 prim_subreg #(
2516 .DW (4),
2517 .SwAccess(prim_subreg_pkg::SwAccessRW),
2518 .RESVAL (4'h9),
2519 .Mubi (1'b1)
2520 ) u_mp_region_cfg_1_ecc_en_1 (
2521 .clk_i (clk_i),
2522 .rst_ni (rst_ni),
2523
2524 // from register interface
2525 .we (mp_region_cfg_1_gated_we),
2526 .wd (mp_region_cfg_1_ecc_en_1_wd),
2527
2528 // from internal hardware
2529 .de (1'b0),
2530 .d ('0),
2531
2532 // to internal hardware
2533 .qe (),
2534 .q (reg2hw.mp_region_cfg[1].ecc_en.q),
2535 .ds (),
2536
2537 // to register interface (read)
2538 .qs (mp_region_cfg_1_ecc_en_1_qs)
2539 );
2540
2541 // F[he_en_1]: 27:24
2542 prim_subreg #(
2543 .DW (4),
2544 .SwAccess(prim_subreg_pkg::SwAccessRW),
2545 .RESVAL (4'h9),
2546 .Mubi (1'b1)
2547 ) u_mp_region_cfg_1_he_en_1 (
2548 .clk_i (clk_i),
2549 .rst_ni (rst_ni),
2550
2551 // from register interface
2552 .we (mp_region_cfg_1_gated_we),
2553 .wd (mp_region_cfg_1_he_en_1_wd),
2554
2555 // from internal hardware
2556 .de (1'b0),
2557 .d ('0),
2558
2559 // to internal hardware
2560 .qe (),
2561 .q (reg2hw.mp_region_cfg[1].he_en.q),
2562 .ds (),
2563
2564 // to register interface (read)
2565 .qs (mp_region_cfg_1_he_en_1_qs)
2566 );
2567
2568
2569 // Subregister 2 of Multireg mp_region_cfg
2570 // R[mp_region_cfg_2]: V(False)
2571 // Create REGWEN-gated WE signal
2572 logic mp_region_cfg_2_gated_we;
2573 1/1 assign mp_region_cfg_2_gated_we = mp_region_cfg_2_we & region_cfg_regwen_2_qs;
Tests: T1 T2 T3
2574 // F[en_2]: 3:0
2575 prim_subreg #(
2576 .DW (4),
2577 .SwAccess(prim_subreg_pkg::SwAccessRW),
2578 .RESVAL (4'h9),
2579 .Mubi (1'b1)
2580 ) u_mp_region_cfg_2_en_2 (
2581 .clk_i (clk_i),
2582 .rst_ni (rst_ni),
2583
2584 // from register interface
2585 .we (mp_region_cfg_2_gated_we),
2586 .wd (mp_region_cfg_2_en_2_wd),
2587
2588 // from internal hardware
2589 .de (1'b0),
2590 .d ('0),
2591
2592 // to internal hardware
2593 .qe (),
2594 .q (reg2hw.mp_region_cfg[2].en.q),
2595 .ds (),
2596
2597 // to register interface (read)
2598 .qs (mp_region_cfg_2_en_2_qs)
2599 );
2600
2601 // F[rd_en_2]: 7:4
2602 prim_subreg #(
2603 .DW (4),
2604 .SwAccess(prim_subreg_pkg::SwAccessRW),
2605 .RESVAL (4'h9),
2606 .Mubi (1'b1)
2607 ) u_mp_region_cfg_2_rd_en_2 (
2608 .clk_i (clk_i),
2609 .rst_ni (rst_ni),
2610
2611 // from register interface
2612 .we (mp_region_cfg_2_gated_we),
2613 .wd (mp_region_cfg_2_rd_en_2_wd),
2614
2615 // from internal hardware
2616 .de (1'b0),
2617 .d ('0),
2618
2619 // to internal hardware
2620 .qe (),
2621 .q (reg2hw.mp_region_cfg[2].rd_en.q),
2622 .ds (),
2623
2624 // to register interface (read)
2625 .qs (mp_region_cfg_2_rd_en_2_qs)
2626 );
2627
2628 // F[prog_en_2]: 11:8
2629 prim_subreg #(
2630 .DW (4),
2631 .SwAccess(prim_subreg_pkg::SwAccessRW),
2632 .RESVAL (4'h9),
2633 .Mubi (1'b1)
2634 ) u_mp_region_cfg_2_prog_en_2 (
2635 .clk_i (clk_i),
2636 .rst_ni (rst_ni),
2637
2638 // from register interface
2639 .we (mp_region_cfg_2_gated_we),
2640 .wd (mp_region_cfg_2_prog_en_2_wd),
2641
2642 // from internal hardware
2643 .de (1'b0),
2644 .d ('0),
2645
2646 // to internal hardware
2647 .qe (),
2648 .q (reg2hw.mp_region_cfg[2].prog_en.q),
2649 .ds (),
2650
2651 // to register interface (read)
2652 .qs (mp_region_cfg_2_prog_en_2_qs)
2653 );
2654
2655 // F[erase_en_2]: 15:12
2656 prim_subreg #(
2657 .DW (4),
2658 .SwAccess(prim_subreg_pkg::SwAccessRW),
2659 .RESVAL (4'h9),
2660 .Mubi (1'b1)
2661 ) u_mp_region_cfg_2_erase_en_2 (
2662 .clk_i (clk_i),
2663 .rst_ni (rst_ni),
2664
2665 // from register interface
2666 .we (mp_region_cfg_2_gated_we),
2667 .wd (mp_region_cfg_2_erase_en_2_wd),
2668
2669 // from internal hardware
2670 .de (1'b0),
2671 .d ('0),
2672
2673 // to internal hardware
2674 .qe (),
2675 .q (reg2hw.mp_region_cfg[2].erase_en.q),
2676 .ds (),
2677
2678 // to register interface (read)
2679 .qs (mp_region_cfg_2_erase_en_2_qs)
2680 );
2681
2682 // F[scramble_en_2]: 19:16
2683 prim_subreg #(
2684 .DW (4),
2685 .SwAccess(prim_subreg_pkg::SwAccessRW),
2686 .RESVAL (4'h9),
2687 .Mubi (1'b1)
2688 ) u_mp_region_cfg_2_scramble_en_2 (
2689 .clk_i (clk_i),
2690 .rst_ni (rst_ni),
2691
2692 // from register interface
2693 .we (mp_region_cfg_2_gated_we),
2694 .wd (mp_region_cfg_2_scramble_en_2_wd),
2695
2696 // from internal hardware
2697 .de (1'b0),
2698 .d ('0),
2699
2700 // to internal hardware
2701 .qe (),
2702 .q (reg2hw.mp_region_cfg[2].scramble_en.q),
2703 .ds (),
2704
2705 // to register interface (read)
2706 .qs (mp_region_cfg_2_scramble_en_2_qs)
2707 );
2708
2709 // F[ecc_en_2]: 23:20
2710 prim_subreg #(
2711 .DW (4),
2712 .SwAccess(prim_subreg_pkg::SwAccessRW),
2713 .RESVAL (4'h9),
2714 .Mubi (1'b1)
2715 ) u_mp_region_cfg_2_ecc_en_2 (
2716 .clk_i (clk_i),
2717 .rst_ni (rst_ni),
2718
2719 // from register interface
2720 .we (mp_region_cfg_2_gated_we),
2721 .wd (mp_region_cfg_2_ecc_en_2_wd),
2722
2723 // from internal hardware
2724 .de (1'b0),
2725 .d ('0),
2726
2727 // to internal hardware
2728 .qe (),
2729 .q (reg2hw.mp_region_cfg[2].ecc_en.q),
2730 .ds (),
2731
2732 // to register interface (read)
2733 .qs (mp_region_cfg_2_ecc_en_2_qs)
2734 );
2735
2736 // F[he_en_2]: 27:24
2737 prim_subreg #(
2738 .DW (4),
2739 .SwAccess(prim_subreg_pkg::SwAccessRW),
2740 .RESVAL (4'h9),
2741 .Mubi (1'b1)
2742 ) u_mp_region_cfg_2_he_en_2 (
2743 .clk_i (clk_i),
2744 .rst_ni (rst_ni),
2745
2746 // from register interface
2747 .we (mp_region_cfg_2_gated_we),
2748 .wd (mp_region_cfg_2_he_en_2_wd),
2749
2750 // from internal hardware
2751 .de (1'b0),
2752 .d ('0),
2753
2754 // to internal hardware
2755 .qe (),
2756 .q (reg2hw.mp_region_cfg[2].he_en.q),
2757 .ds (),
2758
2759 // to register interface (read)
2760 .qs (mp_region_cfg_2_he_en_2_qs)
2761 );
2762
2763
2764 // Subregister 3 of Multireg mp_region_cfg
2765 // R[mp_region_cfg_3]: V(False)
2766 // Create REGWEN-gated WE signal
2767 logic mp_region_cfg_3_gated_we;
2768 1/1 assign mp_region_cfg_3_gated_we = mp_region_cfg_3_we & region_cfg_regwen_3_qs;
Tests: T1 T2 T3
2769 // F[en_3]: 3:0
2770 prim_subreg #(
2771 .DW (4),
2772 .SwAccess(prim_subreg_pkg::SwAccessRW),
2773 .RESVAL (4'h9),
2774 .Mubi (1'b1)
2775 ) u_mp_region_cfg_3_en_3 (
2776 .clk_i (clk_i),
2777 .rst_ni (rst_ni),
2778
2779 // from register interface
2780 .we (mp_region_cfg_3_gated_we),
2781 .wd (mp_region_cfg_3_en_3_wd),
2782
2783 // from internal hardware
2784 .de (1'b0),
2785 .d ('0),
2786
2787 // to internal hardware
2788 .qe (),
2789 .q (reg2hw.mp_region_cfg[3].en.q),
2790 .ds (),
2791
2792 // to register interface (read)
2793 .qs (mp_region_cfg_3_en_3_qs)
2794 );
2795
2796 // F[rd_en_3]: 7:4
2797 prim_subreg #(
2798 .DW (4),
2799 .SwAccess(prim_subreg_pkg::SwAccessRW),
2800 .RESVAL (4'h9),
2801 .Mubi (1'b1)
2802 ) u_mp_region_cfg_3_rd_en_3 (
2803 .clk_i (clk_i),
2804 .rst_ni (rst_ni),
2805
2806 // from register interface
2807 .we (mp_region_cfg_3_gated_we),
2808 .wd (mp_region_cfg_3_rd_en_3_wd),
2809
2810 // from internal hardware
2811 .de (1'b0),
2812 .d ('0),
2813
2814 // to internal hardware
2815 .qe (),
2816 .q (reg2hw.mp_region_cfg[3].rd_en.q),
2817 .ds (),
2818
2819 // to register interface (read)
2820 .qs (mp_region_cfg_3_rd_en_3_qs)
2821 );
2822
2823 // F[prog_en_3]: 11:8
2824 prim_subreg #(
2825 .DW (4),
2826 .SwAccess(prim_subreg_pkg::SwAccessRW),
2827 .RESVAL (4'h9),
2828 .Mubi (1'b1)
2829 ) u_mp_region_cfg_3_prog_en_3 (
2830 .clk_i (clk_i),
2831 .rst_ni (rst_ni),
2832
2833 // from register interface
2834 .we (mp_region_cfg_3_gated_we),
2835 .wd (mp_region_cfg_3_prog_en_3_wd),
2836
2837 // from internal hardware
2838 .de (1'b0),
2839 .d ('0),
2840
2841 // to internal hardware
2842 .qe (),
2843 .q (reg2hw.mp_region_cfg[3].prog_en.q),
2844 .ds (),
2845
2846 // to register interface (read)
2847 .qs (mp_region_cfg_3_prog_en_3_qs)
2848 );
2849
2850 // F[erase_en_3]: 15:12
2851 prim_subreg #(
2852 .DW (4),
2853 .SwAccess(prim_subreg_pkg::SwAccessRW),
2854 .RESVAL (4'h9),
2855 .Mubi (1'b1)
2856 ) u_mp_region_cfg_3_erase_en_3 (
2857 .clk_i (clk_i),
2858 .rst_ni (rst_ni),
2859
2860 // from register interface
2861 .we (mp_region_cfg_3_gated_we),
2862 .wd (mp_region_cfg_3_erase_en_3_wd),
2863
2864 // from internal hardware
2865 .de (1'b0),
2866 .d ('0),
2867
2868 // to internal hardware
2869 .qe (),
2870 .q (reg2hw.mp_region_cfg[3].erase_en.q),
2871 .ds (),
2872
2873 // to register interface (read)
2874 .qs (mp_region_cfg_3_erase_en_3_qs)
2875 );
2876
2877 // F[scramble_en_3]: 19:16
2878 prim_subreg #(
2879 .DW (4),
2880 .SwAccess(prim_subreg_pkg::SwAccessRW),
2881 .RESVAL (4'h9),
2882 .Mubi (1'b1)
2883 ) u_mp_region_cfg_3_scramble_en_3 (
2884 .clk_i (clk_i),
2885 .rst_ni (rst_ni),
2886
2887 // from register interface
2888 .we (mp_region_cfg_3_gated_we),
2889 .wd (mp_region_cfg_3_scramble_en_3_wd),
2890
2891 // from internal hardware
2892 .de (1'b0),
2893 .d ('0),
2894
2895 // to internal hardware
2896 .qe (),
2897 .q (reg2hw.mp_region_cfg[3].scramble_en.q),
2898 .ds (),
2899
2900 // to register interface (read)
2901 .qs (mp_region_cfg_3_scramble_en_3_qs)
2902 );
2903
2904 // F[ecc_en_3]: 23:20
2905 prim_subreg #(
2906 .DW (4),
2907 .SwAccess(prim_subreg_pkg::SwAccessRW),
2908 .RESVAL (4'h9),
2909 .Mubi (1'b1)
2910 ) u_mp_region_cfg_3_ecc_en_3 (
2911 .clk_i (clk_i),
2912 .rst_ni (rst_ni),
2913
2914 // from register interface
2915 .we (mp_region_cfg_3_gated_we),
2916 .wd (mp_region_cfg_3_ecc_en_3_wd),
2917
2918 // from internal hardware
2919 .de (1'b0),
2920 .d ('0),
2921
2922 // to internal hardware
2923 .qe (),
2924 .q (reg2hw.mp_region_cfg[3].ecc_en.q),
2925 .ds (),
2926
2927 // to register interface (read)
2928 .qs (mp_region_cfg_3_ecc_en_3_qs)
2929 );
2930
2931 // F[he_en_3]: 27:24
2932 prim_subreg #(
2933 .DW (4),
2934 .SwAccess(prim_subreg_pkg::SwAccessRW),
2935 .RESVAL (4'h9),
2936 .Mubi (1'b1)
2937 ) u_mp_region_cfg_3_he_en_3 (
2938 .clk_i (clk_i),
2939 .rst_ni (rst_ni),
2940
2941 // from register interface
2942 .we (mp_region_cfg_3_gated_we),
2943 .wd (mp_region_cfg_3_he_en_3_wd),
2944
2945 // from internal hardware
2946 .de (1'b0),
2947 .d ('0),
2948
2949 // to internal hardware
2950 .qe (),
2951 .q (reg2hw.mp_region_cfg[3].he_en.q),
2952 .ds (),
2953
2954 // to register interface (read)
2955 .qs (mp_region_cfg_3_he_en_3_qs)
2956 );
2957
2958
2959 // Subregister 4 of Multireg mp_region_cfg
2960 // R[mp_region_cfg_4]: V(False)
2961 // Create REGWEN-gated WE signal
2962 logic mp_region_cfg_4_gated_we;
2963 1/1 assign mp_region_cfg_4_gated_we = mp_region_cfg_4_we & region_cfg_regwen_4_qs;
Tests: T1 T2 T3
2964 // F[en_4]: 3:0
2965 prim_subreg #(
2966 .DW (4),
2967 .SwAccess(prim_subreg_pkg::SwAccessRW),
2968 .RESVAL (4'h9),
2969 .Mubi (1'b1)
2970 ) u_mp_region_cfg_4_en_4 (
2971 .clk_i (clk_i),
2972 .rst_ni (rst_ni),
2973
2974 // from register interface
2975 .we (mp_region_cfg_4_gated_we),
2976 .wd (mp_region_cfg_4_en_4_wd),
2977
2978 // from internal hardware
2979 .de (1'b0),
2980 .d ('0),
2981
2982 // to internal hardware
2983 .qe (),
2984 .q (reg2hw.mp_region_cfg[4].en.q),
2985 .ds (),
2986
2987 // to register interface (read)
2988 .qs (mp_region_cfg_4_en_4_qs)
2989 );
2990
2991 // F[rd_en_4]: 7:4
2992 prim_subreg #(
2993 .DW (4),
2994 .SwAccess(prim_subreg_pkg::SwAccessRW),
2995 .RESVAL (4'h9),
2996 .Mubi (1'b1)
2997 ) u_mp_region_cfg_4_rd_en_4 (
2998 .clk_i (clk_i),
2999 .rst_ni (rst_ni),
3000
3001 // from register interface
3002 .we (mp_region_cfg_4_gated_we),
3003 .wd (mp_region_cfg_4_rd_en_4_wd),
3004
3005 // from internal hardware
3006 .de (1'b0),
3007 .d ('0),
3008
3009 // to internal hardware
3010 .qe (),
3011 .q (reg2hw.mp_region_cfg[4].rd_en.q),
3012 .ds (),
3013
3014 // to register interface (read)
3015 .qs (mp_region_cfg_4_rd_en_4_qs)
3016 );
3017
3018 // F[prog_en_4]: 11:8
3019 prim_subreg #(
3020 .DW (4),
3021 .SwAccess(prim_subreg_pkg::SwAccessRW),
3022 .RESVAL (4'h9),
3023 .Mubi (1'b1)
3024 ) u_mp_region_cfg_4_prog_en_4 (
3025 .clk_i (clk_i),
3026 .rst_ni (rst_ni),
3027
3028 // from register interface
3029 .we (mp_region_cfg_4_gated_we),
3030 .wd (mp_region_cfg_4_prog_en_4_wd),
3031
3032 // from internal hardware
3033 .de (1'b0),
3034 .d ('0),
3035
3036 // to internal hardware
3037 .qe (),
3038 .q (reg2hw.mp_region_cfg[4].prog_en.q),
3039 .ds (),
3040
3041 // to register interface (read)
3042 .qs (mp_region_cfg_4_prog_en_4_qs)
3043 );
3044
3045 // F[erase_en_4]: 15:12
3046 prim_subreg #(
3047 .DW (4),
3048 .SwAccess(prim_subreg_pkg::SwAccessRW),
3049 .RESVAL (4'h9),
3050 .Mubi (1'b1)
3051 ) u_mp_region_cfg_4_erase_en_4 (
3052 .clk_i (clk_i),
3053 .rst_ni (rst_ni),
3054
3055 // from register interface
3056 .we (mp_region_cfg_4_gated_we),
3057 .wd (mp_region_cfg_4_erase_en_4_wd),
3058
3059 // from internal hardware
3060 .de (1'b0),
3061 .d ('0),
3062
3063 // to internal hardware
3064 .qe (),
3065 .q (reg2hw.mp_region_cfg[4].erase_en.q),
3066 .ds (),
3067
3068 // to register interface (read)
3069 .qs (mp_region_cfg_4_erase_en_4_qs)
3070 );
3071
3072 // F[scramble_en_4]: 19:16
3073 prim_subreg #(
3074 .DW (4),
3075 .SwAccess(prim_subreg_pkg::SwAccessRW),
3076 .RESVAL (4'h9),
3077 .Mubi (1'b1)
3078 ) u_mp_region_cfg_4_scramble_en_4 (
3079 .clk_i (clk_i),
3080 .rst_ni (rst_ni),
3081
3082 // from register interface
3083 .we (mp_region_cfg_4_gated_we),
3084 .wd (mp_region_cfg_4_scramble_en_4_wd),
3085
3086 // from internal hardware
3087 .de (1'b0),
3088 .d ('0),
3089
3090 // to internal hardware
3091 .qe (),
3092 .q (reg2hw.mp_region_cfg[4].scramble_en.q),
3093 .ds (),
3094
3095 // to register interface (read)
3096 .qs (mp_region_cfg_4_scramble_en_4_qs)
3097 );
3098
3099 // F[ecc_en_4]: 23:20
3100 prim_subreg #(
3101 .DW (4),
3102 .SwAccess(prim_subreg_pkg::SwAccessRW),
3103 .RESVAL (4'h9),
3104 .Mubi (1'b1)
3105 ) u_mp_region_cfg_4_ecc_en_4 (
3106 .clk_i (clk_i),
3107 .rst_ni (rst_ni),
3108
3109 // from register interface
3110 .we (mp_region_cfg_4_gated_we),
3111 .wd (mp_region_cfg_4_ecc_en_4_wd),
3112
3113 // from internal hardware
3114 .de (1'b0),
3115 .d ('0),
3116
3117 // to internal hardware
3118 .qe (),
3119 .q (reg2hw.mp_region_cfg[4].ecc_en.q),
3120 .ds (),
3121
3122 // to register interface (read)
3123 .qs (mp_region_cfg_4_ecc_en_4_qs)
3124 );
3125
3126 // F[he_en_4]: 27:24
3127 prim_subreg #(
3128 .DW (4),
3129 .SwAccess(prim_subreg_pkg::SwAccessRW),
3130 .RESVAL (4'h9),
3131 .Mubi (1'b1)
3132 ) u_mp_region_cfg_4_he_en_4 (
3133 .clk_i (clk_i),
3134 .rst_ni (rst_ni),
3135
3136 // from register interface
3137 .we (mp_region_cfg_4_gated_we),
3138 .wd (mp_region_cfg_4_he_en_4_wd),
3139
3140 // from internal hardware
3141 .de (1'b0),
3142 .d ('0),
3143
3144 // to internal hardware
3145 .qe (),
3146 .q (reg2hw.mp_region_cfg[4].he_en.q),
3147 .ds (),
3148
3149 // to register interface (read)
3150 .qs (mp_region_cfg_4_he_en_4_qs)
3151 );
3152
3153
3154 // Subregister 5 of Multireg mp_region_cfg
3155 // R[mp_region_cfg_5]: V(False)
3156 // Create REGWEN-gated WE signal
3157 logic mp_region_cfg_5_gated_we;
3158 1/1 assign mp_region_cfg_5_gated_we = mp_region_cfg_5_we & region_cfg_regwen_5_qs;
Tests: T1 T2 T3
3159 // F[en_5]: 3:0
3160 prim_subreg #(
3161 .DW (4),
3162 .SwAccess(prim_subreg_pkg::SwAccessRW),
3163 .RESVAL (4'h9),
3164 .Mubi (1'b1)
3165 ) u_mp_region_cfg_5_en_5 (
3166 .clk_i (clk_i),
3167 .rst_ni (rst_ni),
3168
3169 // from register interface
3170 .we (mp_region_cfg_5_gated_we),
3171 .wd (mp_region_cfg_5_en_5_wd),
3172
3173 // from internal hardware
3174 .de (1'b0),
3175 .d ('0),
3176
3177 // to internal hardware
3178 .qe (),
3179 .q (reg2hw.mp_region_cfg[5].en.q),
3180 .ds (),
3181
3182 // to register interface (read)
3183 .qs (mp_region_cfg_5_en_5_qs)
3184 );
3185
3186 // F[rd_en_5]: 7:4
3187 prim_subreg #(
3188 .DW (4),
3189 .SwAccess(prim_subreg_pkg::SwAccessRW),
3190 .RESVAL (4'h9),
3191 .Mubi (1'b1)
3192 ) u_mp_region_cfg_5_rd_en_5 (
3193 .clk_i (clk_i),
3194 .rst_ni (rst_ni),
3195
3196 // from register interface
3197 .we (mp_region_cfg_5_gated_we),
3198 .wd (mp_region_cfg_5_rd_en_5_wd),
3199
3200 // from internal hardware
3201 .de (1'b0),
3202 .d ('0),
3203
3204 // to internal hardware
3205 .qe (),
3206 .q (reg2hw.mp_region_cfg[5].rd_en.q),
3207 .ds (),
3208
3209 // to register interface (read)
3210 .qs (mp_region_cfg_5_rd_en_5_qs)
3211 );
3212
3213 // F[prog_en_5]: 11:8
3214 prim_subreg #(
3215 .DW (4),
3216 .SwAccess(prim_subreg_pkg::SwAccessRW),
3217 .RESVAL (4'h9),
3218 .Mubi (1'b1)
3219 ) u_mp_region_cfg_5_prog_en_5 (
3220 .clk_i (clk_i),
3221 .rst_ni (rst_ni),
3222
3223 // from register interface
3224 .we (mp_region_cfg_5_gated_we),
3225 .wd (mp_region_cfg_5_prog_en_5_wd),
3226
3227 // from internal hardware
3228 .de (1'b0),
3229 .d ('0),
3230
3231 // to internal hardware
3232 .qe (),
3233 .q (reg2hw.mp_region_cfg[5].prog_en.q),
3234 .ds (),
3235
3236 // to register interface (read)
3237 .qs (mp_region_cfg_5_prog_en_5_qs)
3238 );
3239
3240 // F[erase_en_5]: 15:12
3241 prim_subreg #(
3242 .DW (4),
3243 .SwAccess(prim_subreg_pkg::SwAccessRW),
3244 .RESVAL (4'h9),
3245 .Mubi (1'b1)
3246 ) u_mp_region_cfg_5_erase_en_5 (
3247 .clk_i (clk_i),
3248 .rst_ni (rst_ni),
3249
3250 // from register interface
3251 .we (mp_region_cfg_5_gated_we),
3252 .wd (mp_region_cfg_5_erase_en_5_wd),
3253
3254 // from internal hardware
3255 .de (1'b0),
3256 .d ('0),
3257
3258 // to internal hardware
3259 .qe (),
3260 .q (reg2hw.mp_region_cfg[5].erase_en.q),
3261 .ds (),
3262
3263 // to register interface (read)
3264 .qs (mp_region_cfg_5_erase_en_5_qs)
3265 );
3266
3267 // F[scramble_en_5]: 19:16
3268 prim_subreg #(
3269 .DW (4),
3270 .SwAccess(prim_subreg_pkg::SwAccessRW),
3271 .RESVAL (4'h9),
3272 .Mubi (1'b1)
3273 ) u_mp_region_cfg_5_scramble_en_5 (
3274 .clk_i (clk_i),
3275 .rst_ni (rst_ni),
3276
3277 // from register interface
3278 .we (mp_region_cfg_5_gated_we),
3279 .wd (mp_region_cfg_5_scramble_en_5_wd),
3280
3281 // from internal hardware
3282 .de (1'b0),
3283 .d ('0),
3284
3285 // to internal hardware
3286 .qe (),
3287 .q (reg2hw.mp_region_cfg[5].scramble_en.q),
3288 .ds (),
3289
3290 // to register interface (read)
3291 .qs (mp_region_cfg_5_scramble_en_5_qs)
3292 );
3293
3294 // F[ecc_en_5]: 23:20
3295 prim_subreg #(
3296 .DW (4),
3297 .SwAccess(prim_subreg_pkg::SwAccessRW),
3298 .RESVAL (4'h9),
3299 .Mubi (1'b1)
3300 ) u_mp_region_cfg_5_ecc_en_5 (
3301 .clk_i (clk_i),
3302 .rst_ni (rst_ni),
3303
3304 // from register interface
3305 .we (mp_region_cfg_5_gated_we),
3306 .wd (mp_region_cfg_5_ecc_en_5_wd),
3307
3308 // from internal hardware
3309 .de (1'b0),
3310 .d ('0),
3311
3312 // to internal hardware
3313 .qe (),
3314 .q (reg2hw.mp_region_cfg[5].ecc_en.q),
3315 .ds (),
3316
3317 // to register interface (read)
3318 .qs (mp_region_cfg_5_ecc_en_5_qs)
3319 );
3320
3321 // F[he_en_5]: 27:24
3322 prim_subreg #(
3323 .DW (4),
3324 .SwAccess(prim_subreg_pkg::SwAccessRW),
3325 .RESVAL (4'h9),
3326 .Mubi (1'b1)
3327 ) u_mp_region_cfg_5_he_en_5 (
3328 .clk_i (clk_i),
3329 .rst_ni (rst_ni),
3330
3331 // from register interface
3332 .we (mp_region_cfg_5_gated_we),
3333 .wd (mp_region_cfg_5_he_en_5_wd),
3334
3335 // from internal hardware
3336 .de (1'b0),
3337 .d ('0),
3338
3339 // to internal hardware
3340 .qe (),
3341 .q (reg2hw.mp_region_cfg[5].he_en.q),
3342 .ds (),
3343
3344 // to register interface (read)
3345 .qs (mp_region_cfg_5_he_en_5_qs)
3346 );
3347
3348
3349 // Subregister 6 of Multireg mp_region_cfg
3350 // R[mp_region_cfg_6]: V(False)
3351 // Create REGWEN-gated WE signal
3352 logic mp_region_cfg_6_gated_we;
3353 1/1 assign mp_region_cfg_6_gated_we = mp_region_cfg_6_we & region_cfg_regwen_6_qs;
Tests: T1 T2 T3
3354 // F[en_6]: 3:0
3355 prim_subreg #(
3356 .DW (4),
3357 .SwAccess(prim_subreg_pkg::SwAccessRW),
3358 .RESVAL (4'h9),
3359 .Mubi (1'b1)
3360 ) u_mp_region_cfg_6_en_6 (
3361 .clk_i (clk_i),
3362 .rst_ni (rst_ni),
3363
3364 // from register interface
3365 .we (mp_region_cfg_6_gated_we),
3366 .wd (mp_region_cfg_6_en_6_wd),
3367
3368 // from internal hardware
3369 .de (1'b0),
3370 .d ('0),
3371
3372 // to internal hardware
3373 .qe (),
3374 .q (reg2hw.mp_region_cfg[6].en.q),
3375 .ds (),
3376
3377 // to register interface (read)
3378 .qs (mp_region_cfg_6_en_6_qs)
3379 );
3380
3381 // F[rd_en_6]: 7:4
3382 prim_subreg #(
3383 .DW (4),
3384 .SwAccess(prim_subreg_pkg::SwAccessRW),
3385 .RESVAL (4'h9),
3386 .Mubi (1'b1)
3387 ) u_mp_region_cfg_6_rd_en_6 (
3388 .clk_i (clk_i),
3389 .rst_ni (rst_ni),
3390
3391 // from register interface
3392 .we (mp_region_cfg_6_gated_we),
3393 .wd (mp_region_cfg_6_rd_en_6_wd),
3394
3395 // from internal hardware
3396 .de (1'b0),
3397 .d ('0),
3398
3399 // to internal hardware
3400 .qe (),
3401 .q (reg2hw.mp_region_cfg[6].rd_en.q),
3402 .ds (),
3403
3404 // to register interface (read)
3405 .qs (mp_region_cfg_6_rd_en_6_qs)
3406 );
3407
3408 // F[prog_en_6]: 11:8
3409 prim_subreg #(
3410 .DW (4),
3411 .SwAccess(prim_subreg_pkg::SwAccessRW),
3412 .RESVAL (4'h9),
3413 .Mubi (1'b1)
3414 ) u_mp_region_cfg_6_prog_en_6 (
3415 .clk_i (clk_i),
3416 .rst_ni (rst_ni),
3417
3418 // from register interface
3419 .we (mp_region_cfg_6_gated_we),
3420 .wd (mp_region_cfg_6_prog_en_6_wd),
3421
3422 // from internal hardware
3423 .de (1'b0),
3424 .d ('0),
3425
3426 // to internal hardware
3427 .qe (),
3428 .q (reg2hw.mp_region_cfg[6].prog_en.q),
3429 .ds (),
3430
3431 // to register interface (read)
3432 .qs (mp_region_cfg_6_prog_en_6_qs)
3433 );
3434
3435 // F[erase_en_6]: 15:12
3436 prim_subreg #(
3437 .DW (4),
3438 .SwAccess(prim_subreg_pkg::SwAccessRW),
3439 .RESVAL (4'h9),
3440 .Mubi (1'b1)
3441 ) u_mp_region_cfg_6_erase_en_6 (
3442 .clk_i (clk_i),
3443 .rst_ni (rst_ni),
3444
3445 // from register interface
3446 .we (mp_region_cfg_6_gated_we),
3447 .wd (mp_region_cfg_6_erase_en_6_wd),
3448
3449 // from internal hardware
3450 .de (1'b0),
3451 .d ('0),
3452
3453 // to internal hardware
3454 .qe (),
3455 .q (reg2hw.mp_region_cfg[6].erase_en.q),
3456 .ds (),
3457
3458 // to register interface (read)
3459 .qs (mp_region_cfg_6_erase_en_6_qs)
3460 );
3461
3462 // F[scramble_en_6]: 19:16
3463 prim_subreg #(
3464 .DW (4),
3465 .SwAccess(prim_subreg_pkg::SwAccessRW),
3466 .RESVAL (4'h9),
3467 .Mubi (1'b1)
3468 ) u_mp_region_cfg_6_scramble_en_6 (
3469 .clk_i (clk_i),
3470 .rst_ni (rst_ni),
3471
3472 // from register interface
3473 .we (mp_region_cfg_6_gated_we),
3474 .wd (mp_region_cfg_6_scramble_en_6_wd),
3475
3476 // from internal hardware
3477 .de (1'b0),
3478 .d ('0),
3479
3480 // to internal hardware
3481 .qe (),
3482 .q (reg2hw.mp_region_cfg[6].scramble_en.q),
3483 .ds (),
3484
3485 // to register interface (read)
3486 .qs (mp_region_cfg_6_scramble_en_6_qs)
3487 );
3488
3489 // F[ecc_en_6]: 23:20
3490 prim_subreg #(
3491 .DW (4),
3492 .SwAccess(prim_subreg_pkg::SwAccessRW),
3493 .RESVAL (4'h9),
3494 .Mubi (1'b1)
3495 ) u_mp_region_cfg_6_ecc_en_6 (
3496 .clk_i (clk_i),
3497 .rst_ni (rst_ni),
3498
3499 // from register interface
3500 .we (mp_region_cfg_6_gated_we),
3501 .wd (mp_region_cfg_6_ecc_en_6_wd),
3502
3503 // from internal hardware
3504 .de (1'b0),
3505 .d ('0),
3506
3507 // to internal hardware
3508 .qe (),
3509 .q (reg2hw.mp_region_cfg[6].ecc_en.q),
3510 .ds (),
3511
3512 // to register interface (read)
3513 .qs (mp_region_cfg_6_ecc_en_6_qs)
3514 );
3515
3516 // F[he_en_6]: 27:24
3517 prim_subreg #(
3518 .DW (4),
3519 .SwAccess(prim_subreg_pkg::SwAccessRW),
3520 .RESVAL (4'h9),
3521 .Mubi (1'b1)
3522 ) u_mp_region_cfg_6_he_en_6 (
3523 .clk_i (clk_i),
3524 .rst_ni (rst_ni),
3525
3526 // from register interface
3527 .we (mp_region_cfg_6_gated_we),
3528 .wd (mp_region_cfg_6_he_en_6_wd),
3529
3530 // from internal hardware
3531 .de (1'b0),
3532 .d ('0),
3533
3534 // to internal hardware
3535 .qe (),
3536 .q (reg2hw.mp_region_cfg[6].he_en.q),
3537 .ds (),
3538
3539 // to register interface (read)
3540 .qs (mp_region_cfg_6_he_en_6_qs)
3541 );
3542
3543
3544 // Subregister 7 of Multireg mp_region_cfg
3545 // R[mp_region_cfg_7]: V(False)
3546 // Create REGWEN-gated WE signal
3547 logic mp_region_cfg_7_gated_we;
3548 1/1 assign mp_region_cfg_7_gated_we = mp_region_cfg_7_we & region_cfg_regwen_7_qs;
Tests: T1 T2 T3
3549 // F[en_7]: 3:0
3550 prim_subreg #(
3551 .DW (4),
3552 .SwAccess(prim_subreg_pkg::SwAccessRW),
3553 .RESVAL (4'h9),
3554 .Mubi (1'b1)
3555 ) u_mp_region_cfg_7_en_7 (
3556 .clk_i (clk_i),
3557 .rst_ni (rst_ni),
3558
3559 // from register interface
3560 .we (mp_region_cfg_7_gated_we),
3561 .wd (mp_region_cfg_7_en_7_wd),
3562
3563 // from internal hardware
3564 .de (1'b0),
3565 .d ('0),
3566
3567 // to internal hardware
3568 .qe (),
3569 .q (reg2hw.mp_region_cfg[7].en.q),
3570 .ds (),
3571
3572 // to register interface (read)
3573 .qs (mp_region_cfg_7_en_7_qs)
3574 );
3575
3576 // F[rd_en_7]: 7:4
3577 prim_subreg #(
3578 .DW (4),
3579 .SwAccess(prim_subreg_pkg::SwAccessRW),
3580 .RESVAL (4'h9),
3581 .Mubi (1'b1)
3582 ) u_mp_region_cfg_7_rd_en_7 (
3583 .clk_i (clk_i),
3584 .rst_ni (rst_ni),
3585
3586 // from register interface
3587 .we (mp_region_cfg_7_gated_we),
3588 .wd (mp_region_cfg_7_rd_en_7_wd),
3589
3590 // from internal hardware
3591 .de (1'b0),
3592 .d ('0),
3593
3594 // to internal hardware
3595 .qe (),
3596 .q (reg2hw.mp_region_cfg[7].rd_en.q),
3597 .ds (),
3598
3599 // to register interface (read)
3600 .qs (mp_region_cfg_7_rd_en_7_qs)
3601 );
3602
3603 // F[prog_en_7]: 11:8
3604 prim_subreg #(
3605 .DW (4),
3606 .SwAccess(prim_subreg_pkg::SwAccessRW),
3607 .RESVAL (4'h9),
3608 .Mubi (1'b1)
3609 ) u_mp_region_cfg_7_prog_en_7 (
3610 .clk_i (clk_i),
3611 .rst_ni (rst_ni),
3612
3613 // from register interface
3614 .we (mp_region_cfg_7_gated_we),
3615 .wd (mp_region_cfg_7_prog_en_7_wd),
3616
3617 // from internal hardware
3618 .de (1'b0),
3619 .d ('0),
3620
3621 // to internal hardware
3622 .qe (),
3623 .q (reg2hw.mp_region_cfg[7].prog_en.q),
3624 .ds (),
3625
3626 // to register interface (read)
3627 .qs (mp_region_cfg_7_prog_en_7_qs)
3628 );
3629
3630 // F[erase_en_7]: 15:12
3631 prim_subreg #(
3632 .DW (4),
3633 .SwAccess(prim_subreg_pkg::SwAccessRW),
3634 .RESVAL (4'h9),
3635 .Mubi (1'b1)
3636 ) u_mp_region_cfg_7_erase_en_7 (
3637 .clk_i (clk_i),
3638 .rst_ni (rst_ni),
3639
3640 // from register interface
3641 .we (mp_region_cfg_7_gated_we),
3642 .wd (mp_region_cfg_7_erase_en_7_wd),
3643
3644 // from internal hardware
3645 .de (1'b0),
3646 .d ('0),
3647
3648 // to internal hardware
3649 .qe (),
3650 .q (reg2hw.mp_region_cfg[7].erase_en.q),
3651 .ds (),
3652
3653 // to register interface (read)
3654 .qs (mp_region_cfg_7_erase_en_7_qs)
3655 );
3656
3657 // F[scramble_en_7]: 19:16
3658 prim_subreg #(
3659 .DW (4),
3660 .SwAccess(prim_subreg_pkg::SwAccessRW),
3661 .RESVAL (4'h9),
3662 .Mubi (1'b1)
3663 ) u_mp_region_cfg_7_scramble_en_7 (
3664 .clk_i (clk_i),
3665 .rst_ni (rst_ni),
3666
3667 // from register interface
3668 .we (mp_region_cfg_7_gated_we),
3669 .wd (mp_region_cfg_7_scramble_en_7_wd),
3670
3671 // from internal hardware
3672 .de (1'b0),
3673 .d ('0),
3674
3675 // to internal hardware
3676 .qe (),
3677 .q (reg2hw.mp_region_cfg[7].scramble_en.q),
3678 .ds (),
3679
3680 // to register interface (read)
3681 .qs (mp_region_cfg_7_scramble_en_7_qs)
3682 );
3683
3684 // F[ecc_en_7]: 23:20
3685 prim_subreg #(
3686 .DW (4),
3687 .SwAccess(prim_subreg_pkg::SwAccessRW),
3688 .RESVAL (4'h9),
3689 .Mubi (1'b1)
3690 ) u_mp_region_cfg_7_ecc_en_7 (
3691 .clk_i (clk_i),
3692 .rst_ni (rst_ni),
3693
3694 // from register interface
3695 .we (mp_region_cfg_7_gated_we),
3696 .wd (mp_region_cfg_7_ecc_en_7_wd),
3697
3698 // from internal hardware
3699 .de (1'b0),
3700 .d ('0),
3701
3702 // to internal hardware
3703 .qe (),
3704 .q (reg2hw.mp_region_cfg[7].ecc_en.q),
3705 .ds (),
3706
3707 // to register interface (read)
3708 .qs (mp_region_cfg_7_ecc_en_7_qs)
3709 );
3710
3711 // F[he_en_7]: 27:24
3712 prim_subreg #(
3713 .DW (4),
3714 .SwAccess(prim_subreg_pkg::SwAccessRW),
3715 .RESVAL (4'h9),
3716 .Mubi (1'b1)
3717 ) u_mp_region_cfg_7_he_en_7 (
3718 .clk_i (clk_i),
3719 .rst_ni (rst_ni),
3720
3721 // from register interface
3722 .we (mp_region_cfg_7_gated_we),
3723 .wd (mp_region_cfg_7_he_en_7_wd),
3724
3725 // from internal hardware
3726 .de (1'b0),
3727 .d ('0),
3728
3729 // to internal hardware
3730 .qe (),
3731 .q (reg2hw.mp_region_cfg[7].he_en.q),
3732 .ds (),
3733
3734 // to register interface (read)
3735 .qs (mp_region_cfg_7_he_en_7_qs)
3736 );
3737
3738
3739 // Subregister 0 of Multireg mp_region
3740 // R[mp_region_0]: V(False)
3741 // Create REGWEN-gated WE signal
3742 logic mp_region_0_gated_we;
3743 1/1 assign mp_region_0_gated_we = mp_region_0_we & region_cfg_regwen_0_qs;
Tests: T1 T2 T3
3744 // F[base_0]: 8:0
3745 prim_subreg #(
3746 .DW (9),
3747 .SwAccess(prim_subreg_pkg::SwAccessRW),
3748 .RESVAL (9'h0),
3749 .Mubi (1'b0)
3750 ) u_mp_region_0_base_0 (
3751 .clk_i (clk_i),
3752 .rst_ni (rst_ni),
3753
3754 // from register interface
3755 .we (mp_region_0_gated_we),
3756 .wd (mp_region_0_base_0_wd),
3757
3758 // from internal hardware
3759 .de (1'b0),
3760 .d ('0),
3761
3762 // to internal hardware
3763 .qe (),
3764 .q (reg2hw.mp_region[0].base.q),
3765 .ds (),
3766
3767 // to register interface (read)
3768 .qs (mp_region_0_base_0_qs)
3769 );
3770
3771 // F[size_0]: 18:9
3772 prim_subreg #(
3773 .DW (10),
3774 .SwAccess(prim_subreg_pkg::SwAccessRW),
3775 .RESVAL (10'h0),
3776 .Mubi (1'b0)
3777 ) u_mp_region_0_size_0 (
3778 .clk_i (clk_i),
3779 .rst_ni (rst_ni),
3780
3781 // from register interface
3782 .we (mp_region_0_gated_we),
3783 .wd (mp_region_0_size_0_wd),
3784
3785 // from internal hardware
3786 .de (1'b0),
3787 .d ('0),
3788
3789 // to internal hardware
3790 .qe (),
3791 .q (reg2hw.mp_region[0].size.q),
3792 .ds (),
3793
3794 // to register interface (read)
3795 .qs (mp_region_0_size_0_qs)
3796 );
3797
3798
3799 // Subregister 1 of Multireg mp_region
3800 // R[mp_region_1]: V(False)
3801 // Create REGWEN-gated WE signal
3802 logic mp_region_1_gated_we;
3803 1/1 assign mp_region_1_gated_we = mp_region_1_we & region_cfg_regwen_1_qs;
Tests: T1 T2 T3
3804 // F[base_1]: 8:0
3805 prim_subreg #(
3806 .DW (9),
3807 .SwAccess(prim_subreg_pkg::SwAccessRW),
3808 .RESVAL (9'h0),
3809 .Mubi (1'b0)
3810 ) u_mp_region_1_base_1 (
3811 .clk_i (clk_i),
3812 .rst_ni (rst_ni),
3813
3814 // from register interface
3815 .we (mp_region_1_gated_we),
3816 .wd (mp_region_1_base_1_wd),
3817
3818 // from internal hardware
3819 .de (1'b0),
3820 .d ('0),
3821
3822 // to internal hardware
3823 .qe (),
3824 .q (reg2hw.mp_region[1].base.q),
3825 .ds (),
3826
3827 // to register interface (read)
3828 .qs (mp_region_1_base_1_qs)
3829 );
3830
3831 // F[size_1]: 18:9
3832 prim_subreg #(
3833 .DW (10),
3834 .SwAccess(prim_subreg_pkg::SwAccessRW),
3835 .RESVAL (10'h0),
3836 .Mubi (1'b0)
3837 ) u_mp_region_1_size_1 (
3838 .clk_i (clk_i),
3839 .rst_ni (rst_ni),
3840
3841 // from register interface
3842 .we (mp_region_1_gated_we),
3843 .wd (mp_region_1_size_1_wd),
3844
3845 // from internal hardware
3846 .de (1'b0),
3847 .d ('0),
3848
3849 // to internal hardware
3850 .qe (),
3851 .q (reg2hw.mp_region[1].size.q),
3852 .ds (),
3853
3854 // to register interface (read)
3855 .qs (mp_region_1_size_1_qs)
3856 );
3857
3858
3859 // Subregister 2 of Multireg mp_region
3860 // R[mp_region_2]: V(False)
3861 // Create REGWEN-gated WE signal
3862 logic mp_region_2_gated_we;
3863 1/1 assign mp_region_2_gated_we = mp_region_2_we & region_cfg_regwen_2_qs;
Tests: T1 T2 T3
3864 // F[base_2]: 8:0
3865 prim_subreg #(
3866 .DW (9),
3867 .SwAccess(prim_subreg_pkg::SwAccessRW),
3868 .RESVAL (9'h0),
3869 .Mubi (1'b0)
3870 ) u_mp_region_2_base_2 (
3871 .clk_i (clk_i),
3872 .rst_ni (rst_ni),
3873
3874 // from register interface
3875 .we (mp_region_2_gated_we),
3876 .wd (mp_region_2_base_2_wd),
3877
3878 // from internal hardware
3879 .de (1'b0),
3880 .d ('0),
3881
3882 // to internal hardware
3883 .qe (),
3884 .q (reg2hw.mp_region[2].base.q),
3885 .ds (),
3886
3887 // to register interface (read)
3888 .qs (mp_region_2_base_2_qs)
3889 );
3890
3891 // F[size_2]: 18:9
3892 prim_subreg #(
3893 .DW (10),
3894 .SwAccess(prim_subreg_pkg::SwAccessRW),
3895 .RESVAL (10'h0),
3896 .Mubi (1'b0)
3897 ) u_mp_region_2_size_2 (
3898 .clk_i (clk_i),
3899 .rst_ni (rst_ni),
3900
3901 // from register interface
3902 .we (mp_region_2_gated_we),
3903 .wd (mp_region_2_size_2_wd),
3904
3905 // from internal hardware
3906 .de (1'b0),
3907 .d ('0),
3908
3909 // to internal hardware
3910 .qe (),
3911 .q (reg2hw.mp_region[2].size.q),
3912 .ds (),
3913
3914 // to register interface (read)
3915 .qs (mp_region_2_size_2_qs)
3916 );
3917
3918
3919 // Subregister 3 of Multireg mp_region
3920 // R[mp_region_3]: V(False)
3921 // Create REGWEN-gated WE signal
3922 logic mp_region_3_gated_we;
3923 1/1 assign mp_region_3_gated_we = mp_region_3_we & region_cfg_regwen_3_qs;
Tests: T1 T2 T3
3924 // F[base_3]: 8:0
3925 prim_subreg #(
3926 .DW (9),
3927 .SwAccess(prim_subreg_pkg::SwAccessRW),
3928 .RESVAL (9'h0),
3929 .Mubi (1'b0)
3930 ) u_mp_region_3_base_3 (
3931 .clk_i (clk_i),
3932 .rst_ni (rst_ni),
3933
3934 // from register interface
3935 .we (mp_region_3_gated_we),
3936 .wd (mp_region_3_base_3_wd),
3937
3938 // from internal hardware
3939 .de (1'b0),
3940 .d ('0),
3941
3942 // to internal hardware
3943 .qe (),
3944 .q (reg2hw.mp_region[3].base.q),
3945 .ds (),
3946
3947 // to register interface (read)
3948 .qs (mp_region_3_base_3_qs)
3949 );
3950
3951 // F[size_3]: 18:9
3952 prim_subreg #(
3953 .DW (10),
3954 .SwAccess(prim_subreg_pkg::SwAccessRW),
3955 .RESVAL (10'h0),
3956 .Mubi (1'b0)
3957 ) u_mp_region_3_size_3 (
3958 .clk_i (clk_i),
3959 .rst_ni (rst_ni),
3960
3961 // from register interface
3962 .we (mp_region_3_gated_we),
3963 .wd (mp_region_3_size_3_wd),
3964
3965 // from internal hardware
3966 .de (1'b0),
3967 .d ('0),
3968
3969 // to internal hardware
3970 .qe (),
3971 .q (reg2hw.mp_region[3].size.q),
3972 .ds (),
3973
3974 // to register interface (read)
3975 .qs (mp_region_3_size_3_qs)
3976 );
3977
3978
3979 // Subregister 4 of Multireg mp_region
3980 // R[mp_region_4]: V(False)
3981 // Create REGWEN-gated WE signal
3982 logic mp_region_4_gated_we;
3983 1/1 assign mp_region_4_gated_we = mp_region_4_we & region_cfg_regwen_4_qs;
Tests: T1 T2 T3
3984 // F[base_4]: 8:0
3985 prim_subreg #(
3986 .DW (9),
3987 .SwAccess(prim_subreg_pkg::SwAccessRW),
3988 .RESVAL (9'h0),
3989 .Mubi (1'b0)
3990 ) u_mp_region_4_base_4 (
3991 .clk_i (clk_i),
3992 .rst_ni (rst_ni),
3993
3994 // from register interface
3995 .we (mp_region_4_gated_we),
3996 .wd (mp_region_4_base_4_wd),
3997
3998 // from internal hardware
3999 .de (1'b0),
4000 .d ('0),
4001
4002 // to internal hardware
4003 .qe (),
4004 .q (reg2hw.mp_region[4].base.q),
4005 .ds (),
4006
4007 // to register interface (read)
4008 .qs (mp_region_4_base_4_qs)
4009 );
4010
4011 // F[size_4]: 18:9
4012 prim_subreg #(
4013 .DW (10),
4014 .SwAccess(prim_subreg_pkg::SwAccessRW),
4015 .RESVAL (10'h0),
4016 .Mubi (1'b0)
4017 ) u_mp_region_4_size_4 (
4018 .clk_i (clk_i),
4019 .rst_ni (rst_ni),
4020
4021 // from register interface
4022 .we (mp_region_4_gated_we),
4023 .wd (mp_region_4_size_4_wd),
4024
4025 // from internal hardware
4026 .de (1'b0),
4027 .d ('0),
4028
4029 // to internal hardware
4030 .qe (),
4031 .q (reg2hw.mp_region[4].size.q),
4032 .ds (),
4033
4034 // to register interface (read)
4035 .qs (mp_region_4_size_4_qs)
4036 );
4037
4038
4039 // Subregister 5 of Multireg mp_region
4040 // R[mp_region_5]: V(False)
4041 // Create REGWEN-gated WE signal
4042 logic mp_region_5_gated_we;
4043 1/1 assign mp_region_5_gated_we = mp_region_5_we & region_cfg_regwen_5_qs;
Tests: T1 T2 T3
4044 // F[base_5]: 8:0
4045 prim_subreg #(
4046 .DW (9),
4047 .SwAccess(prim_subreg_pkg::SwAccessRW),
4048 .RESVAL (9'h0),
4049 .Mubi (1'b0)
4050 ) u_mp_region_5_base_5 (
4051 .clk_i (clk_i),
4052 .rst_ni (rst_ni),
4053
4054 // from register interface
4055 .we (mp_region_5_gated_we),
4056 .wd (mp_region_5_base_5_wd),
4057
4058 // from internal hardware
4059 .de (1'b0),
4060 .d ('0),
4061
4062 // to internal hardware
4063 .qe (),
4064 .q (reg2hw.mp_region[5].base.q),
4065 .ds (),
4066
4067 // to register interface (read)
4068 .qs (mp_region_5_base_5_qs)
4069 );
4070
4071 // F[size_5]: 18:9
4072 prim_subreg #(
4073 .DW (10),
4074 .SwAccess(prim_subreg_pkg::SwAccessRW),
4075 .RESVAL (10'h0),
4076 .Mubi (1'b0)
4077 ) u_mp_region_5_size_5 (
4078 .clk_i (clk_i),
4079 .rst_ni (rst_ni),
4080
4081 // from register interface
4082 .we (mp_region_5_gated_we),
4083 .wd (mp_region_5_size_5_wd),
4084
4085 // from internal hardware
4086 .de (1'b0),
4087 .d ('0),
4088
4089 // to internal hardware
4090 .qe (),
4091 .q (reg2hw.mp_region[5].size.q),
4092 .ds (),
4093
4094 // to register interface (read)
4095 .qs (mp_region_5_size_5_qs)
4096 );
4097
4098
4099 // Subregister 6 of Multireg mp_region
4100 // R[mp_region_6]: V(False)
4101 // Create REGWEN-gated WE signal
4102 logic mp_region_6_gated_we;
4103 1/1 assign mp_region_6_gated_we = mp_region_6_we & region_cfg_regwen_6_qs;
Tests: T1 T2 T3
4104 // F[base_6]: 8:0
4105 prim_subreg #(
4106 .DW (9),
4107 .SwAccess(prim_subreg_pkg::SwAccessRW),
4108 .RESVAL (9'h0),
4109 .Mubi (1'b0)
4110 ) u_mp_region_6_base_6 (
4111 .clk_i (clk_i),
4112 .rst_ni (rst_ni),
4113
4114 // from register interface
4115 .we (mp_region_6_gated_we),
4116 .wd (mp_region_6_base_6_wd),
4117
4118 // from internal hardware
4119 .de (1'b0),
4120 .d ('0),
4121
4122 // to internal hardware
4123 .qe (),
4124 .q (reg2hw.mp_region[6].base.q),
4125 .ds (),
4126
4127 // to register interface (read)
4128 .qs (mp_region_6_base_6_qs)
4129 );
4130
4131 // F[size_6]: 18:9
4132 prim_subreg #(
4133 .DW (10),
4134 .SwAccess(prim_subreg_pkg::SwAccessRW),
4135 .RESVAL (10'h0),
4136 .Mubi (1'b0)
4137 ) u_mp_region_6_size_6 (
4138 .clk_i (clk_i),
4139 .rst_ni (rst_ni),
4140
4141 // from register interface
4142 .we (mp_region_6_gated_we),
4143 .wd (mp_region_6_size_6_wd),
4144
4145 // from internal hardware
4146 .de (1'b0),
4147 .d ('0),
4148
4149 // to internal hardware
4150 .qe (),
4151 .q (reg2hw.mp_region[6].size.q),
4152 .ds (),
4153
4154 // to register interface (read)
4155 .qs (mp_region_6_size_6_qs)
4156 );
4157
4158
4159 // Subregister 7 of Multireg mp_region
4160 // R[mp_region_7]: V(False)
4161 // Create REGWEN-gated WE signal
4162 logic mp_region_7_gated_we;
4163 1/1 assign mp_region_7_gated_we = mp_region_7_we & region_cfg_regwen_7_qs;
Tests: T1 T2 T3
4164 // F[base_7]: 8:0
4165 prim_subreg #(
4166 .DW (9),
4167 .SwAccess(prim_subreg_pkg::SwAccessRW),
4168 .RESVAL (9'h0),
4169 .Mubi (1'b0)
4170 ) u_mp_region_7_base_7 (
4171 .clk_i (clk_i),
4172 .rst_ni (rst_ni),
4173
4174 // from register interface
4175 .we (mp_region_7_gated_we),
4176 .wd (mp_region_7_base_7_wd),
4177
4178 // from internal hardware
4179 .de (1'b0),
4180 .d ('0),
4181
4182 // to internal hardware
4183 .qe (),
4184 .q (reg2hw.mp_region[7].base.q),
4185 .ds (),
4186
4187 // to register interface (read)
4188 .qs (mp_region_7_base_7_qs)
4189 );
4190
4191 // F[size_7]: 18:9
4192 prim_subreg #(
4193 .DW (10),
4194 .SwAccess(prim_subreg_pkg::SwAccessRW),
4195 .RESVAL (10'h0),
4196 .Mubi (1'b0)
4197 ) u_mp_region_7_size_7 (
4198 .clk_i (clk_i),
4199 .rst_ni (rst_ni),
4200
4201 // from register interface
4202 .we (mp_region_7_gated_we),
4203 .wd (mp_region_7_size_7_wd),
4204
4205 // from internal hardware
4206 .de (1'b0),
4207 .d ('0),
4208
4209 // to internal hardware
4210 .qe (),
4211 .q (reg2hw.mp_region[7].size.q),
4212 .ds (),
4213
4214 // to register interface (read)
4215 .qs (mp_region_7_size_7_qs)
4216 );
4217
4218
4219 // R[default_region]: V(False)
4220 // F[rd_en]: 3:0
4221 prim_subreg #(
4222 .DW (4),
4223 .SwAccess(prim_subreg_pkg::SwAccessRW),
4224 .RESVAL (4'h9),
4225 .Mubi (1'b1)
4226 ) u_default_region_rd_en (
4227 .clk_i (clk_i),
4228 .rst_ni (rst_ni),
4229
4230 // from register interface
4231 .we (default_region_we),
4232 .wd (default_region_rd_en_wd),
4233
4234 // from internal hardware
4235 .de (1'b0),
4236 .d ('0),
4237
4238 // to internal hardware
4239 .qe (),
4240 .q (reg2hw.default_region.rd_en.q),
4241 .ds (),
4242
4243 // to register interface (read)
4244 .qs (default_region_rd_en_qs)
4245 );
4246
4247 // F[prog_en]: 7:4
4248 prim_subreg #(
4249 .DW (4),
4250 .SwAccess(prim_subreg_pkg::SwAccessRW),
4251 .RESVAL (4'h9),
4252 .Mubi (1'b1)
4253 ) u_default_region_prog_en (
4254 .clk_i (clk_i),
4255 .rst_ni (rst_ni),
4256
4257 // from register interface
4258 .we (default_region_we),
4259 .wd (default_region_prog_en_wd),
4260
4261 // from internal hardware
4262 .de (1'b0),
4263 .d ('0),
4264
4265 // to internal hardware
4266 .qe (),
4267 .q (reg2hw.default_region.prog_en.q),
4268 .ds (),
4269
4270 // to register interface (read)
4271 .qs (default_region_prog_en_qs)
4272 );
4273
4274 // F[erase_en]: 11:8
4275 prim_subreg #(
4276 .DW (4),
4277 .SwAccess(prim_subreg_pkg::SwAccessRW),
4278 .RESVAL (4'h9),
4279 .Mubi (1'b1)
4280 ) u_default_region_erase_en (
4281 .clk_i (clk_i),
4282 .rst_ni (rst_ni),
4283
4284 // from register interface
4285 .we (default_region_we),
4286 .wd (default_region_erase_en_wd),
4287
4288 // from internal hardware
4289 .de (1'b0),
4290 .d ('0),
4291
4292 // to internal hardware
4293 .qe (),
4294 .q (reg2hw.default_region.erase_en.q),
4295 .ds (),
4296
4297 // to register interface (read)
4298 .qs (default_region_erase_en_qs)
4299 );
4300
4301 // F[scramble_en]: 15:12
4302 prim_subreg #(
4303 .DW (4),
4304 .SwAccess(prim_subreg_pkg::SwAccessRW),
4305 .RESVAL (4'h9),
4306 .Mubi (1'b1)
4307 ) u_default_region_scramble_en (
4308 .clk_i (clk_i),
4309 .rst_ni (rst_ni),
4310
4311 // from register interface
4312 .we (default_region_we),
4313 .wd (default_region_scramble_en_wd),
4314
4315 // from internal hardware
4316 .de (1'b0),
4317 .d ('0),
4318
4319 // to internal hardware
4320 .qe (),
4321 .q (reg2hw.default_region.scramble_en.q),
4322 .ds (),
4323
4324 // to register interface (read)
4325 .qs (default_region_scramble_en_qs)
4326 );
4327
4328 // F[ecc_en]: 19:16
4329 prim_subreg #(
4330 .DW (4),
4331 .SwAccess(prim_subreg_pkg::SwAccessRW),
4332 .RESVAL (4'h9),
4333 .Mubi (1'b1)
4334 ) u_default_region_ecc_en (
4335 .clk_i (clk_i),
4336 .rst_ni (rst_ni),
4337
4338 // from register interface
4339 .we (default_region_we),
4340 .wd (default_region_ecc_en_wd),
4341
4342 // from internal hardware
4343 .de (1'b0),
4344 .d ('0),
4345
4346 // to internal hardware
4347 .qe (),
4348 .q (reg2hw.default_region.ecc_en.q),
4349 .ds (),
4350
4351 // to register interface (read)
4352 .qs (default_region_ecc_en_qs)
4353 );
4354
4355 // F[he_en]: 23:20
4356 prim_subreg #(
4357 .DW (4),
4358 .SwAccess(prim_subreg_pkg::SwAccessRW),
4359 .RESVAL (4'h9),
4360 .Mubi (1'b1)
4361 ) u_default_region_he_en (
4362 .clk_i (clk_i),
4363 .rst_ni (rst_ni),
4364
4365 // from register interface
4366 .we (default_region_we),
4367 .wd (default_region_he_en_wd),
4368
4369 // from internal hardware
4370 .de (1'b0),
4371 .d ('0),
4372
4373 // to internal hardware
4374 .qe (),
4375 .q (reg2hw.default_region.he_en.q),
4376 .ds (),
4377
4378 // to register interface (read)
4379 .qs (default_region_he_en_qs)
4380 );
4381
4382
4383 // Subregister 0 of Multireg bank0_info0_regwen
4384 // R[bank0_info0_regwen_0]: V(False)
4385 prim_subreg #(
4386 .DW (1),
4387 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4388 .RESVAL (1'h1),
4389 .Mubi (1'b0)
4390 ) u_bank0_info0_regwen_0 (
4391 .clk_i (clk_i),
4392 .rst_ni (rst_ni),
4393
4394 // from register interface
4395 .we (bank0_info0_regwen_0_we),
4396 .wd (bank0_info0_regwen_0_wd),
4397
4398 // from internal hardware
4399 .de (1'b0),
4400 .d ('0),
4401
4402 // to internal hardware
4403 .qe (),
4404 .q (),
4405 .ds (),
4406
4407 // to register interface (read)
4408 .qs (bank0_info0_regwen_0_qs)
4409 );
4410
4411
4412 // Subregister 1 of Multireg bank0_info0_regwen
4413 // R[bank0_info0_regwen_1]: V(False)
4414 prim_subreg #(
4415 .DW (1),
4416 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4417 .RESVAL (1'h1),
4418 .Mubi (1'b0)
4419 ) u_bank0_info0_regwen_1 (
4420 .clk_i (clk_i),
4421 .rst_ni (rst_ni),
4422
4423 // from register interface
4424 .we (bank0_info0_regwen_1_we),
4425 .wd (bank0_info0_regwen_1_wd),
4426
4427 // from internal hardware
4428 .de (1'b0),
4429 .d ('0),
4430
4431 // to internal hardware
4432 .qe (),
4433 .q (),
4434 .ds (),
4435
4436 // to register interface (read)
4437 .qs (bank0_info0_regwen_1_qs)
4438 );
4439
4440
4441 // Subregister 2 of Multireg bank0_info0_regwen
4442 // R[bank0_info0_regwen_2]: V(False)
4443 prim_subreg #(
4444 .DW (1),
4445 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4446 .RESVAL (1'h1),
4447 .Mubi (1'b0)
4448 ) u_bank0_info0_regwen_2 (
4449 .clk_i (clk_i),
4450 .rst_ni (rst_ni),
4451
4452 // from register interface
4453 .we (bank0_info0_regwen_2_we),
4454 .wd (bank0_info0_regwen_2_wd),
4455
4456 // from internal hardware
4457 .de (1'b0),
4458 .d ('0),
4459
4460 // to internal hardware
4461 .qe (),
4462 .q (),
4463 .ds (),
4464
4465 // to register interface (read)
4466 .qs (bank0_info0_regwen_2_qs)
4467 );
4468
4469
4470 // Subregister 3 of Multireg bank0_info0_regwen
4471 // R[bank0_info0_regwen_3]: V(False)
4472 prim_subreg #(
4473 .DW (1),
4474 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4475 .RESVAL (1'h1),
4476 .Mubi (1'b0)
4477 ) u_bank0_info0_regwen_3 (
4478 .clk_i (clk_i),
4479 .rst_ni (rst_ni),
4480
4481 // from register interface
4482 .we (bank0_info0_regwen_3_we),
4483 .wd (bank0_info0_regwen_3_wd),
4484
4485 // from internal hardware
4486 .de (1'b0),
4487 .d ('0),
4488
4489 // to internal hardware
4490 .qe (),
4491 .q (),
4492 .ds (),
4493
4494 // to register interface (read)
4495 .qs (bank0_info0_regwen_3_qs)
4496 );
4497
4498
4499 // Subregister 4 of Multireg bank0_info0_regwen
4500 // R[bank0_info0_regwen_4]: V(False)
4501 prim_subreg #(
4502 .DW (1),
4503 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4504 .RESVAL (1'h1),
4505 .Mubi (1'b0)
4506 ) u_bank0_info0_regwen_4 (
4507 .clk_i (clk_i),
4508 .rst_ni (rst_ni),
4509
4510 // from register interface
4511 .we (bank0_info0_regwen_4_we),
4512 .wd (bank0_info0_regwen_4_wd),
4513
4514 // from internal hardware
4515 .de (1'b0),
4516 .d ('0),
4517
4518 // to internal hardware
4519 .qe (),
4520 .q (),
4521 .ds (),
4522
4523 // to register interface (read)
4524 .qs (bank0_info0_regwen_4_qs)
4525 );
4526
4527
4528 // Subregister 5 of Multireg bank0_info0_regwen
4529 // R[bank0_info0_regwen_5]: V(False)
4530 prim_subreg #(
4531 .DW (1),
4532 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4533 .RESVAL (1'h1),
4534 .Mubi (1'b0)
4535 ) u_bank0_info0_regwen_5 (
4536 .clk_i (clk_i),
4537 .rst_ni (rst_ni),
4538
4539 // from register interface
4540 .we (bank0_info0_regwen_5_we),
4541 .wd (bank0_info0_regwen_5_wd),
4542
4543 // from internal hardware
4544 .de (1'b0),
4545 .d ('0),
4546
4547 // to internal hardware
4548 .qe (),
4549 .q (),
4550 .ds (),
4551
4552 // to register interface (read)
4553 .qs (bank0_info0_regwen_5_qs)
4554 );
4555
4556
4557 // Subregister 6 of Multireg bank0_info0_regwen
4558 // R[bank0_info0_regwen_6]: V(False)
4559 prim_subreg #(
4560 .DW (1),
4561 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4562 .RESVAL (1'h1),
4563 .Mubi (1'b0)
4564 ) u_bank0_info0_regwen_6 (
4565 .clk_i (clk_i),
4566 .rst_ni (rst_ni),
4567
4568 // from register interface
4569 .we (bank0_info0_regwen_6_we),
4570 .wd (bank0_info0_regwen_6_wd),
4571
4572 // from internal hardware
4573 .de (1'b0),
4574 .d ('0),
4575
4576 // to internal hardware
4577 .qe (),
4578 .q (),
4579 .ds (),
4580
4581 // to register interface (read)
4582 .qs (bank0_info0_regwen_6_qs)
4583 );
4584
4585
4586 // Subregister 7 of Multireg bank0_info0_regwen
4587 // R[bank0_info0_regwen_7]: V(False)
4588 prim_subreg #(
4589 .DW (1),
4590 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4591 .RESVAL (1'h1),
4592 .Mubi (1'b0)
4593 ) u_bank0_info0_regwen_7 (
4594 .clk_i (clk_i),
4595 .rst_ni (rst_ni),
4596
4597 // from register interface
4598 .we (bank0_info0_regwen_7_we),
4599 .wd (bank0_info0_regwen_7_wd),
4600
4601 // from internal hardware
4602 .de (1'b0),
4603 .d ('0),
4604
4605 // to internal hardware
4606 .qe (),
4607 .q (),
4608 .ds (),
4609
4610 // to register interface (read)
4611 .qs (bank0_info0_regwen_7_qs)
4612 );
4613
4614
4615 // Subregister 8 of Multireg bank0_info0_regwen
4616 // R[bank0_info0_regwen_8]: V(False)
4617 prim_subreg #(
4618 .DW (1),
4619 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4620 .RESVAL (1'h1),
4621 .Mubi (1'b0)
4622 ) u_bank0_info0_regwen_8 (
4623 .clk_i (clk_i),
4624 .rst_ni (rst_ni),
4625
4626 // from register interface
4627 .we (bank0_info0_regwen_8_we),
4628 .wd (bank0_info0_regwen_8_wd),
4629
4630 // from internal hardware
4631 .de (1'b0),
4632 .d ('0),
4633
4634 // to internal hardware
4635 .qe (),
4636 .q (),
4637 .ds (),
4638
4639 // to register interface (read)
4640 .qs (bank0_info0_regwen_8_qs)
4641 );
4642
4643
4644 // Subregister 9 of Multireg bank0_info0_regwen
4645 // R[bank0_info0_regwen_9]: V(False)
4646 prim_subreg #(
4647 .DW (1),
4648 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4649 .RESVAL (1'h1),
4650 .Mubi (1'b0)
4651 ) u_bank0_info0_regwen_9 (
4652 .clk_i (clk_i),
4653 .rst_ni (rst_ni),
4654
4655 // from register interface
4656 .we (bank0_info0_regwen_9_we),
4657 .wd (bank0_info0_regwen_9_wd),
4658
4659 // from internal hardware
4660 .de (1'b0),
4661 .d ('0),
4662
4663 // to internal hardware
4664 .qe (),
4665 .q (),
4666 .ds (),
4667
4668 // to register interface (read)
4669 .qs (bank0_info0_regwen_9_qs)
4670 );
4671
4672
4673 // Subregister 0 of Multireg bank0_info0_page_cfg
4674 // R[bank0_info0_page_cfg_0]: V(False)
4675 // Create REGWEN-gated WE signal
4676 logic bank0_info0_page_cfg_0_gated_we;
4677 1/1 assign bank0_info0_page_cfg_0_gated_we = bank0_info0_page_cfg_0_we & bank0_info0_regwen_0_qs;
Tests: T1 T2 T3
4678 // F[en_0]: 3:0
4679 prim_subreg #(
4680 .DW (4),
4681 .SwAccess(prim_subreg_pkg::SwAccessRW),
4682 .RESVAL (4'h9),
4683 .Mubi (1'b1)
4684 ) u_bank0_info0_page_cfg_0_en_0 (
4685 .clk_i (clk_i),
4686 .rst_ni (rst_ni),
4687
4688 // from register interface
4689 .we (bank0_info0_page_cfg_0_gated_we),
4690 .wd (bank0_info0_page_cfg_0_en_0_wd),
4691
4692 // from internal hardware
4693 .de (1'b0),
4694 .d ('0),
4695
4696 // to internal hardware
4697 .qe (),
4698 .q (reg2hw.bank0_info0_page_cfg[0].en.q),
4699 .ds (),
4700
4701 // to register interface (read)
4702 .qs (bank0_info0_page_cfg_0_en_0_qs)
4703 );
4704
4705 // F[rd_en_0]: 7:4
4706 prim_subreg #(
4707 .DW (4),
4708 .SwAccess(prim_subreg_pkg::SwAccessRW),
4709 .RESVAL (4'h9),
4710 .Mubi (1'b1)
4711 ) u_bank0_info0_page_cfg_0_rd_en_0 (
4712 .clk_i (clk_i),
4713 .rst_ni (rst_ni),
4714
4715 // from register interface
4716 .we (bank0_info0_page_cfg_0_gated_we),
4717 .wd (bank0_info0_page_cfg_0_rd_en_0_wd),
4718
4719 // from internal hardware
4720 .de (1'b0),
4721 .d ('0),
4722
4723 // to internal hardware
4724 .qe (),
4725 .q (reg2hw.bank0_info0_page_cfg[0].rd_en.q),
4726 .ds (),
4727
4728 // to register interface (read)
4729 .qs (bank0_info0_page_cfg_0_rd_en_0_qs)
4730 );
4731
4732 // F[prog_en_0]: 11:8
4733 prim_subreg #(
4734 .DW (4),
4735 .SwAccess(prim_subreg_pkg::SwAccessRW),
4736 .RESVAL (4'h9),
4737 .Mubi (1'b1)
4738 ) u_bank0_info0_page_cfg_0_prog_en_0 (
4739 .clk_i (clk_i),
4740 .rst_ni (rst_ni),
4741
4742 // from register interface
4743 .we (bank0_info0_page_cfg_0_gated_we),
4744 .wd (bank0_info0_page_cfg_0_prog_en_0_wd),
4745
4746 // from internal hardware
4747 .de (1'b0),
4748 .d ('0),
4749
4750 // to internal hardware
4751 .qe (),
4752 .q (reg2hw.bank0_info0_page_cfg[0].prog_en.q),
4753 .ds (),
4754
4755 // to register interface (read)
4756 .qs (bank0_info0_page_cfg_0_prog_en_0_qs)
4757 );
4758
4759 // F[erase_en_0]: 15:12
4760 prim_subreg #(
4761 .DW (4),
4762 .SwAccess(prim_subreg_pkg::SwAccessRW),
4763 .RESVAL (4'h9),
4764 .Mubi (1'b1)
4765 ) u_bank0_info0_page_cfg_0_erase_en_0 (
4766 .clk_i (clk_i),
4767 .rst_ni (rst_ni),
4768
4769 // from register interface
4770 .we (bank0_info0_page_cfg_0_gated_we),
4771 .wd (bank0_info0_page_cfg_0_erase_en_0_wd),
4772
4773 // from internal hardware
4774 .de (1'b0),
4775 .d ('0),
4776
4777 // to internal hardware
4778 .qe (),
4779 .q (reg2hw.bank0_info0_page_cfg[0].erase_en.q),
4780 .ds (),
4781
4782 // to register interface (read)
4783 .qs (bank0_info0_page_cfg_0_erase_en_0_qs)
4784 );
4785
4786 // F[scramble_en_0]: 19:16
4787 prim_subreg #(
4788 .DW (4),
4789 .SwAccess(prim_subreg_pkg::SwAccessRW),
4790 .RESVAL (4'h9),
4791 .Mubi (1'b1)
4792 ) u_bank0_info0_page_cfg_0_scramble_en_0 (
4793 .clk_i (clk_i),
4794 .rst_ni (rst_ni),
4795
4796 // from register interface
4797 .we (bank0_info0_page_cfg_0_gated_we),
4798 .wd (bank0_info0_page_cfg_0_scramble_en_0_wd),
4799
4800 // from internal hardware
4801 .de (1'b0),
4802 .d ('0),
4803
4804 // to internal hardware
4805 .qe (),
4806 .q (reg2hw.bank0_info0_page_cfg[0].scramble_en.q),
4807 .ds (),
4808
4809 // to register interface (read)
4810 .qs (bank0_info0_page_cfg_0_scramble_en_0_qs)
4811 );
4812
4813 // F[ecc_en_0]: 23:20
4814 prim_subreg #(
4815 .DW (4),
4816 .SwAccess(prim_subreg_pkg::SwAccessRW),
4817 .RESVAL (4'h9),
4818 .Mubi (1'b1)
4819 ) u_bank0_info0_page_cfg_0_ecc_en_0 (
4820 .clk_i (clk_i),
4821 .rst_ni (rst_ni),
4822
4823 // from register interface
4824 .we (bank0_info0_page_cfg_0_gated_we),
4825 .wd (bank0_info0_page_cfg_0_ecc_en_0_wd),
4826
4827 // from internal hardware
4828 .de (1'b0),
4829 .d ('0),
4830
4831 // to internal hardware
4832 .qe (),
4833 .q (reg2hw.bank0_info0_page_cfg[0].ecc_en.q),
4834 .ds (),
4835
4836 // to register interface (read)
4837 .qs (bank0_info0_page_cfg_0_ecc_en_0_qs)
4838 );
4839
4840 // F[he_en_0]: 27:24
4841 prim_subreg #(
4842 .DW (4),
4843 .SwAccess(prim_subreg_pkg::SwAccessRW),
4844 .RESVAL (4'h9),
4845 .Mubi (1'b1)
4846 ) u_bank0_info0_page_cfg_0_he_en_0 (
4847 .clk_i (clk_i),
4848 .rst_ni (rst_ni),
4849
4850 // from register interface
4851 .we (bank0_info0_page_cfg_0_gated_we),
4852 .wd (bank0_info0_page_cfg_0_he_en_0_wd),
4853
4854 // from internal hardware
4855 .de (1'b0),
4856 .d ('0),
4857
4858 // to internal hardware
4859 .qe (),
4860 .q (reg2hw.bank0_info0_page_cfg[0].he_en.q),
4861 .ds (),
4862
4863 // to register interface (read)
4864 .qs (bank0_info0_page_cfg_0_he_en_0_qs)
4865 );
4866
4867
4868 // Subregister 1 of Multireg bank0_info0_page_cfg
4869 // R[bank0_info0_page_cfg_1]: V(False)
4870 // Create REGWEN-gated WE signal
4871 logic bank0_info0_page_cfg_1_gated_we;
4872 1/1 assign bank0_info0_page_cfg_1_gated_we = bank0_info0_page_cfg_1_we & bank0_info0_regwen_1_qs;
Tests: T1 T2 T3
4873 // F[en_1]: 3:0
4874 prim_subreg #(
4875 .DW (4),
4876 .SwAccess(prim_subreg_pkg::SwAccessRW),
4877 .RESVAL (4'h9),
4878 .Mubi (1'b1)
4879 ) u_bank0_info0_page_cfg_1_en_1 (
4880 .clk_i (clk_i),
4881 .rst_ni (rst_ni),
4882
4883 // from register interface
4884 .we (bank0_info0_page_cfg_1_gated_we),
4885 .wd (bank0_info0_page_cfg_1_en_1_wd),
4886
4887 // from internal hardware
4888 .de (1'b0),
4889 .d ('0),
4890
4891 // to internal hardware
4892 .qe (),
4893 .q (reg2hw.bank0_info0_page_cfg[1].en.q),
4894 .ds (),
4895
4896 // to register interface (read)
4897 .qs (bank0_info0_page_cfg_1_en_1_qs)
4898 );
4899
4900 // F[rd_en_1]: 7:4
4901 prim_subreg #(
4902 .DW (4),
4903 .SwAccess(prim_subreg_pkg::SwAccessRW),
4904 .RESVAL (4'h9),
4905 .Mubi (1'b1)
4906 ) u_bank0_info0_page_cfg_1_rd_en_1 (
4907 .clk_i (clk_i),
4908 .rst_ni (rst_ni),
4909
4910 // from register interface
4911 .we (bank0_info0_page_cfg_1_gated_we),
4912 .wd (bank0_info0_page_cfg_1_rd_en_1_wd),
4913
4914 // from internal hardware
4915 .de (1'b0),
4916 .d ('0),
4917
4918 // to internal hardware
4919 .qe (),
4920 .q (reg2hw.bank0_info0_page_cfg[1].rd_en.q),
4921 .ds (),
4922
4923 // to register interface (read)
4924 .qs (bank0_info0_page_cfg_1_rd_en_1_qs)
4925 );
4926
4927 // F[prog_en_1]: 11:8
4928 prim_subreg #(
4929 .DW (4),
4930 .SwAccess(prim_subreg_pkg::SwAccessRW),
4931 .RESVAL (4'h9),
4932 .Mubi (1'b1)
4933 ) u_bank0_info0_page_cfg_1_prog_en_1 (
4934 .clk_i (clk_i),
4935 .rst_ni (rst_ni),
4936
4937 // from register interface
4938 .we (bank0_info0_page_cfg_1_gated_we),
4939 .wd (bank0_info0_page_cfg_1_prog_en_1_wd),
4940
4941 // from internal hardware
4942 .de (1'b0),
4943 .d ('0),
4944
4945 // to internal hardware
4946 .qe (),
4947 .q (reg2hw.bank0_info0_page_cfg[1].prog_en.q),
4948 .ds (),
4949
4950 // to register interface (read)
4951 .qs (bank0_info0_page_cfg_1_prog_en_1_qs)
4952 );
4953
4954 // F[erase_en_1]: 15:12
4955 prim_subreg #(
4956 .DW (4),
4957 .SwAccess(prim_subreg_pkg::SwAccessRW),
4958 .RESVAL (4'h9),
4959 .Mubi (1'b1)
4960 ) u_bank0_info0_page_cfg_1_erase_en_1 (
4961 .clk_i (clk_i),
4962 .rst_ni (rst_ni),
4963
4964 // from register interface
4965 .we (bank0_info0_page_cfg_1_gated_we),
4966 .wd (bank0_info0_page_cfg_1_erase_en_1_wd),
4967
4968 // from internal hardware
4969 .de (1'b0),
4970 .d ('0),
4971
4972 // to internal hardware
4973 .qe (),
4974 .q (reg2hw.bank0_info0_page_cfg[1].erase_en.q),
4975 .ds (),
4976
4977 // to register interface (read)
4978 .qs (bank0_info0_page_cfg_1_erase_en_1_qs)
4979 );
4980
4981 // F[scramble_en_1]: 19:16
4982 prim_subreg #(
4983 .DW (4),
4984 .SwAccess(prim_subreg_pkg::SwAccessRW),
4985 .RESVAL (4'h9),
4986 .Mubi (1'b1)
4987 ) u_bank0_info0_page_cfg_1_scramble_en_1 (
4988 .clk_i (clk_i),
4989 .rst_ni (rst_ni),
4990
4991 // from register interface
4992 .we (bank0_info0_page_cfg_1_gated_we),
4993 .wd (bank0_info0_page_cfg_1_scramble_en_1_wd),
4994
4995 // from internal hardware
4996 .de (1'b0),
4997 .d ('0),
4998
4999 // to internal hardware
5000 .qe (),
5001 .q (reg2hw.bank0_info0_page_cfg[1].scramble_en.q),
5002 .ds (),
5003
5004 // to register interface (read)
5005 .qs (bank0_info0_page_cfg_1_scramble_en_1_qs)
5006 );
5007
5008 // F[ecc_en_1]: 23:20
5009 prim_subreg #(
5010 .DW (4),
5011 .SwAccess(prim_subreg_pkg::SwAccessRW),
5012 .RESVAL (4'h9),
5013 .Mubi (1'b1)
5014 ) u_bank0_info0_page_cfg_1_ecc_en_1 (
5015 .clk_i (clk_i),
5016 .rst_ni (rst_ni),
5017
5018 // from register interface
5019 .we (bank0_info0_page_cfg_1_gated_we),
5020 .wd (bank0_info0_page_cfg_1_ecc_en_1_wd),
5021
5022 // from internal hardware
5023 .de (1'b0),
5024 .d ('0),
5025
5026 // to internal hardware
5027 .qe (),
5028 .q (reg2hw.bank0_info0_page_cfg[1].ecc_en.q),
5029 .ds (),
5030
5031 // to register interface (read)
5032 .qs (bank0_info0_page_cfg_1_ecc_en_1_qs)
5033 );
5034
5035 // F[he_en_1]: 27:24
5036 prim_subreg #(
5037 .DW (4),
5038 .SwAccess(prim_subreg_pkg::SwAccessRW),
5039 .RESVAL (4'h9),
5040 .Mubi (1'b1)
5041 ) u_bank0_info0_page_cfg_1_he_en_1 (
5042 .clk_i (clk_i),
5043 .rst_ni (rst_ni),
5044
5045 // from register interface
5046 .we (bank0_info0_page_cfg_1_gated_we),
5047 .wd (bank0_info0_page_cfg_1_he_en_1_wd),
5048
5049 // from internal hardware
5050 .de (1'b0),
5051 .d ('0),
5052
5053 // to internal hardware
5054 .qe (),
5055 .q (reg2hw.bank0_info0_page_cfg[1].he_en.q),
5056 .ds (),
5057
5058 // to register interface (read)
5059 .qs (bank0_info0_page_cfg_1_he_en_1_qs)
5060 );
5061
5062
5063 // Subregister 2 of Multireg bank0_info0_page_cfg
5064 // R[bank0_info0_page_cfg_2]: V(False)
5065 // Create REGWEN-gated WE signal
5066 logic bank0_info0_page_cfg_2_gated_we;
5067 1/1 assign bank0_info0_page_cfg_2_gated_we = bank0_info0_page_cfg_2_we & bank0_info0_regwen_2_qs;
Tests: T1 T2 T3
5068 // F[en_2]: 3:0
5069 prim_subreg #(
5070 .DW (4),
5071 .SwAccess(prim_subreg_pkg::SwAccessRW),
5072 .RESVAL (4'h9),
5073 .Mubi (1'b1)
5074 ) u_bank0_info0_page_cfg_2_en_2 (
5075 .clk_i (clk_i),
5076 .rst_ni (rst_ni),
5077
5078 // from register interface
5079 .we (bank0_info0_page_cfg_2_gated_we),
5080 .wd (bank0_info0_page_cfg_2_en_2_wd),
5081
5082 // from internal hardware
5083 .de (1'b0),
5084 .d ('0),
5085
5086 // to internal hardware
5087 .qe (),
5088 .q (reg2hw.bank0_info0_page_cfg[2].en.q),
5089 .ds (),
5090
5091 // to register interface (read)
5092 .qs (bank0_info0_page_cfg_2_en_2_qs)
5093 );
5094
5095 // F[rd_en_2]: 7:4
5096 prim_subreg #(
5097 .DW (4),
5098 .SwAccess(prim_subreg_pkg::SwAccessRW),
5099 .RESVAL (4'h9),
5100 .Mubi (1'b1)
5101 ) u_bank0_info0_page_cfg_2_rd_en_2 (
5102 .clk_i (clk_i),
5103 .rst_ni (rst_ni),
5104
5105 // from register interface
5106 .we (bank0_info0_page_cfg_2_gated_we),
5107 .wd (bank0_info0_page_cfg_2_rd_en_2_wd),
5108
5109 // from internal hardware
5110 .de (1'b0),
5111 .d ('0),
5112
5113 // to internal hardware
5114 .qe (),
5115 .q (reg2hw.bank0_info0_page_cfg[2].rd_en.q),
5116 .ds (),
5117
5118 // to register interface (read)
5119 .qs (bank0_info0_page_cfg_2_rd_en_2_qs)
5120 );
5121
5122 // F[prog_en_2]: 11:8
5123 prim_subreg #(
5124 .DW (4),
5125 .SwAccess(prim_subreg_pkg::SwAccessRW),
5126 .RESVAL (4'h9),
5127 .Mubi (1'b1)
5128 ) u_bank0_info0_page_cfg_2_prog_en_2 (
5129 .clk_i (clk_i),
5130 .rst_ni (rst_ni),
5131
5132 // from register interface
5133 .we (bank0_info0_page_cfg_2_gated_we),
5134 .wd (bank0_info0_page_cfg_2_prog_en_2_wd),
5135
5136 // from internal hardware
5137 .de (1'b0),
5138 .d ('0),
5139
5140 // to internal hardware
5141 .qe (),
5142 .q (reg2hw.bank0_info0_page_cfg[2].prog_en.q),
5143 .ds (),
5144
5145 // to register interface (read)
5146 .qs (bank0_info0_page_cfg_2_prog_en_2_qs)
5147 );
5148
5149 // F[erase_en_2]: 15:12
5150 prim_subreg #(
5151 .DW (4),
5152 .SwAccess(prim_subreg_pkg::SwAccessRW),
5153 .RESVAL (4'h9),
5154 .Mubi (1'b1)
5155 ) u_bank0_info0_page_cfg_2_erase_en_2 (
5156 .clk_i (clk_i),
5157 .rst_ni (rst_ni),
5158
5159 // from register interface
5160 .we (bank0_info0_page_cfg_2_gated_we),
5161 .wd (bank0_info0_page_cfg_2_erase_en_2_wd),
5162
5163 // from internal hardware
5164 .de (1'b0),
5165 .d ('0),
5166
5167 // to internal hardware
5168 .qe (),
5169 .q (reg2hw.bank0_info0_page_cfg[2].erase_en.q),
5170 .ds (),
5171
5172 // to register interface (read)
5173 .qs (bank0_info0_page_cfg_2_erase_en_2_qs)
5174 );
5175
5176 // F[scramble_en_2]: 19:16
5177 prim_subreg #(
5178 .DW (4),
5179 .SwAccess(prim_subreg_pkg::SwAccessRW),
5180 .RESVAL (4'h9),
5181 .Mubi (1'b1)
5182 ) u_bank0_info0_page_cfg_2_scramble_en_2 (
5183 .clk_i (clk_i),
5184 .rst_ni (rst_ni),
5185
5186 // from register interface
5187 .we (bank0_info0_page_cfg_2_gated_we),
5188 .wd (bank0_info0_page_cfg_2_scramble_en_2_wd),
5189
5190 // from internal hardware
5191 .de (1'b0),
5192 .d ('0),
5193
5194 // to internal hardware
5195 .qe (),
5196 .q (reg2hw.bank0_info0_page_cfg[2].scramble_en.q),
5197 .ds (),
5198
5199 // to register interface (read)
5200 .qs (bank0_info0_page_cfg_2_scramble_en_2_qs)
5201 );
5202
5203 // F[ecc_en_2]: 23:20
5204 prim_subreg #(
5205 .DW (4),
5206 .SwAccess(prim_subreg_pkg::SwAccessRW),
5207 .RESVAL (4'h9),
5208 .Mubi (1'b1)
5209 ) u_bank0_info0_page_cfg_2_ecc_en_2 (
5210 .clk_i (clk_i),
5211 .rst_ni (rst_ni),
5212
5213 // from register interface
5214 .we (bank0_info0_page_cfg_2_gated_we),
5215 .wd (bank0_info0_page_cfg_2_ecc_en_2_wd),
5216
5217 // from internal hardware
5218 .de (1'b0),
5219 .d ('0),
5220
5221 // to internal hardware
5222 .qe (),
5223 .q (reg2hw.bank0_info0_page_cfg[2].ecc_en.q),
5224 .ds (),
5225
5226 // to register interface (read)
5227 .qs (bank0_info0_page_cfg_2_ecc_en_2_qs)
5228 );
5229
5230 // F[he_en_2]: 27:24
5231 prim_subreg #(
5232 .DW (4),
5233 .SwAccess(prim_subreg_pkg::SwAccessRW),
5234 .RESVAL (4'h9),
5235 .Mubi (1'b1)
5236 ) u_bank0_info0_page_cfg_2_he_en_2 (
5237 .clk_i (clk_i),
5238 .rst_ni (rst_ni),
5239
5240 // from register interface
5241 .we (bank0_info0_page_cfg_2_gated_we),
5242 .wd (bank0_info0_page_cfg_2_he_en_2_wd),
5243
5244 // from internal hardware
5245 .de (1'b0),
5246 .d ('0),
5247
5248 // to internal hardware
5249 .qe (),
5250 .q (reg2hw.bank0_info0_page_cfg[2].he_en.q),
5251 .ds (),
5252
5253 // to register interface (read)
5254 .qs (bank0_info0_page_cfg_2_he_en_2_qs)
5255 );
5256
5257
5258 // Subregister 3 of Multireg bank0_info0_page_cfg
5259 // R[bank0_info0_page_cfg_3]: V(False)
5260 // Create REGWEN-gated WE signal
5261 logic bank0_info0_page_cfg_3_gated_we;
5262 1/1 assign bank0_info0_page_cfg_3_gated_we = bank0_info0_page_cfg_3_we & bank0_info0_regwen_3_qs;
Tests: T1 T2 T3
5263 // F[en_3]: 3:0
5264 prim_subreg #(
5265 .DW (4),
5266 .SwAccess(prim_subreg_pkg::SwAccessRW),
5267 .RESVAL (4'h9),
5268 .Mubi (1'b1)
5269 ) u_bank0_info0_page_cfg_3_en_3 (
5270 .clk_i (clk_i),
5271 .rst_ni (rst_ni),
5272
5273 // from register interface
5274 .we (bank0_info0_page_cfg_3_gated_we),
5275 .wd (bank0_info0_page_cfg_3_en_3_wd),
5276
5277 // from internal hardware
5278 .de (1'b0),
5279 .d ('0),
5280
5281 // to internal hardware
5282 .qe (),
5283 .q (reg2hw.bank0_info0_page_cfg[3].en.q),
5284 .ds (),
5285
5286 // to register interface (read)
5287 .qs (bank0_info0_page_cfg_3_en_3_qs)
5288 );
5289
5290 // F[rd_en_3]: 7:4
5291 prim_subreg #(
5292 .DW (4),
5293 .SwAccess(prim_subreg_pkg::SwAccessRW),
5294 .RESVAL (4'h9),
5295 .Mubi (1'b1)
5296 ) u_bank0_info0_page_cfg_3_rd_en_3 (
5297 .clk_i (clk_i),
5298 .rst_ni (rst_ni),
5299
5300 // from register interface
5301 .we (bank0_info0_page_cfg_3_gated_we),
5302 .wd (bank0_info0_page_cfg_3_rd_en_3_wd),
5303
5304 // from internal hardware
5305 .de (1'b0),
5306 .d ('0),
5307
5308 // to internal hardware
5309 .qe (),
5310 .q (reg2hw.bank0_info0_page_cfg[3].rd_en.q),
5311 .ds (),
5312
5313 // to register interface (read)
5314 .qs (bank0_info0_page_cfg_3_rd_en_3_qs)
5315 );
5316
5317 // F[prog_en_3]: 11:8
5318 prim_subreg #(
5319 .DW (4),
5320 .SwAccess(prim_subreg_pkg::SwAccessRW),
5321 .RESVAL (4'h9),
5322 .Mubi (1'b1)
5323 ) u_bank0_info0_page_cfg_3_prog_en_3 (
5324 .clk_i (clk_i),
5325 .rst_ni (rst_ni),
5326
5327 // from register interface
5328 .we (bank0_info0_page_cfg_3_gated_we),
5329 .wd (bank0_info0_page_cfg_3_prog_en_3_wd),
5330
5331 // from internal hardware
5332 .de (1'b0),
5333 .d ('0),
5334
5335 // to internal hardware
5336 .qe (),
5337 .q (reg2hw.bank0_info0_page_cfg[3].prog_en.q),
5338 .ds (),
5339
5340 // to register interface (read)
5341 .qs (bank0_info0_page_cfg_3_prog_en_3_qs)
5342 );
5343
5344 // F[erase_en_3]: 15:12
5345 prim_subreg #(
5346 .DW (4),
5347 .SwAccess(prim_subreg_pkg::SwAccessRW),
5348 .RESVAL (4'h9),
5349 .Mubi (1'b1)
5350 ) u_bank0_info0_page_cfg_3_erase_en_3 (
5351 .clk_i (clk_i),
5352 .rst_ni (rst_ni),
5353
5354 // from register interface
5355 .we (bank0_info0_page_cfg_3_gated_we),
5356 .wd (bank0_info0_page_cfg_3_erase_en_3_wd),
5357
5358 // from internal hardware
5359 .de (1'b0),
5360 .d ('0),
5361
5362 // to internal hardware
5363 .qe (),
5364 .q (reg2hw.bank0_info0_page_cfg[3].erase_en.q),
5365 .ds (),
5366
5367 // to register interface (read)
5368 .qs (bank0_info0_page_cfg_3_erase_en_3_qs)
5369 );
5370
5371 // F[scramble_en_3]: 19:16
5372 prim_subreg #(
5373 .DW (4),
5374 .SwAccess(prim_subreg_pkg::SwAccessRW),
5375 .RESVAL (4'h9),
5376 .Mubi (1'b1)
5377 ) u_bank0_info0_page_cfg_3_scramble_en_3 (
5378 .clk_i (clk_i),
5379 .rst_ni (rst_ni),
5380
5381 // from register interface
5382 .we (bank0_info0_page_cfg_3_gated_we),
5383 .wd (bank0_info0_page_cfg_3_scramble_en_3_wd),
5384
5385 // from internal hardware
5386 .de (1'b0),
5387 .d ('0),
5388
5389 // to internal hardware
5390 .qe (),
5391 .q (reg2hw.bank0_info0_page_cfg[3].scramble_en.q),
5392 .ds (),
5393
5394 // to register interface (read)
5395 .qs (bank0_info0_page_cfg_3_scramble_en_3_qs)
5396 );
5397
5398 // F[ecc_en_3]: 23:20
5399 prim_subreg #(
5400 .DW (4),
5401 .SwAccess(prim_subreg_pkg::SwAccessRW),
5402 .RESVAL (4'h9),
5403 .Mubi (1'b1)
5404 ) u_bank0_info0_page_cfg_3_ecc_en_3 (
5405 .clk_i (clk_i),
5406 .rst_ni (rst_ni),
5407
5408 // from register interface
5409 .we (bank0_info0_page_cfg_3_gated_we),
5410 .wd (bank0_info0_page_cfg_3_ecc_en_3_wd),
5411
5412 // from internal hardware
5413 .de (1'b0),
5414 .d ('0),
5415
5416 // to internal hardware
5417 .qe (),
5418 .q (reg2hw.bank0_info0_page_cfg[3].ecc_en.q),
5419 .ds (),
5420
5421 // to register interface (read)
5422 .qs (bank0_info0_page_cfg_3_ecc_en_3_qs)
5423 );
5424
5425 // F[he_en_3]: 27:24
5426 prim_subreg #(
5427 .DW (4),
5428 .SwAccess(prim_subreg_pkg::SwAccessRW),
5429 .RESVAL (4'h9),
5430 .Mubi (1'b1)
5431 ) u_bank0_info0_page_cfg_3_he_en_3 (
5432 .clk_i (clk_i),
5433 .rst_ni (rst_ni),
5434
5435 // from register interface
5436 .we (bank0_info0_page_cfg_3_gated_we),
5437 .wd (bank0_info0_page_cfg_3_he_en_3_wd),
5438
5439 // from internal hardware
5440 .de (1'b0),
5441 .d ('0),
5442
5443 // to internal hardware
5444 .qe (),
5445 .q (reg2hw.bank0_info0_page_cfg[3].he_en.q),
5446 .ds (),
5447
5448 // to register interface (read)
5449 .qs (bank0_info0_page_cfg_3_he_en_3_qs)
5450 );
5451
5452
5453 // Subregister 4 of Multireg bank0_info0_page_cfg
5454 // R[bank0_info0_page_cfg_4]: V(False)
5455 // Create REGWEN-gated WE signal
5456 logic bank0_info0_page_cfg_4_gated_we;
5457 1/1 assign bank0_info0_page_cfg_4_gated_we = bank0_info0_page_cfg_4_we & bank0_info0_regwen_4_qs;
Tests: T1 T2 T3
5458 // F[en_4]: 3:0
5459 prim_subreg #(
5460 .DW (4),
5461 .SwAccess(prim_subreg_pkg::SwAccessRW),
5462 .RESVAL (4'h9),
5463 .Mubi (1'b1)
5464 ) u_bank0_info0_page_cfg_4_en_4 (
5465 .clk_i (clk_i),
5466 .rst_ni (rst_ni),
5467
5468 // from register interface
5469 .we (bank0_info0_page_cfg_4_gated_we),
5470 .wd (bank0_info0_page_cfg_4_en_4_wd),
5471
5472 // from internal hardware
5473 .de (1'b0),
5474 .d ('0),
5475
5476 // to internal hardware
5477 .qe (),
5478 .q (reg2hw.bank0_info0_page_cfg[4].en.q),
5479 .ds (),
5480
5481 // to register interface (read)
5482 .qs (bank0_info0_page_cfg_4_en_4_qs)
5483 );
5484
5485 // F[rd_en_4]: 7:4
5486 prim_subreg #(
5487 .DW (4),
5488 .SwAccess(prim_subreg_pkg::SwAccessRW),
5489 .RESVAL (4'h9),
5490 .Mubi (1'b1)
5491 ) u_bank0_info0_page_cfg_4_rd_en_4 (
5492 .clk_i (clk_i),
5493 .rst_ni (rst_ni),
5494
5495 // from register interface
5496 .we (bank0_info0_page_cfg_4_gated_we),
5497 .wd (bank0_info0_page_cfg_4_rd_en_4_wd),
5498
5499 // from internal hardware
5500 .de (1'b0),
5501 .d ('0),
5502
5503 // to internal hardware
5504 .qe (),
5505 .q (reg2hw.bank0_info0_page_cfg[4].rd_en.q),
5506 .ds (),
5507
5508 // to register interface (read)
5509 .qs (bank0_info0_page_cfg_4_rd_en_4_qs)
5510 );
5511
5512 // F[prog_en_4]: 11:8
5513 prim_subreg #(
5514 .DW (4),
5515 .SwAccess(prim_subreg_pkg::SwAccessRW),
5516 .RESVAL (4'h9),
5517 .Mubi (1'b1)
5518 ) u_bank0_info0_page_cfg_4_prog_en_4 (
5519 .clk_i (clk_i),
5520 .rst_ni (rst_ni),
5521
5522 // from register interface
5523 .we (bank0_info0_page_cfg_4_gated_we),
5524 .wd (bank0_info0_page_cfg_4_prog_en_4_wd),
5525
5526 // from internal hardware
5527 .de (1'b0),
5528 .d ('0),
5529
5530 // to internal hardware
5531 .qe (),
5532 .q (reg2hw.bank0_info0_page_cfg[4].prog_en.q),
5533 .ds (),
5534
5535 // to register interface (read)
5536 .qs (bank0_info0_page_cfg_4_prog_en_4_qs)
5537 );
5538
5539 // F[erase_en_4]: 15:12
5540 prim_subreg #(
5541 .DW (4),
5542 .SwAccess(prim_subreg_pkg::SwAccessRW),
5543 .RESVAL (4'h9),
5544 .Mubi (1'b1)
5545 ) u_bank0_info0_page_cfg_4_erase_en_4 (
5546 .clk_i (clk_i),
5547 .rst_ni (rst_ni),
5548
5549 // from register interface
5550 .we (bank0_info0_page_cfg_4_gated_we),
5551 .wd (bank0_info0_page_cfg_4_erase_en_4_wd),
5552
5553 // from internal hardware
5554 .de (1'b0),
5555 .d ('0),
5556
5557 // to internal hardware
5558 .qe (),
5559 .q (reg2hw.bank0_info0_page_cfg[4].erase_en.q),
5560 .ds (),
5561
5562 // to register interface (read)
5563 .qs (bank0_info0_page_cfg_4_erase_en_4_qs)
5564 );
5565
5566 // F[scramble_en_4]: 19:16
5567 prim_subreg #(
5568 .DW (4),
5569 .SwAccess(prim_subreg_pkg::SwAccessRW),
5570 .RESVAL (4'h9),
5571 .Mubi (1'b1)
5572 ) u_bank0_info0_page_cfg_4_scramble_en_4 (
5573 .clk_i (clk_i),
5574 .rst_ni (rst_ni),
5575
5576 // from register interface
5577 .we (bank0_info0_page_cfg_4_gated_we),
5578 .wd (bank0_info0_page_cfg_4_scramble_en_4_wd),
5579
5580 // from internal hardware
5581 .de (1'b0),
5582 .d ('0),
5583
5584 // to internal hardware
5585 .qe (),
5586 .q (reg2hw.bank0_info0_page_cfg[4].scramble_en.q),
5587 .ds (),
5588
5589 // to register interface (read)
5590 .qs (bank0_info0_page_cfg_4_scramble_en_4_qs)
5591 );
5592
5593 // F[ecc_en_4]: 23:20
5594 prim_subreg #(
5595 .DW (4),
5596 .SwAccess(prim_subreg_pkg::SwAccessRW),
5597 .RESVAL (4'h9),
5598 .Mubi (1'b1)
5599 ) u_bank0_info0_page_cfg_4_ecc_en_4 (
5600 .clk_i (clk_i),
5601 .rst_ni (rst_ni),
5602
5603 // from register interface
5604 .we (bank0_info0_page_cfg_4_gated_we),
5605 .wd (bank0_info0_page_cfg_4_ecc_en_4_wd),
5606
5607 // from internal hardware
5608 .de (1'b0),
5609 .d ('0),
5610
5611 // to internal hardware
5612 .qe (),
5613 .q (reg2hw.bank0_info0_page_cfg[4].ecc_en.q),
5614 .ds (),
5615
5616 // to register interface (read)
5617 .qs (bank0_info0_page_cfg_4_ecc_en_4_qs)
5618 );
5619
5620 // F[he_en_4]: 27:24
5621 prim_subreg #(
5622 .DW (4),
5623 .SwAccess(prim_subreg_pkg::SwAccessRW),
5624 .RESVAL (4'h9),
5625 .Mubi (1'b1)
5626 ) u_bank0_info0_page_cfg_4_he_en_4 (
5627 .clk_i (clk_i),
5628 .rst_ni (rst_ni),
5629
5630 // from register interface
5631 .we (bank0_info0_page_cfg_4_gated_we),
5632 .wd (bank0_info0_page_cfg_4_he_en_4_wd),
5633
5634 // from internal hardware
5635 .de (1'b0),
5636 .d ('0),
5637
5638 // to internal hardware
5639 .qe (),
5640 .q (reg2hw.bank0_info0_page_cfg[4].he_en.q),
5641 .ds (),
5642
5643 // to register interface (read)
5644 .qs (bank0_info0_page_cfg_4_he_en_4_qs)
5645 );
5646
5647
5648 // Subregister 5 of Multireg bank0_info0_page_cfg
5649 // R[bank0_info0_page_cfg_5]: V(False)
5650 // Create REGWEN-gated WE signal
5651 logic bank0_info0_page_cfg_5_gated_we;
5652 1/1 assign bank0_info0_page_cfg_5_gated_we = bank0_info0_page_cfg_5_we & bank0_info0_regwen_5_qs;
Tests: T1 T2 T3
5653 // F[en_5]: 3:0
5654 prim_subreg #(
5655 .DW (4),
5656 .SwAccess(prim_subreg_pkg::SwAccessRW),
5657 .RESVAL (4'h9),
5658 .Mubi (1'b1)
5659 ) u_bank0_info0_page_cfg_5_en_5 (
5660 .clk_i (clk_i),
5661 .rst_ni (rst_ni),
5662
5663 // from register interface
5664 .we (bank0_info0_page_cfg_5_gated_we),
5665 .wd (bank0_info0_page_cfg_5_en_5_wd),
5666
5667 // from internal hardware
5668 .de (1'b0),
5669 .d ('0),
5670
5671 // to internal hardware
5672 .qe (),
5673 .q (reg2hw.bank0_info0_page_cfg[5].en.q),
5674 .ds (),
5675
5676 // to register interface (read)
5677 .qs (bank0_info0_page_cfg_5_en_5_qs)
5678 );
5679
5680 // F[rd_en_5]: 7:4
5681 prim_subreg #(
5682 .DW (4),
5683 .SwAccess(prim_subreg_pkg::SwAccessRW),
5684 .RESVAL (4'h9),
5685 .Mubi (1'b1)
5686 ) u_bank0_info0_page_cfg_5_rd_en_5 (
5687 .clk_i (clk_i),
5688 .rst_ni (rst_ni),
5689
5690 // from register interface
5691 .we (bank0_info0_page_cfg_5_gated_we),
5692 .wd (bank0_info0_page_cfg_5_rd_en_5_wd),
5693
5694 // from internal hardware
5695 .de (1'b0),
5696 .d ('0),
5697
5698 // to internal hardware
5699 .qe (),
5700 .q (reg2hw.bank0_info0_page_cfg[5].rd_en.q),
5701 .ds (),
5702
5703 // to register interface (read)
5704 .qs (bank0_info0_page_cfg_5_rd_en_5_qs)
5705 );
5706
5707 // F[prog_en_5]: 11:8
5708 prim_subreg #(
5709 .DW (4),
5710 .SwAccess(prim_subreg_pkg::SwAccessRW),
5711 .RESVAL (4'h9),
5712 .Mubi (1'b1)
5713 ) u_bank0_info0_page_cfg_5_prog_en_5 (
5714 .clk_i (clk_i),
5715 .rst_ni (rst_ni),
5716
5717 // from register interface
5718 .we (bank0_info0_page_cfg_5_gated_we),
5719 .wd (bank0_info0_page_cfg_5_prog_en_5_wd),
5720
5721 // from internal hardware
5722 .de (1'b0),
5723 .d ('0),
5724
5725 // to internal hardware
5726 .qe (),
5727 .q (reg2hw.bank0_info0_page_cfg[5].prog_en.q),
5728 .ds (),
5729
5730 // to register interface (read)
5731 .qs (bank0_info0_page_cfg_5_prog_en_5_qs)
5732 );
5733
5734 // F[erase_en_5]: 15:12
5735 prim_subreg #(
5736 .DW (4),
5737 .SwAccess(prim_subreg_pkg::SwAccessRW),
5738 .RESVAL (4'h9),
5739 .Mubi (1'b1)
5740 ) u_bank0_info0_page_cfg_5_erase_en_5 (
5741 .clk_i (clk_i),
5742 .rst_ni (rst_ni),
5743
5744 // from register interface
5745 .we (bank0_info0_page_cfg_5_gated_we),
5746 .wd (bank0_info0_page_cfg_5_erase_en_5_wd),
5747
5748 // from internal hardware
5749 .de (1'b0),
5750 .d ('0),
5751
5752 // to internal hardware
5753 .qe (),
5754 .q (reg2hw.bank0_info0_page_cfg[5].erase_en.q),
5755 .ds (),
5756
5757 // to register interface (read)
5758 .qs (bank0_info0_page_cfg_5_erase_en_5_qs)
5759 );
5760
5761 // F[scramble_en_5]: 19:16
5762 prim_subreg #(
5763 .DW (4),
5764 .SwAccess(prim_subreg_pkg::SwAccessRW),
5765 .RESVAL (4'h9),
5766 .Mubi (1'b1)
5767 ) u_bank0_info0_page_cfg_5_scramble_en_5 (
5768 .clk_i (clk_i),
5769 .rst_ni (rst_ni),
5770
5771 // from register interface
5772 .we (bank0_info0_page_cfg_5_gated_we),
5773 .wd (bank0_info0_page_cfg_5_scramble_en_5_wd),
5774
5775 // from internal hardware
5776 .de (1'b0),
5777 .d ('0),
5778
5779 // to internal hardware
5780 .qe (),
5781 .q (reg2hw.bank0_info0_page_cfg[5].scramble_en.q),
5782 .ds (),
5783
5784 // to register interface (read)
5785 .qs (bank0_info0_page_cfg_5_scramble_en_5_qs)
5786 );
5787
5788 // F[ecc_en_5]: 23:20
5789 prim_subreg #(
5790 .DW (4),
5791 .SwAccess(prim_subreg_pkg::SwAccessRW),
5792 .RESVAL (4'h9),
5793 .Mubi (1'b1)
5794 ) u_bank0_info0_page_cfg_5_ecc_en_5 (
5795 .clk_i (clk_i),
5796 .rst_ni (rst_ni),
5797
5798 // from register interface
5799 .we (bank0_info0_page_cfg_5_gated_we),
5800 .wd (bank0_info0_page_cfg_5_ecc_en_5_wd),
5801
5802 // from internal hardware
5803 .de (1'b0),
5804 .d ('0),
5805
5806 // to internal hardware
5807 .qe (),
5808 .q (reg2hw.bank0_info0_page_cfg[5].ecc_en.q),
5809 .ds (),
5810
5811 // to register interface (read)
5812 .qs (bank0_info0_page_cfg_5_ecc_en_5_qs)
5813 );
5814
5815 // F[he_en_5]: 27:24
5816 prim_subreg #(
5817 .DW (4),
5818 .SwAccess(prim_subreg_pkg::SwAccessRW),
5819 .RESVAL (4'h9),
5820 .Mubi (1'b1)
5821 ) u_bank0_info0_page_cfg_5_he_en_5 (
5822 .clk_i (clk_i),
5823 .rst_ni (rst_ni),
5824
5825 // from register interface
5826 .we (bank0_info0_page_cfg_5_gated_we),
5827 .wd (bank0_info0_page_cfg_5_he_en_5_wd),
5828
5829 // from internal hardware
5830 .de (1'b0),
5831 .d ('0),
5832
5833 // to internal hardware
5834 .qe (),
5835 .q (reg2hw.bank0_info0_page_cfg[5].he_en.q),
5836 .ds (),
5837
5838 // to register interface (read)
5839 .qs (bank0_info0_page_cfg_5_he_en_5_qs)
5840 );
5841
5842
5843 // Subregister 6 of Multireg bank0_info0_page_cfg
5844 // R[bank0_info0_page_cfg_6]: V(False)
5845 // Create REGWEN-gated WE signal
5846 logic bank0_info0_page_cfg_6_gated_we;
5847 1/1 assign bank0_info0_page_cfg_6_gated_we = bank0_info0_page_cfg_6_we & bank0_info0_regwen_6_qs;
Tests: T1 T2 T3
5848 // F[en_6]: 3:0
5849 prim_subreg #(
5850 .DW (4),
5851 .SwAccess(prim_subreg_pkg::SwAccessRW),
5852 .RESVAL (4'h9),
5853 .Mubi (1'b1)
5854 ) u_bank0_info0_page_cfg_6_en_6 (
5855 .clk_i (clk_i),
5856 .rst_ni (rst_ni),
5857
5858 // from register interface
5859 .we (bank0_info0_page_cfg_6_gated_we),
5860 .wd (bank0_info0_page_cfg_6_en_6_wd),
5861
5862 // from internal hardware
5863 .de (1'b0),
5864 .d ('0),
5865
5866 // to internal hardware
5867 .qe (),
5868 .q (reg2hw.bank0_info0_page_cfg[6].en.q),
5869 .ds (),
5870
5871 // to register interface (read)
5872 .qs (bank0_info0_page_cfg_6_en_6_qs)
5873 );
5874
5875 // F[rd_en_6]: 7:4
5876 prim_subreg #(
5877 .DW (4),
5878 .SwAccess(prim_subreg_pkg::SwAccessRW),
5879 .RESVAL (4'h9),
5880 .Mubi (1'b1)
5881 ) u_bank0_info0_page_cfg_6_rd_en_6 (
5882 .clk_i (clk_i),
5883 .rst_ni (rst_ni),
5884
5885 // from register interface
5886 .we (bank0_info0_page_cfg_6_gated_we),
5887 .wd (bank0_info0_page_cfg_6_rd_en_6_wd),
5888
5889 // from internal hardware
5890 .de (1'b0),
5891 .d ('0),
5892
5893 // to internal hardware
5894 .qe (),
5895 .q (reg2hw.bank0_info0_page_cfg[6].rd_en.q),
5896 .ds (),
5897
5898 // to register interface (read)
5899 .qs (bank0_info0_page_cfg_6_rd_en_6_qs)
5900 );
5901
5902 // F[prog_en_6]: 11:8
5903 prim_subreg #(
5904 .DW (4),
5905 .SwAccess(prim_subreg_pkg::SwAccessRW),
5906 .RESVAL (4'h9),
5907 .Mubi (1'b1)
5908 ) u_bank0_info0_page_cfg_6_prog_en_6 (
5909 .clk_i (clk_i),
5910 .rst_ni (rst_ni),
5911
5912 // from register interface
5913 .we (bank0_info0_page_cfg_6_gated_we),
5914 .wd (bank0_info0_page_cfg_6_prog_en_6_wd),
5915
5916 // from internal hardware
5917 .de (1'b0),
5918 .d ('0),
5919
5920 // to internal hardware
5921 .qe (),
5922 .q (reg2hw.bank0_info0_page_cfg[6].prog_en.q),
5923 .ds (),
5924
5925 // to register interface (read)
5926 .qs (bank0_info0_page_cfg_6_prog_en_6_qs)
5927 );
5928
5929 // F[erase_en_6]: 15:12
5930 prim_subreg #(
5931 .DW (4),
5932 .SwAccess(prim_subreg_pkg::SwAccessRW),
5933 .RESVAL (4'h9),
5934 .Mubi (1'b1)
5935 ) u_bank0_info0_page_cfg_6_erase_en_6 (
5936 .clk_i (clk_i),
5937 .rst_ni (rst_ni),
5938
5939 // from register interface
5940 .we (bank0_info0_page_cfg_6_gated_we),
5941 .wd (bank0_info0_page_cfg_6_erase_en_6_wd),
5942
5943 // from internal hardware
5944 .de (1'b0),
5945 .d ('0),
5946
5947 // to internal hardware
5948 .qe (),
5949 .q (reg2hw.bank0_info0_page_cfg[6].erase_en.q),
5950 .ds (),
5951
5952 // to register interface (read)
5953 .qs (bank0_info0_page_cfg_6_erase_en_6_qs)
5954 );
5955
5956 // F[scramble_en_6]: 19:16
5957 prim_subreg #(
5958 .DW (4),
5959 .SwAccess(prim_subreg_pkg::SwAccessRW),
5960 .RESVAL (4'h9),
5961 .Mubi (1'b1)
5962 ) u_bank0_info0_page_cfg_6_scramble_en_6 (
5963 .clk_i (clk_i),
5964 .rst_ni (rst_ni),
5965
5966 // from register interface
5967 .we (bank0_info0_page_cfg_6_gated_we),
5968 .wd (bank0_info0_page_cfg_6_scramble_en_6_wd),
5969
5970 // from internal hardware
5971 .de (1'b0),
5972 .d ('0),
5973
5974 // to internal hardware
5975 .qe (),
5976 .q (reg2hw.bank0_info0_page_cfg[6].scramble_en.q),
5977 .ds (),
5978
5979 // to register interface (read)
5980 .qs (bank0_info0_page_cfg_6_scramble_en_6_qs)
5981 );
5982
5983 // F[ecc_en_6]: 23:20
5984 prim_subreg #(
5985 .DW (4),
5986 .SwAccess(prim_subreg_pkg::SwAccessRW),
5987 .RESVAL (4'h9),
5988 .Mubi (1'b1)
5989 ) u_bank0_info0_page_cfg_6_ecc_en_6 (
5990 .clk_i (clk_i),
5991 .rst_ni (rst_ni),
5992
5993 // from register interface
5994 .we (bank0_info0_page_cfg_6_gated_we),
5995 .wd (bank0_info0_page_cfg_6_ecc_en_6_wd),
5996
5997 // from internal hardware
5998 .de (1'b0),
5999 .d ('0),
6000
6001 // to internal hardware
6002 .qe (),
6003 .q (reg2hw.bank0_info0_page_cfg[6].ecc_en.q),
6004 .ds (),
6005
6006 // to register interface (read)
6007 .qs (bank0_info0_page_cfg_6_ecc_en_6_qs)
6008 );
6009
6010 // F[he_en_6]: 27:24
6011 prim_subreg #(
6012 .DW (4),
6013 .SwAccess(prim_subreg_pkg::SwAccessRW),
6014 .RESVAL (4'h9),
6015 .Mubi (1'b1)
6016 ) u_bank0_info0_page_cfg_6_he_en_6 (
6017 .clk_i (clk_i),
6018 .rst_ni (rst_ni),
6019
6020 // from register interface
6021 .we (bank0_info0_page_cfg_6_gated_we),
6022 .wd (bank0_info0_page_cfg_6_he_en_6_wd),
6023
6024 // from internal hardware
6025 .de (1'b0),
6026 .d ('0),
6027
6028 // to internal hardware
6029 .qe (),
6030 .q (reg2hw.bank0_info0_page_cfg[6].he_en.q),
6031 .ds (),
6032
6033 // to register interface (read)
6034 .qs (bank0_info0_page_cfg_6_he_en_6_qs)
6035 );
6036
6037
6038 // Subregister 7 of Multireg bank0_info0_page_cfg
6039 // R[bank0_info0_page_cfg_7]: V(False)
6040 // Create REGWEN-gated WE signal
6041 logic bank0_info0_page_cfg_7_gated_we;
6042 1/1 assign bank0_info0_page_cfg_7_gated_we = bank0_info0_page_cfg_7_we & bank0_info0_regwen_7_qs;
Tests: T1 T2 T3
6043 // F[en_7]: 3:0
6044 prim_subreg #(
6045 .DW (4),
6046 .SwAccess(prim_subreg_pkg::SwAccessRW),
6047 .RESVAL (4'h9),
6048 .Mubi (1'b1)
6049 ) u_bank0_info0_page_cfg_7_en_7 (
6050 .clk_i (clk_i),
6051 .rst_ni (rst_ni),
6052
6053 // from register interface
6054 .we (bank0_info0_page_cfg_7_gated_we),
6055 .wd (bank0_info0_page_cfg_7_en_7_wd),
6056
6057 // from internal hardware
6058 .de (1'b0),
6059 .d ('0),
6060
6061 // to internal hardware
6062 .qe (),
6063 .q (reg2hw.bank0_info0_page_cfg[7].en.q),
6064 .ds (),
6065
6066 // to register interface (read)
6067 .qs (bank0_info0_page_cfg_7_en_7_qs)
6068 );
6069
6070 // F[rd_en_7]: 7:4
6071 prim_subreg #(
6072 .DW (4),
6073 .SwAccess(prim_subreg_pkg::SwAccessRW),
6074 .RESVAL (4'h9),
6075 .Mubi (1'b1)
6076 ) u_bank0_info0_page_cfg_7_rd_en_7 (
6077 .clk_i (clk_i),
6078 .rst_ni (rst_ni),
6079
6080 // from register interface
6081 .we (bank0_info0_page_cfg_7_gated_we),
6082 .wd (bank0_info0_page_cfg_7_rd_en_7_wd),
6083
6084 // from internal hardware
6085 .de (1'b0),
6086 .d ('0),
6087
6088 // to internal hardware
6089 .qe (),
6090 .q (reg2hw.bank0_info0_page_cfg[7].rd_en.q),
6091 .ds (),
6092
6093 // to register interface (read)
6094 .qs (bank0_info0_page_cfg_7_rd_en_7_qs)
6095 );
6096
6097 // F[prog_en_7]: 11:8
6098 prim_subreg #(
6099 .DW (4),
6100 .SwAccess(prim_subreg_pkg::SwAccessRW),
6101 .RESVAL (4'h9),
6102 .Mubi (1'b1)
6103 ) u_bank0_info0_page_cfg_7_prog_en_7 (
6104 .clk_i (clk_i),
6105 .rst_ni (rst_ni),
6106
6107 // from register interface
6108 .we (bank0_info0_page_cfg_7_gated_we),
6109 .wd (bank0_info0_page_cfg_7_prog_en_7_wd),
6110
6111 // from internal hardware
6112 .de (1'b0),
6113 .d ('0),
6114
6115 // to internal hardware
6116 .qe (),
6117 .q (reg2hw.bank0_info0_page_cfg[7].prog_en.q),
6118 .ds (),
6119
6120 // to register interface (read)
6121 .qs (bank0_info0_page_cfg_7_prog_en_7_qs)
6122 );
6123
6124 // F[erase_en_7]: 15:12
6125 prim_subreg #(
6126 .DW (4),
6127 .SwAccess(prim_subreg_pkg::SwAccessRW),
6128 .RESVAL (4'h9),
6129 .Mubi (1'b1)
6130 ) u_bank0_info0_page_cfg_7_erase_en_7 (
6131 .clk_i (clk_i),
6132 .rst_ni (rst_ni),
6133
6134 // from register interface
6135 .we (bank0_info0_page_cfg_7_gated_we),
6136 .wd (bank0_info0_page_cfg_7_erase_en_7_wd),
6137
6138 // from internal hardware
6139 .de (1'b0),
6140 .d ('0),
6141
6142 // to internal hardware
6143 .qe (),
6144 .q (reg2hw.bank0_info0_page_cfg[7].erase_en.q),
6145 .ds (),
6146
6147 // to register interface (read)
6148 .qs (bank0_info0_page_cfg_7_erase_en_7_qs)
6149 );
6150
6151 // F[scramble_en_7]: 19:16
6152 prim_subreg #(
6153 .DW (4),
6154 .SwAccess(prim_subreg_pkg::SwAccessRW),
6155 .RESVAL (4'h9),
6156 .Mubi (1'b1)
6157 ) u_bank0_info0_page_cfg_7_scramble_en_7 (
6158 .clk_i (clk_i),
6159 .rst_ni (rst_ni),
6160
6161 // from register interface
6162 .we (bank0_info0_page_cfg_7_gated_we),
6163 .wd (bank0_info0_page_cfg_7_scramble_en_7_wd),
6164
6165 // from internal hardware
6166 .de (1'b0),
6167 .d ('0),
6168
6169 // to internal hardware
6170 .qe (),
6171 .q (reg2hw.bank0_info0_page_cfg[7].scramble_en.q),
6172 .ds (),
6173
6174 // to register interface (read)
6175 .qs (bank0_info0_page_cfg_7_scramble_en_7_qs)
6176 );
6177
6178 // F[ecc_en_7]: 23:20
6179 prim_subreg #(
6180 .DW (4),
6181 .SwAccess(prim_subreg_pkg::SwAccessRW),
6182 .RESVAL (4'h9),
6183 .Mubi (1'b1)
6184 ) u_bank0_info0_page_cfg_7_ecc_en_7 (
6185 .clk_i (clk_i),
6186 .rst_ni (rst_ni),
6187
6188 // from register interface
6189 .we (bank0_info0_page_cfg_7_gated_we),
6190 .wd (bank0_info0_page_cfg_7_ecc_en_7_wd),
6191
6192 // from internal hardware
6193 .de (1'b0),
6194 .d ('0),
6195
6196 // to internal hardware
6197 .qe (),
6198 .q (reg2hw.bank0_info0_page_cfg[7].ecc_en.q),
6199 .ds (),
6200
6201 // to register interface (read)
6202 .qs (bank0_info0_page_cfg_7_ecc_en_7_qs)
6203 );
6204
6205 // F[he_en_7]: 27:24
6206 prim_subreg #(
6207 .DW (4),
6208 .SwAccess(prim_subreg_pkg::SwAccessRW),
6209 .RESVAL (4'h9),
6210 .Mubi (1'b1)
6211 ) u_bank0_info0_page_cfg_7_he_en_7 (
6212 .clk_i (clk_i),
6213 .rst_ni (rst_ni),
6214
6215 // from register interface
6216 .we (bank0_info0_page_cfg_7_gated_we),
6217 .wd (bank0_info0_page_cfg_7_he_en_7_wd),
6218
6219 // from internal hardware
6220 .de (1'b0),
6221 .d ('0),
6222
6223 // to internal hardware
6224 .qe (),
6225 .q (reg2hw.bank0_info0_page_cfg[7].he_en.q),
6226 .ds (),
6227
6228 // to register interface (read)
6229 .qs (bank0_info0_page_cfg_7_he_en_7_qs)
6230 );
6231
6232
6233 // Subregister 8 of Multireg bank0_info0_page_cfg
6234 // R[bank0_info0_page_cfg_8]: V(False)
6235 // Create REGWEN-gated WE signal
6236 logic bank0_info0_page_cfg_8_gated_we;
6237 1/1 assign bank0_info0_page_cfg_8_gated_we = bank0_info0_page_cfg_8_we & bank0_info0_regwen_8_qs;
Tests: T1 T2 T3
6238 // F[en_8]: 3:0
6239 prim_subreg #(
6240 .DW (4),
6241 .SwAccess(prim_subreg_pkg::SwAccessRW),
6242 .RESVAL (4'h9),
6243 .Mubi (1'b1)
6244 ) u_bank0_info0_page_cfg_8_en_8 (
6245 .clk_i (clk_i),
6246 .rst_ni (rst_ni),
6247
6248 // from register interface
6249 .we (bank0_info0_page_cfg_8_gated_we),
6250 .wd (bank0_info0_page_cfg_8_en_8_wd),
6251
6252 // from internal hardware
6253 .de (1'b0),
6254 .d ('0),
6255
6256 // to internal hardware
6257 .qe (),
6258 .q (reg2hw.bank0_info0_page_cfg[8].en.q),
6259 .ds (),
6260
6261 // to register interface (read)
6262 .qs (bank0_info0_page_cfg_8_en_8_qs)
6263 );
6264
6265 // F[rd_en_8]: 7:4
6266 prim_subreg #(
6267 .DW (4),
6268 .SwAccess(prim_subreg_pkg::SwAccessRW),
6269 .RESVAL (4'h9),
6270 .Mubi (1'b1)
6271 ) u_bank0_info0_page_cfg_8_rd_en_8 (
6272 .clk_i (clk_i),
6273 .rst_ni (rst_ni),
6274
6275 // from register interface
6276 .we (bank0_info0_page_cfg_8_gated_we),
6277 .wd (bank0_info0_page_cfg_8_rd_en_8_wd),
6278
6279 // from internal hardware
6280 .de (1'b0),
6281 .d ('0),
6282
6283 // to internal hardware
6284 .qe (),
6285 .q (reg2hw.bank0_info0_page_cfg[8].rd_en.q),
6286 .ds (),
6287
6288 // to register interface (read)
6289 .qs (bank0_info0_page_cfg_8_rd_en_8_qs)
6290 );
6291
6292 // F[prog_en_8]: 11:8
6293 prim_subreg #(
6294 .DW (4),
6295 .SwAccess(prim_subreg_pkg::SwAccessRW),
6296 .RESVAL (4'h9),
6297 .Mubi (1'b1)
6298 ) u_bank0_info0_page_cfg_8_prog_en_8 (
6299 .clk_i (clk_i),
6300 .rst_ni (rst_ni),
6301
6302 // from register interface
6303 .we (bank0_info0_page_cfg_8_gated_we),
6304 .wd (bank0_info0_page_cfg_8_prog_en_8_wd),
6305
6306 // from internal hardware
6307 .de (1'b0),
6308 .d ('0),
6309
6310 // to internal hardware
6311 .qe (),
6312 .q (reg2hw.bank0_info0_page_cfg[8].prog_en.q),
6313 .ds (),
6314
6315 // to register interface (read)
6316 .qs (bank0_info0_page_cfg_8_prog_en_8_qs)
6317 );
6318
6319 // F[erase_en_8]: 15:12
6320 prim_subreg #(
6321 .DW (4),
6322 .SwAccess(prim_subreg_pkg::SwAccessRW),
6323 .RESVAL (4'h9),
6324 .Mubi (1'b1)
6325 ) u_bank0_info0_page_cfg_8_erase_en_8 (
6326 .clk_i (clk_i),
6327 .rst_ni (rst_ni),
6328
6329 // from register interface
6330 .we (bank0_info0_page_cfg_8_gated_we),
6331 .wd (bank0_info0_page_cfg_8_erase_en_8_wd),
6332
6333 // from internal hardware
6334 .de (1'b0),
6335 .d ('0),
6336
6337 // to internal hardware
6338 .qe (),
6339 .q (reg2hw.bank0_info0_page_cfg[8].erase_en.q),
6340 .ds (),
6341
6342 // to register interface (read)
6343 .qs (bank0_info0_page_cfg_8_erase_en_8_qs)
6344 );
6345
6346 // F[scramble_en_8]: 19:16
6347 prim_subreg #(
6348 .DW (4),
6349 .SwAccess(prim_subreg_pkg::SwAccessRW),
6350 .RESVAL (4'h9),
6351 .Mubi (1'b1)
6352 ) u_bank0_info0_page_cfg_8_scramble_en_8 (
6353 .clk_i (clk_i),
6354 .rst_ni (rst_ni),
6355
6356 // from register interface
6357 .we (bank0_info0_page_cfg_8_gated_we),
6358 .wd (bank0_info0_page_cfg_8_scramble_en_8_wd),
6359
6360 // from internal hardware
6361 .de (1'b0),
6362 .d ('0),
6363
6364 // to internal hardware
6365 .qe (),
6366 .q (reg2hw.bank0_info0_page_cfg[8].scramble_en.q),
6367 .ds (),
6368
6369 // to register interface (read)
6370 .qs (bank0_info0_page_cfg_8_scramble_en_8_qs)
6371 );
6372
6373 // F[ecc_en_8]: 23:20
6374 prim_subreg #(
6375 .DW (4),
6376 .SwAccess(prim_subreg_pkg::SwAccessRW),
6377 .RESVAL (4'h9),
6378 .Mubi (1'b1)
6379 ) u_bank0_info0_page_cfg_8_ecc_en_8 (
6380 .clk_i (clk_i),
6381 .rst_ni (rst_ni),
6382
6383 // from register interface
6384 .we (bank0_info0_page_cfg_8_gated_we),
6385 .wd (bank0_info0_page_cfg_8_ecc_en_8_wd),
6386
6387 // from internal hardware
6388 .de (1'b0),
6389 .d ('0),
6390
6391 // to internal hardware
6392 .qe (),
6393 .q (reg2hw.bank0_info0_page_cfg[8].ecc_en.q),
6394 .ds (),
6395
6396 // to register interface (read)
6397 .qs (bank0_info0_page_cfg_8_ecc_en_8_qs)
6398 );
6399
6400 // F[he_en_8]: 27:24
6401 prim_subreg #(
6402 .DW (4),
6403 .SwAccess(prim_subreg_pkg::SwAccessRW),
6404 .RESVAL (4'h9),
6405 .Mubi (1'b1)
6406 ) u_bank0_info0_page_cfg_8_he_en_8 (
6407 .clk_i (clk_i),
6408 .rst_ni (rst_ni),
6409
6410 // from register interface
6411 .we (bank0_info0_page_cfg_8_gated_we),
6412 .wd (bank0_info0_page_cfg_8_he_en_8_wd),
6413
6414 // from internal hardware
6415 .de (1'b0),
6416 .d ('0),
6417
6418 // to internal hardware
6419 .qe (),
6420 .q (reg2hw.bank0_info0_page_cfg[8].he_en.q),
6421 .ds (),
6422
6423 // to register interface (read)
6424 .qs (bank0_info0_page_cfg_8_he_en_8_qs)
6425 );
6426
6427
6428 // Subregister 9 of Multireg bank0_info0_page_cfg
6429 // R[bank0_info0_page_cfg_9]: V(False)
6430 // Create REGWEN-gated WE signal
6431 logic bank0_info0_page_cfg_9_gated_we;
6432 1/1 assign bank0_info0_page_cfg_9_gated_we = bank0_info0_page_cfg_9_we & bank0_info0_regwen_9_qs;
Tests: T1 T2 T3
6433 // F[en_9]: 3:0
6434 prim_subreg #(
6435 .DW (4),
6436 .SwAccess(prim_subreg_pkg::SwAccessRW),
6437 .RESVAL (4'h9),
6438 .Mubi (1'b1)
6439 ) u_bank0_info0_page_cfg_9_en_9 (
6440 .clk_i (clk_i),
6441 .rst_ni (rst_ni),
6442
6443 // from register interface
6444 .we (bank0_info0_page_cfg_9_gated_we),
6445 .wd (bank0_info0_page_cfg_9_en_9_wd),
6446
6447 // from internal hardware
6448 .de (1'b0),
6449 .d ('0),
6450
6451 // to internal hardware
6452 .qe (),
6453 .q (reg2hw.bank0_info0_page_cfg[9].en.q),
6454 .ds (),
6455
6456 // to register interface (read)
6457 .qs (bank0_info0_page_cfg_9_en_9_qs)
6458 );
6459
6460 // F[rd_en_9]: 7:4
6461 prim_subreg #(
6462 .DW (4),
6463 .SwAccess(prim_subreg_pkg::SwAccessRW),
6464 .RESVAL (4'h9),
6465 .Mubi (1'b1)
6466 ) u_bank0_info0_page_cfg_9_rd_en_9 (
6467 .clk_i (clk_i),
6468 .rst_ni (rst_ni),
6469
6470 // from register interface
6471 .we (bank0_info0_page_cfg_9_gated_we),
6472 .wd (bank0_info0_page_cfg_9_rd_en_9_wd),
6473
6474 // from internal hardware
6475 .de (1'b0),
6476 .d ('0),
6477
6478 // to internal hardware
6479 .qe (),
6480 .q (reg2hw.bank0_info0_page_cfg[9].rd_en.q),
6481 .ds (),
6482
6483 // to register interface (read)
6484 .qs (bank0_info0_page_cfg_9_rd_en_9_qs)
6485 );
6486
6487 // F[prog_en_9]: 11:8
6488 prim_subreg #(
6489 .DW (4),
6490 .SwAccess(prim_subreg_pkg::SwAccessRW),
6491 .RESVAL (4'h9),
6492 .Mubi (1'b1)
6493 ) u_bank0_info0_page_cfg_9_prog_en_9 (
6494 .clk_i (clk_i),
6495 .rst_ni (rst_ni),
6496
6497 // from register interface
6498 .we (bank0_info0_page_cfg_9_gated_we),
6499 .wd (bank0_info0_page_cfg_9_prog_en_9_wd),
6500
6501 // from internal hardware
6502 .de (1'b0),
6503 .d ('0),
6504
6505 // to internal hardware
6506 .qe (),
6507 .q (reg2hw.bank0_info0_page_cfg[9].prog_en.q),
6508 .ds (),
6509
6510 // to register interface (read)
6511 .qs (bank0_info0_page_cfg_9_prog_en_9_qs)
6512 );
6513
6514 // F[erase_en_9]: 15:12
6515 prim_subreg #(
6516 .DW (4),
6517 .SwAccess(prim_subreg_pkg::SwAccessRW),
6518 .RESVAL (4'h9),
6519 .Mubi (1'b1)
6520 ) u_bank0_info0_page_cfg_9_erase_en_9 (
6521 .clk_i (clk_i),
6522 .rst_ni (rst_ni),
6523
6524 // from register interface
6525 .we (bank0_info0_page_cfg_9_gated_we),
6526 .wd (bank0_info0_page_cfg_9_erase_en_9_wd),
6527
6528 // from internal hardware
6529 .de (1'b0),
6530 .d ('0),
6531
6532 // to internal hardware
6533 .qe (),
6534 .q (reg2hw.bank0_info0_page_cfg[9].erase_en.q),
6535 .ds (),
6536
6537 // to register interface (read)
6538 .qs (bank0_info0_page_cfg_9_erase_en_9_qs)
6539 );
6540
6541 // F[scramble_en_9]: 19:16
6542 prim_subreg #(
6543 .DW (4),
6544 .SwAccess(prim_subreg_pkg::SwAccessRW),
6545 .RESVAL (4'h9),
6546 .Mubi (1'b1)
6547 ) u_bank0_info0_page_cfg_9_scramble_en_9 (
6548 .clk_i (clk_i),
6549 .rst_ni (rst_ni),
6550
6551 // from register interface
6552 .we (bank0_info0_page_cfg_9_gated_we),
6553 .wd (bank0_info0_page_cfg_9_scramble_en_9_wd),
6554
6555 // from internal hardware
6556 .de (1'b0),
6557 .d ('0),
6558
6559 // to internal hardware
6560 .qe (),
6561 .q (reg2hw.bank0_info0_page_cfg[9].scramble_en.q),
6562 .ds (),
6563
6564 // to register interface (read)
6565 .qs (bank0_info0_page_cfg_9_scramble_en_9_qs)
6566 );
6567
6568 // F[ecc_en_9]: 23:20
6569 prim_subreg #(
6570 .DW (4),
6571 .SwAccess(prim_subreg_pkg::SwAccessRW),
6572 .RESVAL (4'h9),
6573 .Mubi (1'b1)
6574 ) u_bank0_info0_page_cfg_9_ecc_en_9 (
6575 .clk_i (clk_i),
6576 .rst_ni (rst_ni),
6577
6578 // from register interface
6579 .we (bank0_info0_page_cfg_9_gated_we),
6580 .wd (bank0_info0_page_cfg_9_ecc_en_9_wd),
6581
6582 // from internal hardware
6583 .de (1'b0),
6584 .d ('0),
6585
6586 // to internal hardware
6587 .qe (),
6588 .q (reg2hw.bank0_info0_page_cfg[9].ecc_en.q),
6589 .ds (),
6590
6591 // to register interface (read)
6592 .qs (bank0_info0_page_cfg_9_ecc_en_9_qs)
6593 );
6594
6595 // F[he_en_9]: 27:24
6596 prim_subreg #(
6597 .DW (4),
6598 .SwAccess(prim_subreg_pkg::SwAccessRW),
6599 .RESVAL (4'h9),
6600 .Mubi (1'b1)
6601 ) u_bank0_info0_page_cfg_9_he_en_9 (
6602 .clk_i (clk_i),
6603 .rst_ni (rst_ni),
6604
6605 // from register interface
6606 .we (bank0_info0_page_cfg_9_gated_we),
6607 .wd (bank0_info0_page_cfg_9_he_en_9_wd),
6608
6609 // from internal hardware
6610 .de (1'b0),
6611 .d ('0),
6612
6613 // to internal hardware
6614 .qe (),
6615 .q (reg2hw.bank0_info0_page_cfg[9].he_en.q),
6616 .ds (),
6617
6618 // to register interface (read)
6619 .qs (bank0_info0_page_cfg_9_he_en_9_qs)
6620 );
6621
6622
6623 // Subregister 0 of Multireg bank0_info1_regwen
6624 // R[bank0_info1_regwen]: V(False)
6625 prim_subreg #(
6626 .DW (1),
6627 .SwAccess(prim_subreg_pkg::SwAccessW0C),
6628 .RESVAL (1'h1),
6629 .Mubi (1'b0)
6630 ) u_bank0_info1_regwen (
6631 .clk_i (clk_i),
6632 .rst_ni (rst_ni),
6633
6634 // from register interface
6635 .we (bank0_info1_regwen_we),
6636 .wd (bank0_info1_regwen_wd),
6637
6638 // from internal hardware
6639 .de (1'b0),
6640 .d ('0),
6641
6642 // to internal hardware
6643 .qe (),
6644 .q (),
6645 .ds (),
6646
6647 // to register interface (read)
6648 .qs (bank0_info1_regwen_qs)
6649 );
6650
6651
6652 // Subregister 0 of Multireg bank0_info1_page_cfg
6653 // R[bank0_info1_page_cfg]: V(False)
6654 // Create REGWEN-gated WE signal
6655 logic bank0_info1_page_cfg_gated_we;
6656 1/1 assign bank0_info1_page_cfg_gated_we = bank0_info1_page_cfg_we & bank0_info1_regwen_qs;
Tests: T1 T2 T3
6657 // F[en_0]: 3:0
6658 prim_subreg #(
6659 .DW (4),
6660 .SwAccess(prim_subreg_pkg::SwAccessRW),
6661 .RESVAL (4'h9),
6662 .Mubi (1'b1)
6663 ) u_bank0_info1_page_cfg_en_0 (
6664 .clk_i (clk_i),
6665 .rst_ni (rst_ni),
6666
6667 // from register interface
6668 .we (bank0_info1_page_cfg_gated_we),
6669 .wd (bank0_info1_page_cfg_en_0_wd),
6670
6671 // from internal hardware
6672 .de (1'b0),
6673 .d ('0),
6674
6675 // to internal hardware
6676 .qe (),
6677 .q (reg2hw.bank0_info1_page_cfg[0].en.q),
6678 .ds (),
6679
6680 // to register interface (read)
6681 .qs (bank0_info1_page_cfg_en_0_qs)
6682 );
6683
6684 // F[rd_en_0]: 7:4
6685 prim_subreg #(
6686 .DW (4),
6687 .SwAccess(prim_subreg_pkg::SwAccessRW),
6688 .RESVAL (4'h9),
6689 .Mubi (1'b1)
6690 ) u_bank0_info1_page_cfg_rd_en_0 (
6691 .clk_i (clk_i),
6692 .rst_ni (rst_ni),
6693
6694 // from register interface
6695 .we (bank0_info1_page_cfg_gated_we),
6696 .wd (bank0_info1_page_cfg_rd_en_0_wd),
6697
6698 // from internal hardware
6699 .de (1'b0),
6700 .d ('0),
6701
6702 // to internal hardware
6703 .qe (),
6704 .q (reg2hw.bank0_info1_page_cfg[0].rd_en.q),
6705 .ds (),
6706
6707 // to register interface (read)
6708 .qs (bank0_info1_page_cfg_rd_en_0_qs)
6709 );
6710
6711 // F[prog_en_0]: 11:8
6712 prim_subreg #(
6713 .DW (4),
6714 .SwAccess(prim_subreg_pkg::SwAccessRW),
6715 .RESVAL (4'h9),
6716 .Mubi (1'b1)
6717 ) u_bank0_info1_page_cfg_prog_en_0 (
6718 .clk_i (clk_i),
6719 .rst_ni (rst_ni),
6720
6721 // from register interface
6722 .we (bank0_info1_page_cfg_gated_we),
6723 .wd (bank0_info1_page_cfg_prog_en_0_wd),
6724
6725 // from internal hardware
6726 .de (1'b0),
6727 .d ('0),
6728
6729 // to internal hardware
6730 .qe (),
6731 .q (reg2hw.bank0_info1_page_cfg[0].prog_en.q),
6732 .ds (),
6733
6734 // to register interface (read)
6735 .qs (bank0_info1_page_cfg_prog_en_0_qs)
6736 );
6737
6738 // F[erase_en_0]: 15:12
6739 prim_subreg #(
6740 .DW (4),
6741 .SwAccess(prim_subreg_pkg::SwAccessRW),
6742 .RESVAL (4'h9),
6743 .Mubi (1'b1)
6744 ) u_bank0_info1_page_cfg_erase_en_0 (
6745 .clk_i (clk_i),
6746 .rst_ni (rst_ni),
6747
6748 // from register interface
6749 .we (bank0_info1_page_cfg_gated_we),
6750 .wd (bank0_info1_page_cfg_erase_en_0_wd),
6751
6752 // from internal hardware
6753 .de (1'b0),
6754 .d ('0),
6755
6756 // to internal hardware
6757 .qe (),
6758 .q (reg2hw.bank0_info1_page_cfg[0].erase_en.q),
6759 .ds (),
6760
6761 // to register interface (read)
6762 .qs (bank0_info1_page_cfg_erase_en_0_qs)
6763 );
6764
6765 // F[scramble_en_0]: 19:16
6766 prim_subreg #(
6767 .DW (4),
6768 .SwAccess(prim_subreg_pkg::SwAccessRW),
6769 .RESVAL (4'h9),
6770 .Mubi (1'b1)
6771 ) u_bank0_info1_page_cfg_scramble_en_0 (
6772 .clk_i (clk_i),
6773 .rst_ni (rst_ni),
6774
6775 // from register interface
6776 .we (bank0_info1_page_cfg_gated_we),
6777 .wd (bank0_info1_page_cfg_scramble_en_0_wd),
6778
6779 // from internal hardware
6780 .de (1'b0),
6781 .d ('0),
6782
6783 // to internal hardware
6784 .qe (),
6785 .q (reg2hw.bank0_info1_page_cfg[0].scramble_en.q),
6786 .ds (),
6787
6788 // to register interface (read)
6789 .qs (bank0_info1_page_cfg_scramble_en_0_qs)
6790 );
6791
6792 // F[ecc_en_0]: 23:20
6793 prim_subreg #(
6794 .DW (4),
6795 .SwAccess(prim_subreg_pkg::SwAccessRW),
6796 .RESVAL (4'h9),
6797 .Mubi (1'b1)
6798 ) u_bank0_info1_page_cfg_ecc_en_0 (
6799 .clk_i (clk_i),
6800 .rst_ni (rst_ni),
6801
6802 // from register interface
6803 .we (bank0_info1_page_cfg_gated_we),
6804 .wd (bank0_info1_page_cfg_ecc_en_0_wd),
6805
6806 // from internal hardware
6807 .de (1'b0),
6808 .d ('0),
6809
6810 // to internal hardware
6811 .qe (),
6812 .q (reg2hw.bank0_info1_page_cfg[0].ecc_en.q),
6813 .ds (),
6814
6815 // to register interface (read)
6816 .qs (bank0_info1_page_cfg_ecc_en_0_qs)
6817 );
6818
6819 // F[he_en_0]: 27:24
6820 prim_subreg #(
6821 .DW (4),
6822 .SwAccess(prim_subreg_pkg::SwAccessRW),
6823 .RESVAL (4'h9),
6824 .Mubi (1'b1)
6825 ) u_bank0_info1_page_cfg_he_en_0 (
6826 .clk_i (clk_i),
6827 .rst_ni (rst_ni),
6828
6829 // from register interface
6830 .we (bank0_info1_page_cfg_gated_we),
6831 .wd (bank0_info1_page_cfg_he_en_0_wd),
6832
6833 // from internal hardware
6834 .de (1'b0),
6835 .d ('0),
6836
6837 // to internal hardware
6838 .qe (),
6839 .q (reg2hw.bank0_info1_page_cfg[0].he_en.q),
6840 .ds (),
6841
6842 // to register interface (read)
6843 .qs (bank0_info1_page_cfg_he_en_0_qs)
6844 );
6845
6846
6847 // Subregister 0 of Multireg bank0_info2_regwen
6848 // R[bank0_info2_regwen_0]: V(False)
6849 prim_subreg #(
6850 .DW (1),
6851 .SwAccess(prim_subreg_pkg::SwAccessW0C),
6852 .RESVAL (1'h1),
6853 .Mubi (1'b0)
6854 ) u_bank0_info2_regwen_0 (
6855 .clk_i (clk_i),
6856 .rst_ni (rst_ni),
6857
6858 // from register interface
6859 .we (bank0_info2_regwen_0_we),
6860 .wd (bank0_info2_regwen_0_wd),
6861
6862 // from internal hardware
6863 .de (1'b0),
6864 .d ('0),
6865
6866 // to internal hardware
6867 .qe (),
6868 .q (),
6869 .ds (),
6870
6871 // to register interface (read)
6872 .qs (bank0_info2_regwen_0_qs)
6873 );
6874
6875
6876 // Subregister 1 of Multireg bank0_info2_regwen
6877 // R[bank0_info2_regwen_1]: V(False)
6878 prim_subreg #(
6879 .DW (1),
6880 .SwAccess(prim_subreg_pkg::SwAccessW0C),
6881 .RESVAL (1'h1),
6882 .Mubi (1'b0)
6883 ) u_bank0_info2_regwen_1 (
6884 .clk_i (clk_i),
6885 .rst_ni (rst_ni),
6886
6887 // from register interface
6888 .we (bank0_info2_regwen_1_we),
6889 .wd (bank0_info2_regwen_1_wd),
6890
6891 // from internal hardware
6892 .de (1'b0),
6893 .d ('0),
6894
6895 // to internal hardware
6896 .qe (),
6897 .q (),
6898 .ds (),
6899
6900 // to register interface (read)
6901 .qs (bank0_info2_regwen_1_qs)
6902 );
6903
6904
6905 // Subregister 0 of Multireg bank0_info2_page_cfg
6906 // R[bank0_info2_page_cfg_0]: V(False)
6907 // Create REGWEN-gated WE signal
6908 logic bank0_info2_page_cfg_0_gated_we;
6909 1/1 assign bank0_info2_page_cfg_0_gated_we = bank0_info2_page_cfg_0_we & bank0_info2_regwen_0_qs;
Tests: T1 T2 T3
6910 // F[en_0]: 3:0
6911 prim_subreg #(
6912 .DW (4),
6913 .SwAccess(prim_subreg_pkg::SwAccessRW),
6914 .RESVAL (4'h9),
6915 .Mubi (1'b1)
6916 ) u_bank0_info2_page_cfg_0_en_0 (
6917 .clk_i (clk_i),
6918 .rst_ni (rst_ni),
6919
6920 // from register interface
6921 .we (bank0_info2_page_cfg_0_gated_we),
6922 .wd (bank0_info2_page_cfg_0_en_0_wd),
6923
6924 // from internal hardware
6925 .de (1'b0),
6926 .d ('0),
6927
6928 // to internal hardware
6929 .qe (),
6930 .q (reg2hw.bank0_info2_page_cfg[0].en.q),
6931 .ds (),
6932
6933 // to register interface (read)
6934 .qs (bank0_info2_page_cfg_0_en_0_qs)
6935 );
6936
6937 // F[rd_en_0]: 7:4
6938 prim_subreg #(
6939 .DW (4),
6940 .SwAccess(prim_subreg_pkg::SwAccessRW),
6941 .RESVAL (4'h9),
6942 .Mubi (1'b1)
6943 ) u_bank0_info2_page_cfg_0_rd_en_0 (
6944 .clk_i (clk_i),
6945 .rst_ni (rst_ni),
6946
6947 // from register interface
6948 .we (bank0_info2_page_cfg_0_gated_we),
6949 .wd (bank0_info2_page_cfg_0_rd_en_0_wd),
6950
6951 // from internal hardware
6952 .de (1'b0),
6953 .d ('0),
6954
6955 // to internal hardware
6956 .qe (),
6957 .q (reg2hw.bank0_info2_page_cfg[0].rd_en.q),
6958 .ds (),
6959
6960 // to register interface (read)
6961 .qs (bank0_info2_page_cfg_0_rd_en_0_qs)
6962 );
6963
6964 // F[prog_en_0]: 11:8
6965 prim_subreg #(
6966 .DW (4),
6967 .SwAccess(prim_subreg_pkg::SwAccessRW),
6968 .RESVAL (4'h9),
6969 .Mubi (1'b1)
6970 ) u_bank0_info2_page_cfg_0_prog_en_0 (
6971 .clk_i (clk_i),
6972 .rst_ni (rst_ni),
6973
6974 // from register interface
6975 .we (bank0_info2_page_cfg_0_gated_we),
6976 .wd (bank0_info2_page_cfg_0_prog_en_0_wd),
6977
6978 // from internal hardware
6979 .de (1'b0),
6980 .d ('0),
6981
6982 // to internal hardware
6983 .qe (),
6984 .q (reg2hw.bank0_info2_page_cfg[0].prog_en.q),
6985 .ds (),
6986
6987 // to register interface (read)
6988 .qs (bank0_info2_page_cfg_0_prog_en_0_qs)
6989 );
6990
6991 // F[erase_en_0]: 15:12
6992 prim_subreg #(
6993 .DW (4),
6994 .SwAccess(prim_subreg_pkg::SwAccessRW),
6995 .RESVAL (4'h9),
6996 .Mubi (1'b1)
6997 ) u_bank0_info2_page_cfg_0_erase_en_0 (
6998 .clk_i (clk_i),
6999 .rst_ni (rst_ni),
7000
7001 // from register interface
7002 .we (bank0_info2_page_cfg_0_gated_we),
7003 .wd (bank0_info2_page_cfg_0_erase_en_0_wd),
7004
7005 // from internal hardware
7006 .de (1'b0),
7007 .d ('0),
7008
7009 // to internal hardware
7010 .qe (),
7011 .q (reg2hw.bank0_info2_page_cfg[0].erase_en.q),
7012 .ds (),
7013
7014 // to register interface (read)
7015 .qs (bank0_info2_page_cfg_0_erase_en_0_qs)
7016 );
7017
7018 // F[scramble_en_0]: 19:16
7019 prim_subreg #(
7020 .DW (4),
7021 .SwAccess(prim_subreg_pkg::SwAccessRW),
7022 .RESVAL (4'h9),
7023 .Mubi (1'b1)
7024 ) u_bank0_info2_page_cfg_0_scramble_en_0 (
7025 .clk_i (clk_i),
7026 .rst_ni (rst_ni),
7027
7028 // from register interface
7029 .we (bank0_info2_page_cfg_0_gated_we),
7030 .wd (bank0_info2_page_cfg_0_scramble_en_0_wd),
7031
7032 // from internal hardware
7033 .de (1'b0),
7034 .d ('0),
7035
7036 // to internal hardware
7037 .qe (),
7038 .q (reg2hw.bank0_info2_page_cfg[0].scramble_en.q),
7039 .ds (),
7040
7041 // to register interface (read)
7042 .qs (bank0_info2_page_cfg_0_scramble_en_0_qs)
7043 );
7044
7045 // F[ecc_en_0]: 23:20
7046 prim_subreg #(
7047 .DW (4),
7048 .SwAccess(prim_subreg_pkg::SwAccessRW),
7049 .RESVAL (4'h9),
7050 .Mubi (1'b1)
7051 ) u_bank0_info2_page_cfg_0_ecc_en_0 (
7052 .clk_i (clk_i),
7053 .rst_ni (rst_ni),
7054
7055 // from register interface
7056 .we (bank0_info2_page_cfg_0_gated_we),
7057 .wd (bank0_info2_page_cfg_0_ecc_en_0_wd),
7058
7059 // from internal hardware
7060 .de (1'b0),
7061 .d ('0),
7062
7063 // to internal hardware
7064 .qe (),
7065 .q (reg2hw.bank0_info2_page_cfg[0].ecc_en.q),
7066 .ds (),
7067
7068 // to register interface (read)
7069 .qs (bank0_info2_page_cfg_0_ecc_en_0_qs)
7070 );
7071
7072 // F[he_en_0]: 27:24
7073 prim_subreg #(
7074 .DW (4),
7075 .SwAccess(prim_subreg_pkg::SwAccessRW),
7076 .RESVAL (4'h9),
7077 .Mubi (1'b1)
7078 ) u_bank0_info2_page_cfg_0_he_en_0 (
7079 .clk_i (clk_i),
7080 .rst_ni (rst_ni),
7081
7082 // from register interface
7083 .we (bank0_info2_page_cfg_0_gated_we),
7084 .wd (bank0_info2_page_cfg_0_he_en_0_wd),
7085
7086 // from internal hardware
7087 .de (1'b0),
7088 .d ('0),
7089
7090 // to internal hardware
7091 .qe (),
7092 .q (reg2hw.bank0_info2_page_cfg[0].he_en.q),
7093 .ds (),
7094
7095 // to register interface (read)
7096 .qs (bank0_info2_page_cfg_0_he_en_0_qs)
7097 );
7098
7099
7100 // Subregister 1 of Multireg bank0_info2_page_cfg
7101 // R[bank0_info2_page_cfg_1]: V(False)
7102 // Create REGWEN-gated WE signal
7103 logic bank0_info2_page_cfg_1_gated_we;
7104 1/1 assign bank0_info2_page_cfg_1_gated_we = bank0_info2_page_cfg_1_we & bank0_info2_regwen_1_qs;
Tests: T1 T2 T3
7105 // F[en_1]: 3:0
7106 prim_subreg #(
7107 .DW (4),
7108 .SwAccess(prim_subreg_pkg::SwAccessRW),
7109 .RESVAL (4'h9),
7110 .Mubi (1'b1)
7111 ) u_bank0_info2_page_cfg_1_en_1 (
7112 .clk_i (clk_i),
7113 .rst_ni (rst_ni),
7114
7115 // from register interface
7116 .we (bank0_info2_page_cfg_1_gated_we),
7117 .wd (bank0_info2_page_cfg_1_en_1_wd),
7118
7119 // from internal hardware
7120 .de (1'b0),
7121 .d ('0),
7122
7123 // to internal hardware
7124 .qe (),
7125 .q (reg2hw.bank0_info2_page_cfg[1].en.q),
7126 .ds (),
7127
7128 // to register interface (read)
7129 .qs (bank0_info2_page_cfg_1_en_1_qs)
7130 );
7131
7132 // F[rd_en_1]: 7:4
7133 prim_subreg #(
7134 .DW (4),
7135 .SwAccess(prim_subreg_pkg::SwAccessRW),
7136 .RESVAL (4'h9),
7137 .Mubi (1'b1)
7138 ) u_bank0_info2_page_cfg_1_rd_en_1 (
7139 .clk_i (clk_i),
7140 .rst_ni (rst_ni),
7141
7142 // from register interface
7143 .we (bank0_info2_page_cfg_1_gated_we),
7144 .wd (bank0_info2_page_cfg_1_rd_en_1_wd),
7145
7146 // from internal hardware
7147 .de (1'b0),
7148 .d ('0),
7149
7150 // to internal hardware
7151 .qe (),
7152 .q (reg2hw.bank0_info2_page_cfg[1].rd_en.q),
7153 .ds (),
7154
7155 // to register interface (read)
7156 .qs (bank0_info2_page_cfg_1_rd_en_1_qs)
7157 );
7158
7159 // F[prog_en_1]: 11:8
7160 prim_subreg #(
7161 .DW (4),
7162 .SwAccess(prim_subreg_pkg::SwAccessRW),
7163 .RESVAL (4'h9),
7164 .Mubi (1'b1)
7165 ) u_bank0_info2_page_cfg_1_prog_en_1 (
7166 .clk_i (clk_i),
7167 .rst_ni (rst_ni),
7168
7169 // from register interface
7170 .we (bank0_info2_page_cfg_1_gated_we),
7171 .wd (bank0_info2_page_cfg_1_prog_en_1_wd),
7172
7173 // from internal hardware
7174 .de (1'b0),
7175 .d ('0),
7176
7177 // to internal hardware
7178 .qe (),
7179 .q (reg2hw.bank0_info2_page_cfg[1].prog_en.q),
7180 .ds (),
7181
7182 // to register interface (read)
7183 .qs (bank0_info2_page_cfg_1_prog_en_1_qs)
7184 );
7185
7186 // F[erase_en_1]: 15:12
7187 prim_subreg #(
7188 .DW (4),
7189 .SwAccess(prim_subreg_pkg::SwAccessRW),
7190 .RESVAL (4'h9),
7191 .Mubi (1'b1)
7192 ) u_bank0_info2_page_cfg_1_erase_en_1 (
7193 .clk_i (clk_i),
7194 .rst_ni (rst_ni),
7195
7196 // from register interface
7197 .we (bank0_info2_page_cfg_1_gated_we),
7198 .wd (bank0_info2_page_cfg_1_erase_en_1_wd),
7199
7200 // from internal hardware
7201 .de (1'b0),
7202 .d ('0),
7203
7204 // to internal hardware
7205 .qe (),
7206 .q (reg2hw.bank0_info2_page_cfg[1].erase_en.q),
7207 .ds (),
7208
7209 // to register interface (read)
7210 .qs (bank0_info2_page_cfg_1_erase_en_1_qs)
7211 );
7212
7213 // F[scramble_en_1]: 19:16
7214 prim_subreg #(
7215 .DW (4),
7216 .SwAccess(prim_subreg_pkg::SwAccessRW),
7217 .RESVAL (4'h9),
7218 .Mubi (1'b1)
7219 ) u_bank0_info2_page_cfg_1_scramble_en_1 (
7220 .clk_i (clk_i),
7221 .rst_ni (rst_ni),
7222
7223 // from register interface
7224 .we (bank0_info2_page_cfg_1_gated_we),
7225 .wd (bank0_info2_page_cfg_1_scramble_en_1_wd),
7226
7227 // from internal hardware
7228 .de (1'b0),
7229 .d ('0),
7230
7231 // to internal hardware
7232 .qe (),
7233 .q (reg2hw.bank0_info2_page_cfg[1].scramble_en.q),
7234 .ds (),
7235
7236 // to register interface (read)
7237 .qs (bank0_info2_page_cfg_1_scramble_en_1_qs)
7238 );
7239
7240 // F[ecc_en_1]: 23:20
7241 prim_subreg #(
7242 .DW (4),
7243 .SwAccess(prim_subreg_pkg::SwAccessRW),
7244 .RESVAL (4'h9),
7245 .Mubi (1'b1)
7246 ) u_bank0_info2_page_cfg_1_ecc_en_1 (
7247 .clk_i (clk_i),
7248 .rst_ni (rst_ni),
7249
7250 // from register interface
7251 .we (bank0_info2_page_cfg_1_gated_we),
7252 .wd (bank0_info2_page_cfg_1_ecc_en_1_wd),
7253
7254 // from internal hardware
7255 .de (1'b0),
7256 .d ('0),
7257
7258 // to internal hardware
7259 .qe (),
7260 .q (reg2hw.bank0_info2_page_cfg[1].ecc_en.q),
7261 .ds (),
7262
7263 // to register interface (read)
7264 .qs (bank0_info2_page_cfg_1_ecc_en_1_qs)
7265 );
7266
7267 // F[he_en_1]: 27:24
7268 prim_subreg #(
7269 .DW (4),
7270 .SwAccess(prim_subreg_pkg::SwAccessRW),
7271 .RESVAL (4'h9),
7272 .Mubi (1'b1)
7273 ) u_bank0_info2_page_cfg_1_he_en_1 (
7274 .clk_i (clk_i),
7275 .rst_ni (rst_ni),
7276
7277 // from register interface
7278 .we (bank0_info2_page_cfg_1_gated_we),
7279 .wd (bank0_info2_page_cfg_1_he_en_1_wd),
7280
7281 // from internal hardware
7282 .de (1'b0),
7283 .d ('0),
7284
7285 // to internal hardware
7286 .qe (),
7287 .q (reg2hw.bank0_info2_page_cfg[1].he_en.q),
7288 .ds (),
7289
7290 // to register interface (read)
7291 .qs (bank0_info2_page_cfg_1_he_en_1_qs)
7292 );
7293
7294
7295 // Subregister 0 of Multireg bank1_info0_regwen
7296 // R[bank1_info0_regwen_0]: V(False)
7297 prim_subreg #(
7298 .DW (1),
7299 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7300 .RESVAL (1'h1),
7301 .Mubi (1'b0)
7302 ) u_bank1_info0_regwen_0 (
7303 .clk_i (clk_i),
7304 .rst_ni (rst_ni),
7305
7306 // from register interface
7307 .we (bank1_info0_regwen_0_we),
7308 .wd (bank1_info0_regwen_0_wd),
7309
7310 // from internal hardware
7311 .de (1'b0),
7312 .d ('0),
7313
7314 // to internal hardware
7315 .qe (),
7316 .q (),
7317 .ds (),
7318
7319 // to register interface (read)
7320 .qs (bank1_info0_regwen_0_qs)
7321 );
7322
7323
7324 // Subregister 1 of Multireg bank1_info0_regwen
7325 // R[bank1_info0_regwen_1]: V(False)
7326 prim_subreg #(
7327 .DW (1),
7328 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7329 .RESVAL (1'h1),
7330 .Mubi (1'b0)
7331 ) u_bank1_info0_regwen_1 (
7332 .clk_i (clk_i),
7333 .rst_ni (rst_ni),
7334
7335 // from register interface
7336 .we (bank1_info0_regwen_1_we),
7337 .wd (bank1_info0_regwen_1_wd),
7338
7339 // from internal hardware
7340 .de (1'b0),
7341 .d ('0),
7342
7343 // to internal hardware
7344 .qe (),
7345 .q (),
7346 .ds (),
7347
7348 // to register interface (read)
7349 .qs (bank1_info0_regwen_1_qs)
7350 );
7351
7352
7353 // Subregister 2 of Multireg bank1_info0_regwen
7354 // R[bank1_info0_regwen_2]: V(False)
7355 prim_subreg #(
7356 .DW (1),
7357 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7358 .RESVAL (1'h1),
7359 .Mubi (1'b0)
7360 ) u_bank1_info0_regwen_2 (
7361 .clk_i (clk_i),
7362 .rst_ni (rst_ni),
7363
7364 // from register interface
7365 .we (bank1_info0_regwen_2_we),
7366 .wd (bank1_info0_regwen_2_wd),
7367
7368 // from internal hardware
7369 .de (1'b0),
7370 .d ('0),
7371
7372 // to internal hardware
7373 .qe (),
7374 .q (),
7375 .ds (),
7376
7377 // to register interface (read)
7378 .qs (bank1_info0_regwen_2_qs)
7379 );
7380
7381
7382 // Subregister 3 of Multireg bank1_info0_regwen
7383 // R[bank1_info0_regwen_3]: V(False)
7384 prim_subreg #(
7385 .DW (1),
7386 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7387 .RESVAL (1'h1),
7388 .Mubi (1'b0)
7389 ) u_bank1_info0_regwen_3 (
7390 .clk_i (clk_i),
7391 .rst_ni (rst_ni),
7392
7393 // from register interface
7394 .we (bank1_info0_regwen_3_we),
7395 .wd (bank1_info0_regwen_3_wd),
7396
7397 // from internal hardware
7398 .de (1'b0),
7399 .d ('0),
7400
7401 // to internal hardware
7402 .qe (),
7403 .q (),
7404 .ds (),
7405
7406 // to register interface (read)
7407 .qs (bank1_info0_regwen_3_qs)
7408 );
7409
7410
7411 // Subregister 4 of Multireg bank1_info0_regwen
7412 // R[bank1_info0_regwen_4]: V(False)
7413 prim_subreg #(
7414 .DW (1),
7415 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7416 .RESVAL (1'h1),
7417 .Mubi (1'b0)
7418 ) u_bank1_info0_regwen_4 (
7419 .clk_i (clk_i),
7420 .rst_ni (rst_ni),
7421
7422 // from register interface
7423 .we (bank1_info0_regwen_4_we),
7424 .wd (bank1_info0_regwen_4_wd),
7425
7426 // from internal hardware
7427 .de (1'b0),
7428 .d ('0),
7429
7430 // to internal hardware
7431 .qe (),
7432 .q (),
7433 .ds (),
7434
7435 // to register interface (read)
7436 .qs (bank1_info0_regwen_4_qs)
7437 );
7438
7439
7440 // Subregister 5 of Multireg bank1_info0_regwen
7441 // R[bank1_info0_regwen_5]: V(False)
7442 prim_subreg #(
7443 .DW (1),
7444 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7445 .RESVAL (1'h1),
7446 .Mubi (1'b0)
7447 ) u_bank1_info0_regwen_5 (
7448 .clk_i (clk_i),
7449 .rst_ni (rst_ni),
7450
7451 // from register interface
7452 .we (bank1_info0_regwen_5_we),
7453 .wd (bank1_info0_regwen_5_wd),
7454
7455 // from internal hardware
7456 .de (1'b0),
7457 .d ('0),
7458
7459 // to internal hardware
7460 .qe (),
7461 .q (),
7462 .ds (),
7463
7464 // to register interface (read)
7465 .qs (bank1_info0_regwen_5_qs)
7466 );
7467
7468
7469 // Subregister 6 of Multireg bank1_info0_regwen
7470 // R[bank1_info0_regwen_6]: V(False)
7471 prim_subreg #(
7472 .DW (1),
7473 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7474 .RESVAL (1'h1),
7475 .Mubi (1'b0)
7476 ) u_bank1_info0_regwen_6 (
7477 .clk_i (clk_i),
7478 .rst_ni (rst_ni),
7479
7480 // from register interface
7481 .we (bank1_info0_regwen_6_we),
7482 .wd (bank1_info0_regwen_6_wd),
7483
7484 // from internal hardware
7485 .de (1'b0),
7486 .d ('0),
7487
7488 // to internal hardware
7489 .qe (),
7490 .q (),
7491 .ds (),
7492
7493 // to register interface (read)
7494 .qs (bank1_info0_regwen_6_qs)
7495 );
7496
7497
7498 // Subregister 7 of Multireg bank1_info0_regwen
7499 // R[bank1_info0_regwen_7]: V(False)
7500 prim_subreg #(
7501 .DW (1),
7502 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7503 .RESVAL (1'h1),
7504 .Mubi (1'b0)
7505 ) u_bank1_info0_regwen_7 (
7506 .clk_i (clk_i),
7507 .rst_ni (rst_ni),
7508
7509 // from register interface
7510 .we (bank1_info0_regwen_7_we),
7511 .wd (bank1_info0_regwen_7_wd),
7512
7513 // from internal hardware
7514 .de (1'b0),
7515 .d ('0),
7516
7517 // to internal hardware
7518 .qe (),
7519 .q (),
7520 .ds (),
7521
7522 // to register interface (read)
7523 .qs (bank1_info0_regwen_7_qs)
7524 );
7525
7526
7527 // Subregister 8 of Multireg bank1_info0_regwen
7528 // R[bank1_info0_regwen_8]: V(False)
7529 prim_subreg #(
7530 .DW (1),
7531 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7532 .RESVAL (1'h1),
7533 .Mubi (1'b0)
7534 ) u_bank1_info0_regwen_8 (
7535 .clk_i (clk_i),
7536 .rst_ni (rst_ni),
7537
7538 // from register interface
7539 .we (bank1_info0_regwen_8_we),
7540 .wd (bank1_info0_regwen_8_wd),
7541
7542 // from internal hardware
7543 .de (1'b0),
7544 .d ('0),
7545
7546 // to internal hardware
7547 .qe (),
7548 .q (),
7549 .ds (),
7550
7551 // to register interface (read)
7552 .qs (bank1_info0_regwen_8_qs)
7553 );
7554
7555
7556 // Subregister 9 of Multireg bank1_info0_regwen
7557 // R[bank1_info0_regwen_9]: V(False)
7558 prim_subreg #(
7559 .DW (1),
7560 .SwAccess(prim_subreg_pkg::SwAccessW0C),
7561 .RESVAL (1'h1),
7562 .Mubi (1'b0)
7563 ) u_bank1_info0_regwen_9 (
7564 .clk_i (clk_i),
7565 .rst_ni (rst_ni),
7566
7567 // from register interface
7568 .we (bank1_info0_regwen_9_we),
7569 .wd (bank1_info0_regwen_9_wd),
7570
7571 // from internal hardware
7572 .de (1'b0),
7573 .d ('0),
7574
7575 // to internal hardware
7576 .qe (),
7577 .q (),
7578 .ds (),
7579
7580 // to register interface (read)
7581 .qs (bank1_info0_regwen_9_qs)
7582 );
7583
7584
7585 // Subregister 0 of Multireg bank1_info0_page_cfg
7586 // R[bank1_info0_page_cfg_0]: V(False)
7587 // Create REGWEN-gated WE signal
7588 logic bank1_info0_page_cfg_0_gated_we;
7589 1/1 assign bank1_info0_page_cfg_0_gated_we = bank1_info0_page_cfg_0_we & bank1_info0_regwen_0_qs;
Tests: T1 T2 T3
7590 // F[en_0]: 3:0
7591 prim_subreg #(
7592 .DW (4),
7593 .SwAccess(prim_subreg_pkg::SwAccessRW),
7594 .RESVAL (4'h9),
7595 .Mubi (1'b1)
7596 ) u_bank1_info0_page_cfg_0_en_0 (
7597 .clk_i (clk_i),
7598 .rst_ni (rst_ni),
7599
7600 // from register interface
7601 .we (bank1_info0_page_cfg_0_gated_we),
7602 .wd (bank1_info0_page_cfg_0_en_0_wd),
7603
7604 // from internal hardware
7605 .de (1'b0),
7606 .d ('0),
7607
7608 // to internal hardware
7609 .qe (),
7610 .q (reg2hw.bank1_info0_page_cfg[0].en.q),
7611 .ds (),
7612
7613 // to register interface (read)
7614 .qs (bank1_info0_page_cfg_0_en_0_qs)
7615 );
7616
7617 // F[rd_en_0]: 7:4
7618 prim_subreg #(
7619 .DW (4),
7620 .SwAccess(prim_subreg_pkg::SwAccessRW),
7621 .RESVAL (4'h9),
7622 .Mubi (1'b1)
7623 ) u_bank1_info0_page_cfg_0_rd_en_0 (
7624 .clk_i (clk_i),
7625 .rst_ni (rst_ni),
7626
7627 // from register interface
7628 .we (bank1_info0_page_cfg_0_gated_we),
7629 .wd (bank1_info0_page_cfg_0_rd_en_0_wd),
7630
7631 // from internal hardware
7632 .de (1'b0),
7633 .d ('0),
7634
7635 // to internal hardware
7636 .qe (),
7637 .q (reg2hw.bank1_info0_page_cfg[0].rd_en.q),
7638 .ds (),
7639
7640 // to register interface (read)
7641 .qs (bank1_info0_page_cfg_0_rd_en_0_qs)
7642 );
7643
7644 // F[prog_en_0]: 11:8
7645 prim_subreg #(
7646 .DW (4),
7647 .SwAccess(prim_subreg_pkg::SwAccessRW),
7648 .RESVAL (4'h9),
7649 .Mubi (1'b1)
7650 ) u_bank1_info0_page_cfg_0_prog_en_0 (
7651 .clk_i (clk_i),
7652 .rst_ni (rst_ni),
7653
7654 // from register interface
7655 .we (bank1_info0_page_cfg_0_gated_we),
7656 .wd (bank1_info0_page_cfg_0_prog_en_0_wd),
7657
7658 // from internal hardware
7659 .de (1'b0),
7660 .d ('0),
7661
7662 // to internal hardware
7663 .qe (),
7664 .q (reg2hw.bank1_info0_page_cfg[0].prog_en.q),
7665 .ds (),
7666
7667 // to register interface (read)
7668 .qs (bank1_info0_page_cfg_0_prog_en_0_qs)
7669 );
7670
7671 // F[erase_en_0]: 15:12
7672 prim_subreg #(
7673 .DW (4),
7674 .SwAccess(prim_subreg_pkg::SwAccessRW),
7675 .RESVAL (4'h9),
7676 .Mubi (1'b1)
7677 ) u_bank1_info0_page_cfg_0_erase_en_0 (
7678 .clk_i (clk_i),
7679 .rst_ni (rst_ni),
7680
7681 // from register interface
7682 .we (bank1_info0_page_cfg_0_gated_we),
7683 .wd (bank1_info0_page_cfg_0_erase_en_0_wd),
7684
7685 // from internal hardware
7686 .de (1'b0),
7687 .d ('0),
7688
7689 // to internal hardware
7690 .qe (),
7691 .q (reg2hw.bank1_info0_page_cfg[0].erase_en.q),
7692 .ds (),
7693
7694 // to register interface (read)
7695 .qs (bank1_info0_page_cfg_0_erase_en_0_qs)
7696 );
7697
7698 // F[scramble_en_0]: 19:16
7699 prim_subreg #(
7700 .DW (4),
7701 .SwAccess(prim_subreg_pkg::SwAccessRW),
7702 .RESVAL (4'h9),
7703 .Mubi (1'b1)
7704 ) u_bank1_info0_page_cfg_0_scramble_en_0 (
7705 .clk_i (clk_i),
7706 .rst_ni (rst_ni),
7707
7708 // from register interface
7709 .we (bank1_info0_page_cfg_0_gated_we),
7710 .wd (bank1_info0_page_cfg_0_scramble_en_0_wd),
7711
7712 // from internal hardware
7713 .de (1'b0),
7714 .d ('0),
7715
7716 // to internal hardware
7717 .qe (),
7718 .q (reg2hw.bank1_info0_page_cfg[0].scramble_en.q),
7719 .ds (),
7720
7721 // to register interface (read)
7722 .qs (bank1_info0_page_cfg_0_scramble_en_0_qs)
7723 );
7724
7725 // F[ecc_en_0]: 23:20
7726 prim_subreg #(
7727 .DW (4),
7728 .SwAccess(prim_subreg_pkg::SwAccessRW),
7729 .RESVAL (4'h9),
7730 .Mubi (1'b1)
7731 ) u_bank1_info0_page_cfg_0_ecc_en_0 (
7732 .clk_i (clk_i),
7733 .rst_ni (rst_ni),
7734
7735 // from register interface
7736 .we (bank1_info0_page_cfg_0_gated_we),
7737 .wd (bank1_info0_page_cfg_0_ecc_en_0_wd),
7738
7739 // from internal hardware
7740 .de (1'b0),
7741 .d ('0),
7742
7743 // to internal hardware
7744 .qe (),
7745 .q (reg2hw.bank1_info0_page_cfg[0].ecc_en.q),
7746 .ds (),
7747
7748 // to register interface (read)
7749 .qs (bank1_info0_page_cfg_0_ecc_en_0_qs)
7750 );
7751
7752 // F[he_en_0]: 27:24
7753 prim_subreg #(
7754 .DW (4),
7755 .SwAccess(prim_subreg_pkg::SwAccessRW),
7756 .RESVAL (4'h9),
7757 .Mubi (1'b1)
7758 ) u_bank1_info0_page_cfg_0_he_en_0 (
7759 .clk_i (clk_i),
7760 .rst_ni (rst_ni),
7761
7762 // from register interface
7763 .we (bank1_info0_page_cfg_0_gated_we),
7764 .wd (bank1_info0_page_cfg_0_he_en_0_wd),
7765
7766 // from internal hardware
7767 .de (1'b0),
7768 .d ('0),
7769
7770 // to internal hardware
7771 .qe (),
7772 .q (reg2hw.bank1_info0_page_cfg[0].he_en.q),
7773 .ds (),
7774
7775 // to register interface (read)
7776 .qs (bank1_info0_page_cfg_0_he_en_0_qs)
7777 );
7778
7779
7780 // Subregister 1 of Multireg bank1_info0_page_cfg
7781 // R[bank1_info0_page_cfg_1]: V(False)
7782 // Create REGWEN-gated WE signal
7783 logic bank1_info0_page_cfg_1_gated_we;
7784 1/1 assign bank1_info0_page_cfg_1_gated_we = bank1_info0_page_cfg_1_we & bank1_info0_regwen_1_qs;
Tests: T1 T2 T3
7785 // F[en_1]: 3:0
7786 prim_subreg #(
7787 .DW (4),
7788 .SwAccess(prim_subreg_pkg::SwAccessRW),
7789 .RESVAL (4'h9),
7790 .Mubi (1'b1)
7791 ) u_bank1_info0_page_cfg_1_en_1 (
7792 .clk_i (clk_i),
7793 .rst_ni (rst_ni),
7794
7795 // from register interface
7796 .we (bank1_info0_page_cfg_1_gated_we),
7797 .wd (bank1_info0_page_cfg_1_en_1_wd),
7798
7799 // from internal hardware
7800 .de (1'b0),
7801 .d ('0),
7802
7803 // to internal hardware
7804 .qe (),
7805 .q (reg2hw.bank1_info0_page_cfg[1].en.q),
7806 .ds (),
7807
7808 // to register interface (read)
7809 .qs (bank1_info0_page_cfg_1_en_1_qs)
7810 );
7811
7812 // F[rd_en_1]: 7:4
7813 prim_subreg #(
7814 .DW (4),
7815 .SwAccess(prim_subreg_pkg::SwAccessRW),
7816 .RESVAL (4'h9),
7817 .Mubi (1'b1)
7818 ) u_bank1_info0_page_cfg_1_rd_en_1 (
7819 .clk_i (clk_i),
7820 .rst_ni (rst_ni),
7821
7822 // from register interface
7823 .we (bank1_info0_page_cfg_1_gated_we),
7824 .wd (bank1_info0_page_cfg_1_rd_en_1_wd),
7825
7826 // from internal hardware
7827 .de (1'b0),
7828 .d ('0),
7829
7830 // to internal hardware
7831 .qe (),
7832 .q (reg2hw.bank1_info0_page_cfg[1].rd_en.q),
7833 .ds (),
7834
7835 // to register interface (read)
7836 .qs (bank1_info0_page_cfg_1_rd_en_1_qs)
7837 );
7838
7839 // F[prog_en_1]: 11:8
7840 prim_subreg #(
7841 .DW (4),
7842 .SwAccess(prim_subreg_pkg::SwAccessRW),
7843 .RESVAL (4'h9),
7844 .Mubi (1'b1)
7845 ) u_bank1_info0_page_cfg_1_prog_en_1 (
7846 .clk_i (clk_i),
7847 .rst_ni (rst_ni),
7848
7849 // from register interface
7850 .we (bank1_info0_page_cfg_1_gated_we),
7851 .wd (bank1_info0_page_cfg_1_prog_en_1_wd),
7852
7853 // from internal hardware
7854 .de (1'b0),
7855 .d ('0),
7856
7857 // to internal hardware
7858 .qe (),
7859 .q (reg2hw.bank1_info0_page_cfg[1].prog_en.q),
7860 .ds (),
7861
7862 // to register interface (read)
7863 .qs (bank1_info0_page_cfg_1_prog_en_1_qs)
7864 );
7865
7866 // F[erase_en_1]: 15:12
7867 prim_subreg #(
7868 .DW (4),
7869 .SwAccess(prim_subreg_pkg::SwAccessRW),
7870 .RESVAL (4'h9),
7871 .Mubi (1'b1)
7872 ) u_bank1_info0_page_cfg_1_erase_en_1 (
7873 .clk_i (clk_i),
7874 .rst_ni (rst_ni),
7875
7876 // from register interface
7877 .we (bank1_info0_page_cfg_1_gated_we),
7878 .wd (bank1_info0_page_cfg_1_erase_en_1_wd),
7879
7880 // from internal hardware
7881 .de (1'b0),
7882 .d ('0),
7883
7884 // to internal hardware
7885 .qe (),
7886 .q (reg2hw.bank1_info0_page_cfg[1].erase_en.q),
7887 .ds (),
7888
7889 // to register interface (read)
7890 .qs (bank1_info0_page_cfg_1_erase_en_1_qs)
7891 );
7892
7893 // F[scramble_en_1]: 19:16
7894 prim_subreg #(
7895 .DW (4),
7896 .SwAccess(prim_subreg_pkg::SwAccessRW),
7897 .RESVAL (4'h9),
7898 .Mubi (1'b1)
7899 ) u_bank1_info0_page_cfg_1_scramble_en_1 (
7900 .clk_i (clk_i),
7901 .rst_ni (rst_ni),
7902
7903 // from register interface
7904 .we (bank1_info0_page_cfg_1_gated_we),
7905 .wd (bank1_info0_page_cfg_1_scramble_en_1_wd),
7906
7907 // from internal hardware
7908 .de (1'b0),
7909 .d ('0),
7910
7911 // to internal hardware
7912 .qe (),
7913 .q (reg2hw.bank1_info0_page_cfg[1].scramble_en.q),
7914 .ds (),
7915
7916 // to register interface (read)
7917 .qs (bank1_info0_page_cfg_1_scramble_en_1_qs)
7918 );
7919
7920 // F[ecc_en_1]: 23:20
7921 prim_subreg #(
7922 .DW (4),
7923 .SwAccess(prim_subreg_pkg::SwAccessRW),
7924 .RESVAL (4'h9),
7925 .Mubi (1'b1)
7926 ) u_bank1_info0_page_cfg_1_ecc_en_1 (
7927 .clk_i (clk_i),
7928 .rst_ni (rst_ni),
7929
7930 // from register interface
7931 .we (bank1_info0_page_cfg_1_gated_we),
7932 .wd (bank1_info0_page_cfg_1_ecc_en_1_wd),
7933
7934 // from internal hardware
7935 .de (1'b0),
7936 .d ('0),
7937
7938 // to internal hardware
7939 .qe (),
7940 .q (reg2hw.bank1_info0_page_cfg[1].ecc_en.q),
7941 .ds (),
7942
7943 // to register interface (read)
7944 .qs (bank1_info0_page_cfg_1_ecc_en_1_qs)
7945 );
7946
7947 // F[he_en_1]: 27:24
7948 prim_subreg #(
7949 .DW (4),
7950 .SwAccess(prim_subreg_pkg::SwAccessRW),
7951 .RESVAL (4'h9),
7952 .Mubi (1'b1)
7953 ) u_bank1_info0_page_cfg_1_he_en_1 (
7954 .clk_i (clk_i),
7955 .rst_ni (rst_ni),
7956
7957 // from register interface
7958 .we (bank1_info0_page_cfg_1_gated_we),
7959 .wd (bank1_info0_page_cfg_1_he_en_1_wd),
7960
7961 // from internal hardware
7962 .de (1'b0),
7963 .d ('0),
7964
7965 // to internal hardware
7966 .qe (),
7967 .q (reg2hw.bank1_info0_page_cfg[1].he_en.q),
7968 .ds (),
7969
7970 // to register interface (read)
7971 .qs (bank1_info0_page_cfg_1_he_en_1_qs)
7972 );
7973
7974
7975 // Subregister 2 of Multireg bank1_info0_page_cfg
7976 // R[bank1_info0_page_cfg_2]: V(False)
7977 // Create REGWEN-gated WE signal
7978 logic bank1_info0_page_cfg_2_gated_we;
7979 1/1 assign bank1_info0_page_cfg_2_gated_we = bank1_info0_page_cfg_2_we & bank1_info0_regwen_2_qs;
Tests: T1 T2 T3
7980 // F[en_2]: 3:0
7981 prim_subreg #(
7982 .DW (4),
7983 .SwAccess(prim_subreg_pkg::SwAccessRW),
7984 .RESVAL (4'h9),
7985 .Mubi (1'b1)
7986 ) u_bank1_info0_page_cfg_2_en_2 (
7987 .clk_i (clk_i),
7988 .rst_ni (rst_ni),
7989
7990 // from register interface
7991 .we (bank1_info0_page_cfg_2_gated_we),
7992 .wd (bank1_info0_page_cfg_2_en_2_wd),
7993
7994 // from internal hardware
7995 .de (1'b0),
7996 .d ('0),
7997
7998 // to internal hardware
7999 .qe (),
8000 .q (reg2hw.bank1_info0_page_cfg[2].en.q),
8001 .ds (),
8002
8003 // to register interface (read)
8004 .qs (bank1_info0_page_cfg_2_en_2_qs)
8005 );
8006
8007 // F[rd_en_2]: 7:4
8008 prim_subreg #(
8009 .DW (4),
8010 .SwAccess(prim_subreg_pkg::SwAccessRW),
8011 .RESVAL (4'h9),
8012 .Mubi (1'b1)
8013 ) u_bank1_info0_page_cfg_2_rd_en_2 (
8014 .clk_i (clk_i),
8015 .rst_ni (rst_ni),
8016
8017 // from register interface
8018 .we (bank1_info0_page_cfg_2_gated_we),
8019 .wd (bank1_info0_page_cfg_2_rd_en_2_wd),
8020
8021 // from internal hardware
8022 .de (1'b0),
8023 .d ('0),
8024
8025 // to internal hardware
8026 .qe (),
8027 .q (reg2hw.bank1_info0_page_cfg[2].rd_en.q),
8028 .ds (),
8029
8030 // to register interface (read)
8031 .qs (bank1_info0_page_cfg_2_rd_en_2_qs)
8032 );
8033
8034 // F[prog_en_2]: 11:8
8035 prim_subreg #(
8036 .DW (4),
8037 .SwAccess(prim_subreg_pkg::SwAccessRW),
8038 .RESVAL (4'h9),
8039 .Mubi (1'b1)
8040 ) u_bank1_info0_page_cfg_2_prog_en_2 (
8041 .clk_i (clk_i),
8042 .rst_ni (rst_ni),
8043
8044 // from register interface
8045 .we (bank1_info0_page_cfg_2_gated_we),
8046 .wd (bank1_info0_page_cfg_2_prog_en_2_wd),
8047
8048 // from internal hardware
8049 .de (1'b0),
8050 .d ('0),
8051
8052 // to internal hardware
8053 .qe (),
8054 .q (reg2hw.bank1_info0_page_cfg[2].prog_en.q),
8055 .ds (),
8056
8057 // to register interface (read)
8058 .qs (bank1_info0_page_cfg_2_prog_en_2_qs)
8059 );
8060
8061 // F[erase_en_2]: 15:12
8062 prim_subreg #(
8063 .DW (4),
8064 .SwAccess(prim_subreg_pkg::SwAccessRW),
8065 .RESVAL (4'h9),
8066 .Mubi (1'b1)
8067 ) u_bank1_info0_page_cfg_2_erase_en_2 (
8068 .clk_i (clk_i),
8069 .rst_ni (rst_ni),
8070
8071 // from register interface
8072 .we (bank1_info0_page_cfg_2_gated_we),
8073 .wd (bank1_info0_page_cfg_2_erase_en_2_wd),
8074
8075 // from internal hardware
8076 .de (1'b0),
8077 .d ('0),
8078
8079 // to internal hardware
8080 .qe (),
8081 .q (reg2hw.bank1_info0_page_cfg[2].erase_en.q),
8082 .ds (),
8083
8084 // to register interface (read)
8085 .qs (bank1_info0_page_cfg_2_erase_en_2_qs)
8086 );
8087
8088 // F[scramble_en_2]: 19:16
8089 prim_subreg #(
8090 .DW (4),
8091 .SwAccess(prim_subreg_pkg::SwAccessRW),
8092 .RESVAL (4'h9),
8093 .Mubi (1'b1)
8094 ) u_bank1_info0_page_cfg_2_scramble_en_2 (
8095 .clk_i (clk_i),
8096 .rst_ni (rst_ni),
8097
8098 // from register interface
8099 .we (bank1_info0_page_cfg_2_gated_we),
8100 .wd (bank1_info0_page_cfg_2_scramble_en_2_wd),
8101
8102 // from internal hardware
8103 .de (1'b0),
8104 .d ('0),
8105
8106 // to internal hardware
8107 .qe (),
8108 .q (reg2hw.bank1_info0_page_cfg[2].scramble_en.q),
8109 .ds (),
8110
8111 // to register interface (read)
8112 .qs (bank1_info0_page_cfg_2_scramble_en_2_qs)
8113 );
8114
8115 // F[ecc_en_2]: 23:20
8116 prim_subreg #(
8117 .DW (4),
8118 .SwAccess(prim_subreg_pkg::SwAccessRW),
8119 .RESVAL (4'h9),
8120 .Mubi (1'b1)
8121 ) u_bank1_info0_page_cfg_2_ecc_en_2 (
8122 .clk_i (clk_i),
8123 .rst_ni (rst_ni),
8124
8125 // from register interface
8126 .we (bank1_info0_page_cfg_2_gated_we),
8127 .wd (bank1_info0_page_cfg_2_ecc_en_2_wd),
8128
8129 // from internal hardware
8130 .de (1'b0),
8131 .d ('0),
8132
8133 // to internal hardware
8134 .qe (),
8135 .q (reg2hw.bank1_info0_page_cfg[2].ecc_en.q),
8136 .ds (),
8137
8138 // to register interface (read)
8139 .qs (bank1_info0_page_cfg_2_ecc_en_2_qs)
8140 );
8141
8142 // F[he_en_2]: 27:24
8143 prim_subreg #(
8144 .DW (4),
8145 .SwAccess(prim_subreg_pkg::SwAccessRW),
8146 .RESVAL (4'h9),
8147 .Mubi (1'b1)
8148 ) u_bank1_info0_page_cfg_2_he_en_2 (
8149 .clk_i (clk_i),
8150 .rst_ni (rst_ni),
8151
8152 // from register interface
8153 .we (bank1_info0_page_cfg_2_gated_we),
8154 .wd (bank1_info0_page_cfg_2_he_en_2_wd),
8155
8156 // from internal hardware
8157 .de (1'b0),
8158 .d ('0),
8159
8160 // to internal hardware
8161 .qe (),
8162 .q (reg2hw.bank1_info0_page_cfg[2].he_en.q),
8163 .ds (),
8164
8165 // to register interface (read)
8166 .qs (bank1_info0_page_cfg_2_he_en_2_qs)
8167 );
8168
8169
8170 // Subregister 3 of Multireg bank1_info0_page_cfg
8171 // R[bank1_info0_page_cfg_3]: V(False)
8172 // Create REGWEN-gated WE signal
8173 logic bank1_info0_page_cfg_3_gated_we;
8174 1/1 assign bank1_info0_page_cfg_3_gated_we = bank1_info0_page_cfg_3_we & bank1_info0_regwen_3_qs;
Tests: T1 T2 T3
8175 // F[en_3]: 3:0
8176 prim_subreg #(
8177 .DW (4),
8178 .SwAccess(prim_subreg_pkg::SwAccessRW),
8179 .RESVAL (4'h9),
8180 .Mubi (1'b1)
8181 ) u_bank1_info0_page_cfg_3_en_3 (
8182 .clk_i (clk_i),
8183 .rst_ni (rst_ni),
8184
8185 // from register interface
8186 .we (bank1_info0_page_cfg_3_gated_we),
8187 .wd (bank1_info0_page_cfg_3_en_3_wd),
8188
8189 // from internal hardware
8190 .de (1'b0),
8191 .d ('0),
8192
8193 // to internal hardware
8194 .qe (),
8195 .q (reg2hw.bank1_info0_page_cfg[3].en.q),
8196 .ds (),
8197
8198 // to register interface (read)
8199 .qs (bank1_info0_page_cfg_3_en_3_qs)
8200 );
8201
8202 // F[rd_en_3]: 7:4
8203 prim_subreg #(
8204 .DW (4),
8205 .SwAccess(prim_subreg_pkg::SwAccessRW),
8206 .RESVAL (4'h9),
8207 .Mubi (1'b1)
8208 ) u_bank1_info0_page_cfg_3_rd_en_3 (
8209 .clk_i (clk_i),
8210 .rst_ni (rst_ni),
8211
8212 // from register interface
8213 .we (bank1_info0_page_cfg_3_gated_we),
8214 .wd (bank1_info0_page_cfg_3_rd_en_3_wd),
8215
8216 // from internal hardware
8217 .de (1'b0),
8218 .d ('0),
8219
8220 // to internal hardware
8221 .qe (),
8222 .q (reg2hw.bank1_info0_page_cfg[3].rd_en.q),
8223 .ds (),
8224
8225 // to register interface (read)
8226 .qs (bank1_info0_page_cfg_3_rd_en_3_qs)
8227 );
8228
8229 // F[prog_en_3]: 11:8
8230 prim_subreg #(
8231 .DW (4),
8232 .SwAccess(prim_subreg_pkg::SwAccessRW),
8233 .RESVAL (4'h9),
8234 .Mubi (1'b1)
8235 ) u_bank1_info0_page_cfg_3_prog_en_3 (
8236 .clk_i (clk_i),
8237 .rst_ni (rst_ni),
8238
8239 // from register interface
8240 .we (bank1_info0_page_cfg_3_gated_we),
8241 .wd (bank1_info0_page_cfg_3_prog_en_3_wd),
8242
8243 // from internal hardware
8244 .de (1'b0),
8245 .d ('0),
8246
8247 // to internal hardware
8248 .qe (),
8249 .q (reg2hw.bank1_info0_page_cfg[3].prog_en.q),
8250 .ds (),
8251
8252 // to register interface (read)
8253 .qs (bank1_info0_page_cfg_3_prog_en_3_qs)
8254 );
8255
8256 // F[erase_en_3]: 15:12
8257 prim_subreg #(
8258 .DW (4),
8259 .SwAccess(prim_subreg_pkg::SwAccessRW),
8260 .RESVAL (4'h9),
8261 .Mubi (1'b1)
8262 ) u_bank1_info0_page_cfg_3_erase_en_3 (
8263 .clk_i (clk_i),
8264 .rst_ni (rst_ni),
8265
8266 // from register interface
8267 .we (bank1_info0_page_cfg_3_gated_we),
8268 .wd (bank1_info0_page_cfg_3_erase_en_3_wd),
8269
8270 // from internal hardware
8271 .de (1'b0),
8272 .d ('0),
8273
8274 // to internal hardware
8275 .qe (),
8276 .q (reg2hw.bank1_info0_page_cfg[3].erase_en.q),
8277 .ds (),
8278
8279 // to register interface (read)
8280 .qs (bank1_info0_page_cfg_3_erase_en_3_qs)
8281 );
8282
8283 // F[scramble_en_3]: 19:16
8284 prim_subreg #(
8285 .DW (4),
8286 .SwAccess(prim_subreg_pkg::SwAccessRW),
8287 .RESVAL (4'h9),
8288 .Mubi (1'b1)
8289 ) u_bank1_info0_page_cfg_3_scramble_en_3 (
8290 .clk_i (clk_i),
8291 .rst_ni (rst_ni),
8292
8293 // from register interface
8294 .we (bank1_info0_page_cfg_3_gated_we),
8295 .wd (bank1_info0_page_cfg_3_scramble_en_3_wd),
8296
8297 // from internal hardware
8298 .de (1'b0),
8299 .d ('0),
8300
8301 // to internal hardware
8302 .qe (),
8303 .q (reg2hw.bank1_info0_page_cfg[3].scramble_en.q),
8304 .ds (),
8305
8306 // to register interface (read)
8307 .qs (bank1_info0_page_cfg_3_scramble_en_3_qs)
8308 );
8309
8310 // F[ecc_en_3]: 23:20
8311 prim_subreg #(
8312 .DW (4),
8313 .SwAccess(prim_subreg_pkg::SwAccessRW),
8314 .RESVAL (4'h9),
8315 .Mubi (1'b1)
8316 ) u_bank1_info0_page_cfg_3_ecc_en_3 (
8317 .clk_i (clk_i),
8318 .rst_ni (rst_ni),
8319
8320 // from register interface
8321 .we (bank1_info0_page_cfg_3_gated_we),
8322 .wd (bank1_info0_page_cfg_3_ecc_en_3_wd),
8323
8324 // from internal hardware
8325 .de (1'b0),
8326 .d ('0),
8327
8328 // to internal hardware
8329 .qe (),
8330 .q (reg2hw.bank1_info0_page_cfg[3].ecc_en.q),
8331 .ds (),
8332
8333 // to register interface (read)
8334 .qs (bank1_info0_page_cfg_3_ecc_en_3_qs)
8335 );
8336
8337 // F[he_en_3]: 27:24
8338 prim_subreg #(
8339 .DW (4),
8340 .SwAccess(prim_subreg_pkg::SwAccessRW),
8341 .RESVAL (4'h9),
8342 .Mubi (1'b1)
8343 ) u_bank1_info0_page_cfg_3_he_en_3 (
8344 .clk_i (clk_i),
8345 .rst_ni (rst_ni),
8346
8347 // from register interface
8348 .we (bank1_info0_page_cfg_3_gated_we),
8349 .wd (bank1_info0_page_cfg_3_he_en_3_wd),
8350
8351 // from internal hardware
8352 .de (1'b0),
8353 .d ('0),
8354
8355 // to internal hardware
8356 .qe (),
8357 .q (reg2hw.bank1_info0_page_cfg[3].he_en.q),
8358 .ds (),
8359
8360 // to register interface (read)
8361 .qs (bank1_info0_page_cfg_3_he_en_3_qs)
8362 );
8363
8364
8365 // Subregister 4 of Multireg bank1_info0_page_cfg
8366 // R[bank1_info0_page_cfg_4]: V(False)
8367 // Create REGWEN-gated WE signal
8368 logic bank1_info0_page_cfg_4_gated_we;
8369 1/1 assign bank1_info0_page_cfg_4_gated_we = bank1_info0_page_cfg_4_we & bank1_info0_regwen_4_qs;
Tests: T1 T2 T3
8370 // F[en_4]: 3:0
8371 prim_subreg #(
8372 .DW (4),
8373 .SwAccess(prim_subreg_pkg::SwAccessRW),
8374 .RESVAL (4'h9),
8375 .Mubi (1'b1)
8376 ) u_bank1_info0_page_cfg_4_en_4 (
8377 .clk_i (clk_i),
8378 .rst_ni (rst_ni),
8379
8380 // from register interface
8381 .we (bank1_info0_page_cfg_4_gated_we),
8382 .wd (bank1_info0_page_cfg_4_en_4_wd),
8383
8384 // from internal hardware
8385 .de (1'b0),
8386 .d ('0),
8387
8388 // to internal hardware
8389 .qe (),
8390 .q (reg2hw.bank1_info0_page_cfg[4].en.q),
8391 .ds (),
8392
8393 // to register interface (read)
8394 .qs (bank1_info0_page_cfg_4_en_4_qs)
8395 );
8396
8397 // F[rd_en_4]: 7:4
8398 prim_subreg #(
8399 .DW (4),
8400 .SwAccess(prim_subreg_pkg::SwAccessRW),
8401 .RESVAL (4'h9),
8402 .Mubi (1'b1)
8403 ) u_bank1_info0_page_cfg_4_rd_en_4 (
8404 .clk_i (clk_i),
8405 .rst_ni (rst_ni),
8406
8407 // from register interface
8408 .we (bank1_info0_page_cfg_4_gated_we),
8409 .wd (bank1_info0_page_cfg_4_rd_en_4_wd),
8410
8411 // from internal hardware
8412 .de (1'b0),
8413 .d ('0),
8414
8415 // to internal hardware
8416 .qe (),
8417 .q (reg2hw.bank1_info0_page_cfg[4].rd_en.q),
8418 .ds (),
8419
8420 // to register interface (read)
8421 .qs (bank1_info0_page_cfg_4_rd_en_4_qs)
8422 );
8423
8424 // F[prog_en_4]: 11:8
8425 prim_subreg #(
8426 .DW (4),
8427 .SwAccess(prim_subreg_pkg::SwAccessRW),
8428 .RESVAL (4'h9),
8429 .Mubi (1'b1)
8430 ) u_bank1_info0_page_cfg_4_prog_en_4 (
8431 .clk_i (clk_i),
8432 .rst_ni (rst_ni),
8433
8434 // from register interface
8435 .we (bank1_info0_page_cfg_4_gated_we),
8436 .wd (bank1_info0_page_cfg_4_prog_en_4_wd),
8437
8438 // from internal hardware
8439 .de (1'b0),
8440 .d ('0),
8441
8442 // to internal hardware
8443 .qe (),
8444 .q (reg2hw.bank1_info0_page_cfg[4].prog_en.q),
8445 .ds (),
8446
8447 // to register interface (read)
8448 .qs (bank1_info0_page_cfg_4_prog_en_4_qs)
8449 );
8450
8451 // F[erase_en_4]: 15:12
8452 prim_subreg #(
8453 .DW (4),
8454 .SwAccess(prim_subreg_pkg::SwAccessRW),
8455 .RESVAL (4'h9),
8456 .Mubi (1'b1)
8457 ) u_bank1_info0_page_cfg_4_erase_en_4 (
8458 .clk_i (clk_i),
8459 .rst_ni (rst_ni),
8460
8461 // from register interface
8462 .we (bank1_info0_page_cfg_4_gated_we),
8463 .wd (bank1_info0_page_cfg_4_erase_en_4_wd),
8464
8465 // from internal hardware
8466 .de (1'b0),
8467 .d ('0),
8468
8469 // to internal hardware
8470 .qe (),
8471 .q (reg2hw.bank1_info0_page_cfg[4].erase_en.q),
8472 .ds (),
8473
8474 // to register interface (read)
8475 .qs (bank1_info0_page_cfg_4_erase_en_4_qs)
8476 );
8477
8478 // F[scramble_en_4]: 19:16
8479 prim_subreg #(
8480 .DW (4),
8481 .SwAccess(prim_subreg_pkg::SwAccessRW),
8482 .RESVAL (4'h9),
8483 .Mubi (1'b1)
8484 ) u_bank1_info0_page_cfg_4_scramble_en_4 (
8485 .clk_i (clk_i),
8486 .rst_ni (rst_ni),
8487
8488 // from register interface
8489 .we (bank1_info0_page_cfg_4_gated_we),
8490 .wd (bank1_info0_page_cfg_4_scramble_en_4_wd),
8491
8492 // from internal hardware
8493 .de (1'b0),
8494 .d ('0),
8495
8496 // to internal hardware
8497 .qe (),
8498 .q (reg2hw.bank1_info0_page_cfg[4].scramble_en.q),
8499 .ds (),
8500
8501 // to register interface (read)
8502 .qs (bank1_info0_page_cfg_4_scramble_en_4_qs)
8503 );
8504
8505 // F[ecc_en_4]: 23:20
8506 prim_subreg #(
8507 .DW (4),
8508 .SwAccess(prim_subreg_pkg::SwAccessRW),
8509 .RESVAL (4'h9),
8510 .Mubi (1'b1)
8511 ) u_bank1_info0_page_cfg_4_ecc_en_4 (
8512 .clk_i (clk_i),
8513 .rst_ni (rst_ni),
8514
8515 // from register interface
8516 .we (bank1_info0_page_cfg_4_gated_we),
8517 .wd (bank1_info0_page_cfg_4_ecc_en_4_wd),
8518
8519 // from internal hardware
8520 .de (1'b0),
8521 .d ('0),
8522
8523 // to internal hardware
8524 .qe (),
8525 .q (reg2hw.bank1_info0_page_cfg[4].ecc_en.q),
8526 .ds (),
8527
8528 // to register interface (read)
8529 .qs (bank1_info0_page_cfg_4_ecc_en_4_qs)
8530 );
8531
8532 // F[he_en_4]: 27:24
8533 prim_subreg #(
8534 .DW (4),
8535 .SwAccess(prim_subreg_pkg::SwAccessRW),
8536 .RESVAL (4'h9),
8537 .Mubi (1'b1)
8538 ) u_bank1_info0_page_cfg_4_he_en_4 (
8539 .clk_i (clk_i),
8540 .rst_ni (rst_ni),
8541
8542 // from register interface
8543 .we (bank1_info0_page_cfg_4_gated_we),
8544 .wd (bank1_info0_page_cfg_4_he_en_4_wd),
8545
8546 // from internal hardware
8547 .de (1'b0),
8548 .d ('0),
8549
8550 // to internal hardware
8551 .qe (),
8552 .q (reg2hw.bank1_info0_page_cfg[4].he_en.q),
8553 .ds (),
8554
8555 // to register interface (read)
8556 .qs (bank1_info0_page_cfg_4_he_en_4_qs)
8557 );
8558
8559
8560 // Subregister 5 of Multireg bank1_info0_page_cfg
8561 // R[bank1_info0_page_cfg_5]: V(False)
8562 // Create REGWEN-gated WE signal
8563 logic bank1_info0_page_cfg_5_gated_we;
8564 1/1 assign bank1_info0_page_cfg_5_gated_we = bank1_info0_page_cfg_5_we & bank1_info0_regwen_5_qs;
Tests: T1 T2 T3
8565 // F[en_5]: 3:0
8566 prim_subreg #(
8567 .DW (4),
8568 .SwAccess(prim_subreg_pkg::SwAccessRW),
8569 .RESVAL (4'h9),
8570 .Mubi (1'b1)
8571 ) u_bank1_info0_page_cfg_5_en_5 (
8572 .clk_i (clk_i),
8573 .rst_ni (rst_ni),
8574
8575 // from register interface
8576 .we (bank1_info0_page_cfg_5_gated_we),
8577 .wd (bank1_info0_page_cfg_5_en_5_wd),
8578
8579 // from internal hardware
8580 .de (1'b0),
8581 .d ('0),
8582
8583 // to internal hardware
8584 .qe (),
8585 .q (reg2hw.bank1_info0_page_cfg[5].en.q),
8586 .ds (),
8587
8588 // to register interface (read)
8589 .qs (bank1_info0_page_cfg_5_en_5_qs)
8590 );
8591
8592 // F[rd_en_5]: 7:4
8593 prim_subreg #(
8594 .DW (4),
8595 .SwAccess(prim_subreg_pkg::SwAccessRW),
8596 .RESVAL (4'h9),
8597 .Mubi (1'b1)
8598 ) u_bank1_info0_page_cfg_5_rd_en_5 (
8599 .clk_i (clk_i),
8600 .rst_ni (rst_ni),
8601
8602 // from register interface
8603 .we (bank1_info0_page_cfg_5_gated_we),
8604 .wd (bank1_info0_page_cfg_5_rd_en_5_wd),
8605
8606 // from internal hardware
8607 .de (1'b0),
8608 .d ('0),
8609
8610 // to internal hardware
8611 .qe (),
8612 .q (reg2hw.bank1_info0_page_cfg[5].rd_en.q),
8613 .ds (),
8614
8615 // to register interface (read)
8616 .qs (bank1_info0_page_cfg_5_rd_en_5_qs)
8617 );
8618
8619 // F[prog_en_5]: 11:8
8620 prim_subreg #(
8621 .DW (4),
8622 .SwAccess(prim_subreg_pkg::SwAccessRW),
8623 .RESVAL (4'h9),
8624 .Mubi (1'b1)
8625 ) u_bank1_info0_page_cfg_5_prog_en_5 (
8626 .clk_i (clk_i),
8627 .rst_ni (rst_ni),
8628
8629 // from register interface
8630 .we (bank1_info0_page_cfg_5_gated_we),
8631 .wd (bank1_info0_page_cfg_5_prog_en_5_wd),
8632
8633 // from internal hardware
8634 .de (1'b0),
8635 .d ('0),
8636
8637 // to internal hardware
8638 .qe (),
8639 .q (reg2hw.bank1_info0_page_cfg[5].prog_en.q),
8640 .ds (),
8641
8642 // to register interface (read)
8643 .qs (bank1_info0_page_cfg_5_prog_en_5_qs)
8644 );
8645
8646 // F[erase_en_5]: 15:12
8647 prim_subreg #(
8648 .DW (4),
8649 .SwAccess(prim_subreg_pkg::SwAccessRW),
8650 .RESVAL (4'h9),
8651 .Mubi (1'b1)
8652 ) u_bank1_info0_page_cfg_5_erase_en_5 (
8653 .clk_i (clk_i),
8654 .rst_ni (rst_ni),
8655
8656 // from register interface
8657 .we (bank1_info0_page_cfg_5_gated_we),
8658 .wd (bank1_info0_page_cfg_5_erase_en_5_wd),
8659
8660 // from internal hardware
8661 .de (1'b0),
8662 .d ('0),
8663
8664 // to internal hardware
8665 .qe (),
8666 .q (reg2hw.bank1_info0_page_cfg[5].erase_en.q),
8667 .ds (),
8668
8669 // to register interface (read)
8670 .qs (bank1_info0_page_cfg_5_erase_en_5_qs)
8671 );
8672
8673 // F[scramble_en_5]: 19:16
8674 prim_subreg #(
8675 .DW (4),
8676 .SwAccess(prim_subreg_pkg::SwAccessRW),
8677 .RESVAL (4'h9),
8678 .Mubi (1'b1)
8679 ) u_bank1_info0_page_cfg_5_scramble_en_5 (
8680 .clk_i (clk_i),
8681 .rst_ni (rst_ni),
8682
8683 // from register interface
8684 .we (bank1_info0_page_cfg_5_gated_we),
8685 .wd (bank1_info0_page_cfg_5_scramble_en_5_wd),
8686
8687 // from internal hardware
8688 .de (1'b0),
8689 .d ('0),
8690
8691 // to internal hardware
8692 .qe (),
8693 .q (reg2hw.bank1_info0_page_cfg[5].scramble_en.q),
8694 .ds (),
8695
8696 // to register interface (read)
8697 .qs (bank1_info0_page_cfg_5_scramble_en_5_qs)
8698 );
8699
8700 // F[ecc_en_5]: 23:20
8701 prim_subreg #(
8702 .DW (4),
8703 .SwAccess(prim_subreg_pkg::SwAccessRW),
8704 .RESVAL (4'h9),
8705 .Mubi (1'b1)
8706 ) u_bank1_info0_page_cfg_5_ecc_en_5 (
8707 .clk_i (clk_i),
8708 .rst_ni (rst_ni),
8709
8710 // from register interface
8711 .we (bank1_info0_page_cfg_5_gated_we),
8712 .wd (bank1_info0_page_cfg_5_ecc_en_5_wd),
8713
8714 // from internal hardware
8715 .de (1'b0),
8716 .d ('0),
8717
8718 // to internal hardware
8719 .qe (),
8720 .q (reg2hw.bank1_info0_page_cfg[5].ecc_en.q),
8721 .ds (),
8722
8723 // to register interface (read)
8724 .qs (bank1_info0_page_cfg_5_ecc_en_5_qs)
8725 );
8726
8727 // F[he_en_5]: 27:24
8728 prim_subreg #(
8729 .DW (4),
8730 .SwAccess(prim_subreg_pkg::SwAccessRW),
8731 .RESVAL (4'h9),
8732 .Mubi (1'b1)
8733 ) u_bank1_info0_page_cfg_5_he_en_5 (
8734 .clk_i (clk_i),
8735 .rst_ni (rst_ni),
8736
8737 // from register interface
8738 .we (bank1_info0_page_cfg_5_gated_we),
8739 .wd (bank1_info0_page_cfg_5_he_en_5_wd),
8740
8741 // from internal hardware
8742 .de (1'b0),
8743 .d ('0),
8744
8745 // to internal hardware
8746 .qe (),
8747 .q (reg2hw.bank1_info0_page_cfg[5].he_en.q),
8748 .ds (),
8749
8750 // to register interface (read)
8751 .qs (bank1_info0_page_cfg_5_he_en_5_qs)
8752 );
8753
8754
8755 // Subregister 6 of Multireg bank1_info0_page_cfg
8756 // R[bank1_info0_page_cfg_6]: V(False)
8757 // Create REGWEN-gated WE signal
8758 logic bank1_info0_page_cfg_6_gated_we;
8759 1/1 assign bank1_info0_page_cfg_6_gated_we = bank1_info0_page_cfg_6_we & bank1_info0_regwen_6_qs;
Tests: T1 T2 T3
8760 // F[en_6]: 3:0
8761 prim_subreg #(
8762 .DW (4),
8763 .SwAccess(prim_subreg_pkg::SwAccessRW),
8764 .RESVAL (4'h9),
8765 .Mubi (1'b1)
8766 ) u_bank1_info0_page_cfg_6_en_6 (
8767 .clk_i (clk_i),
8768 .rst_ni (rst_ni),
8769
8770 // from register interface
8771 .we (bank1_info0_page_cfg_6_gated_we),
8772 .wd (bank1_info0_page_cfg_6_en_6_wd),
8773
8774 // from internal hardware
8775 .de (1'b0),
8776 .d ('0),
8777
8778 // to internal hardware
8779 .qe (),
8780 .q (reg2hw.bank1_info0_page_cfg[6].en.q),
8781 .ds (),
8782
8783 // to register interface (read)
8784 .qs (bank1_info0_page_cfg_6_en_6_qs)
8785 );
8786
8787 // F[rd_en_6]: 7:4
8788 prim_subreg #(
8789 .DW (4),
8790 .SwAccess(prim_subreg_pkg::SwAccessRW),
8791 .RESVAL (4'h9),
8792 .Mubi (1'b1)
8793 ) u_bank1_info0_page_cfg_6_rd_en_6 (
8794 .clk_i (clk_i),
8795 .rst_ni (rst_ni),
8796
8797 // from register interface
8798 .we (bank1_info0_page_cfg_6_gated_we),
8799 .wd (bank1_info0_page_cfg_6_rd_en_6_wd),
8800
8801 // from internal hardware
8802 .de (1'b0),
8803 .d ('0),
8804
8805 // to internal hardware
8806 .qe (),
8807 .q (reg2hw.bank1_info0_page_cfg[6].rd_en.q),
8808 .ds (),
8809
8810 // to register interface (read)
8811 .qs (bank1_info0_page_cfg_6_rd_en_6_qs)
8812 );
8813
8814 // F[prog_en_6]: 11:8
8815 prim_subreg #(
8816 .DW (4),
8817 .SwAccess(prim_subreg_pkg::SwAccessRW),
8818 .RESVAL (4'h9),
8819 .Mubi (1'b1)
8820 ) u_bank1_info0_page_cfg_6_prog_en_6 (
8821 .clk_i (clk_i),
8822 .rst_ni (rst_ni),
8823
8824 // from register interface
8825 .we (bank1_info0_page_cfg_6_gated_we),
8826 .wd (bank1_info0_page_cfg_6_prog_en_6_wd),
8827
8828 // from internal hardware
8829 .de (1'b0),
8830 .d ('0),
8831
8832 // to internal hardware
8833 .qe (),
8834 .q (reg2hw.bank1_info0_page_cfg[6].prog_en.q),
8835 .ds (),
8836
8837 // to register interface (read)
8838 .qs (bank1_info0_page_cfg_6_prog_en_6_qs)
8839 );
8840
8841 // F[erase_en_6]: 15:12
8842 prim_subreg #(
8843 .DW (4),
8844 .SwAccess(prim_subreg_pkg::SwAccessRW),
8845 .RESVAL (4'h9),
8846 .Mubi (1'b1)
8847 ) u_bank1_info0_page_cfg_6_erase_en_6 (
8848 .clk_i (clk_i),
8849 .rst_ni (rst_ni),
8850
8851 // from register interface
8852 .we (bank1_info0_page_cfg_6_gated_we),
8853 .wd (bank1_info0_page_cfg_6_erase_en_6_wd),
8854
8855 // from internal hardware
8856 .de (1'b0),
8857 .d ('0),
8858
8859 // to internal hardware
8860 .qe (),
8861 .q (reg2hw.bank1_info0_page_cfg[6].erase_en.q),
8862 .ds (),
8863
8864 // to register interface (read)
8865 .qs (bank1_info0_page_cfg_6_erase_en_6_qs)
8866 );
8867
8868 // F[scramble_en_6]: 19:16
8869 prim_subreg #(
8870 .DW (4),
8871 .SwAccess(prim_subreg_pkg::SwAccessRW),
8872 .RESVAL (4'h9),
8873 .Mubi (1'b1)
8874 ) u_bank1_info0_page_cfg_6_scramble_en_6 (
8875 .clk_i (clk_i),
8876 .rst_ni (rst_ni),
8877
8878 // from register interface
8879 .we (bank1_info0_page_cfg_6_gated_we),
8880 .wd (bank1_info0_page_cfg_6_scramble_en_6_wd),
8881
8882 // from internal hardware
8883 .de (1'b0),
8884 .d ('0),
8885
8886 // to internal hardware
8887 .qe (),
8888 .q (reg2hw.bank1_info0_page_cfg[6].scramble_en.q),
8889 .ds (),
8890
8891 // to register interface (read)
8892 .qs (bank1_info0_page_cfg_6_scramble_en_6_qs)
8893 );
8894
8895 // F[ecc_en_6]: 23:20
8896 prim_subreg #(
8897 .DW (4),
8898 .SwAccess(prim_subreg_pkg::SwAccessRW),
8899 .RESVAL (4'h9),
8900 .Mubi (1'b1)
8901 ) u_bank1_info0_page_cfg_6_ecc_en_6 (
8902 .clk_i (clk_i),
8903 .rst_ni (rst_ni),
8904
8905 // from register interface
8906 .we (bank1_info0_page_cfg_6_gated_we),
8907 .wd (bank1_info0_page_cfg_6_ecc_en_6_wd),
8908
8909 // from internal hardware
8910 .de (1'b0),
8911 .d ('0),
8912
8913 // to internal hardware
8914 .qe (),
8915 .q (reg2hw.bank1_info0_page_cfg[6].ecc_en.q),
8916 .ds (),
8917
8918 // to register interface (read)
8919 .qs (bank1_info0_page_cfg_6_ecc_en_6_qs)
8920 );
8921
8922 // F[he_en_6]: 27:24
8923 prim_subreg #(
8924 .DW (4),
8925 .SwAccess(prim_subreg_pkg::SwAccessRW),
8926 .RESVAL (4'h9),
8927 .Mubi (1'b1)
8928 ) u_bank1_info0_page_cfg_6_he_en_6 (
8929 .clk_i (clk_i),
8930 .rst_ni (rst_ni),
8931
8932 // from register interface
8933 .we (bank1_info0_page_cfg_6_gated_we),
8934 .wd (bank1_info0_page_cfg_6_he_en_6_wd),
8935
8936 // from internal hardware
8937 .de (1'b0),
8938 .d ('0),
8939
8940 // to internal hardware
8941 .qe (),
8942 .q (reg2hw.bank1_info0_page_cfg[6].he_en.q),
8943 .ds (),
8944
8945 // to register interface (read)
8946 .qs (bank1_info0_page_cfg_6_he_en_6_qs)
8947 );
8948
8949
8950 // Subregister 7 of Multireg bank1_info0_page_cfg
8951 // R[bank1_info0_page_cfg_7]: V(False)
8952 // Create REGWEN-gated WE signal
8953 logic bank1_info0_page_cfg_7_gated_we;
8954 1/1 assign bank1_info0_page_cfg_7_gated_we = bank1_info0_page_cfg_7_we & bank1_info0_regwen_7_qs;
Tests: T1 T2 T3
8955 // F[en_7]: 3:0
8956 prim_subreg #(
8957 .DW (4),
8958 .SwAccess(prim_subreg_pkg::SwAccessRW),
8959 .RESVAL (4'h9),
8960 .Mubi (1'b1)
8961 ) u_bank1_info0_page_cfg_7_en_7 (
8962 .clk_i (clk_i),
8963 .rst_ni (rst_ni),
8964
8965 // from register interface
8966 .we (bank1_info0_page_cfg_7_gated_we),
8967 .wd (bank1_info0_page_cfg_7_en_7_wd),
8968
8969 // from internal hardware
8970 .de (1'b0),
8971 .d ('0),
8972
8973 // to internal hardware
8974 .qe (),
8975 .q (reg2hw.bank1_info0_page_cfg[7].en.q),
8976 .ds (),
8977
8978 // to register interface (read)
8979 .qs (bank1_info0_page_cfg_7_en_7_qs)
8980 );
8981
8982 // F[rd_en_7]: 7:4
8983 prim_subreg #(
8984 .DW (4),
8985 .SwAccess(prim_subreg_pkg::SwAccessRW),
8986 .RESVAL (4'h9),
8987 .Mubi (1'b1)
8988 ) u_bank1_info0_page_cfg_7_rd_en_7 (
8989 .clk_i (clk_i),
8990 .rst_ni (rst_ni),
8991
8992 // from register interface
8993 .we (bank1_info0_page_cfg_7_gated_we),
8994 .wd (bank1_info0_page_cfg_7_rd_en_7_wd),
8995
8996 // from internal hardware
8997 .de (1'b0),
8998 .d ('0),
8999
9000 // to internal hardware
9001 .qe (),
9002 .q (reg2hw.bank1_info0_page_cfg[7].rd_en.q),
9003 .ds (),
9004
9005 // to register interface (read)
9006 .qs (bank1_info0_page_cfg_7_rd_en_7_qs)
9007 );
9008
9009 // F[prog_en_7]: 11:8
9010 prim_subreg #(
9011 .DW (4),
9012 .SwAccess(prim_subreg_pkg::SwAccessRW),
9013 .RESVAL (4'h9),
9014 .Mubi (1'b1)
9015 ) u_bank1_info0_page_cfg_7_prog_en_7 (
9016 .clk_i (clk_i),
9017 .rst_ni (rst_ni),
9018
9019 // from register interface
9020 .we (bank1_info0_page_cfg_7_gated_we),
9021 .wd (bank1_info0_page_cfg_7_prog_en_7_wd),
9022
9023 // from internal hardware
9024 .de (1'b0),
9025 .d ('0),
9026
9027 // to internal hardware
9028 .qe (),
9029 .q (reg2hw.bank1_info0_page_cfg[7].prog_en.q),
9030 .ds (),
9031
9032 // to register interface (read)
9033 .qs (bank1_info0_page_cfg_7_prog_en_7_qs)
9034 );
9035
9036 // F[erase_en_7]: 15:12
9037 prim_subreg #(
9038 .DW (4),
9039 .SwAccess(prim_subreg_pkg::SwAccessRW),
9040 .RESVAL (4'h9),
9041 .Mubi (1'b1)
9042 ) u_bank1_info0_page_cfg_7_erase_en_7 (
9043 .clk_i (clk_i),
9044 .rst_ni (rst_ni),
9045
9046 // from register interface
9047 .we (bank1_info0_page_cfg_7_gated_we),
9048 .wd (bank1_info0_page_cfg_7_erase_en_7_wd),
9049
9050 // from internal hardware
9051 .de (1'b0),
9052 .d ('0),
9053
9054 // to internal hardware
9055 .qe (),
9056 .q (reg2hw.bank1_info0_page_cfg[7].erase_en.q),
9057 .ds (),
9058
9059 // to register interface (read)
9060 .qs (bank1_info0_page_cfg_7_erase_en_7_qs)
9061 );
9062
9063 // F[scramble_en_7]: 19:16
9064 prim_subreg #(
9065 .DW (4),
9066 .SwAccess(prim_subreg_pkg::SwAccessRW),
9067 .RESVAL (4'h9),
9068 .Mubi (1'b1)
9069 ) u_bank1_info0_page_cfg_7_scramble_en_7 (
9070 .clk_i (clk_i),
9071 .rst_ni (rst_ni),
9072
9073 // from register interface
9074 .we (bank1_info0_page_cfg_7_gated_we),
9075 .wd (bank1_info0_page_cfg_7_scramble_en_7_wd),
9076
9077 // from internal hardware
9078 .de (1'b0),
9079 .d ('0),
9080
9081 // to internal hardware
9082 .qe (),
9083 .q (reg2hw.bank1_info0_page_cfg[7].scramble_en.q),
9084 .ds (),
9085
9086 // to register interface (read)
9087 .qs (bank1_info0_page_cfg_7_scramble_en_7_qs)
9088 );
9089
9090 // F[ecc_en_7]: 23:20
9091 prim_subreg #(
9092 .DW (4),
9093 .SwAccess(prim_subreg_pkg::SwAccessRW),
9094 .RESVAL (4'h9),
9095 .Mubi (1'b1)
9096 ) u_bank1_info0_page_cfg_7_ecc_en_7 (
9097 .clk_i (clk_i),
9098 .rst_ni (rst_ni),
9099
9100 // from register interface
9101 .we (bank1_info0_page_cfg_7_gated_we),
9102 .wd (bank1_info0_page_cfg_7_ecc_en_7_wd),
9103
9104 // from internal hardware
9105 .de (1'b0),
9106 .d ('0),
9107
9108 // to internal hardware
9109 .qe (),
9110 .q (reg2hw.bank1_info0_page_cfg[7].ecc_en.q),
9111 .ds (),
9112
9113 // to register interface (read)
9114 .qs (bank1_info0_page_cfg_7_ecc_en_7_qs)
9115 );
9116
9117 // F[he_en_7]: 27:24
9118 prim_subreg #(
9119 .DW (4),
9120 .SwAccess(prim_subreg_pkg::SwAccessRW),
9121 .RESVAL (4'h9),
9122 .Mubi (1'b1)
9123 ) u_bank1_info0_page_cfg_7_he_en_7 (
9124 .clk_i (clk_i),
9125 .rst_ni (rst_ni),
9126
9127 // from register interface
9128 .we (bank1_info0_page_cfg_7_gated_we),
9129 .wd (bank1_info0_page_cfg_7_he_en_7_wd),
9130
9131 // from internal hardware
9132 .de (1'b0),
9133 .d ('0),
9134
9135 // to internal hardware
9136 .qe (),
9137 .q (reg2hw.bank1_info0_page_cfg[7].he_en.q),
9138 .ds (),
9139
9140 // to register interface (read)
9141 .qs (bank1_info0_page_cfg_7_he_en_7_qs)
9142 );
9143
9144
9145 // Subregister 8 of Multireg bank1_info0_page_cfg
9146 // R[bank1_info0_page_cfg_8]: V(False)
9147 // Create REGWEN-gated WE signal
9148 logic bank1_info0_page_cfg_8_gated_we;
9149 1/1 assign bank1_info0_page_cfg_8_gated_we = bank1_info0_page_cfg_8_we & bank1_info0_regwen_8_qs;
Tests: T1 T2 T3
9150 // F[en_8]: 3:0
9151 prim_subreg #(
9152 .DW (4),
9153 .SwAccess(prim_subreg_pkg::SwAccessRW),
9154 .RESVAL (4'h9),
9155 .Mubi (1'b1)
9156 ) u_bank1_info0_page_cfg_8_en_8 (
9157 .clk_i (clk_i),
9158 .rst_ni (rst_ni),
9159
9160 // from register interface
9161 .we (bank1_info0_page_cfg_8_gated_we),
9162 .wd (bank1_info0_page_cfg_8_en_8_wd),
9163
9164 // from internal hardware
9165 .de (1'b0),
9166 .d ('0),
9167
9168 // to internal hardware
9169 .qe (),
9170 .q (reg2hw.bank1_info0_page_cfg[8].en.q),
9171 .ds (),
9172
9173 // to register interface (read)
9174 .qs (bank1_info0_page_cfg_8_en_8_qs)
9175 );
9176
9177 // F[rd_en_8]: 7:4
9178 prim_subreg #(
9179 .DW (4),
9180 .SwAccess(prim_subreg_pkg::SwAccessRW),
9181 .RESVAL (4'h9),
9182 .Mubi (1'b1)
9183 ) u_bank1_info0_page_cfg_8_rd_en_8 (
9184 .clk_i (clk_i),
9185 .rst_ni (rst_ni),
9186
9187 // from register interface
9188 .we (bank1_info0_page_cfg_8_gated_we),
9189 .wd (bank1_info0_page_cfg_8_rd_en_8_wd),
9190
9191 // from internal hardware
9192 .de (1'b0),
9193 .d ('0),
9194
9195 // to internal hardware
9196 .qe (),
9197 .q (reg2hw.bank1_info0_page_cfg[8].rd_en.q),
9198 .ds (),
9199
9200 // to register interface (read)
9201 .qs (bank1_info0_page_cfg_8_rd_en_8_qs)
9202 );
9203
9204 // F[prog_en_8]: 11:8
9205 prim_subreg #(
9206 .DW (4),
9207 .SwAccess(prim_subreg_pkg::SwAccessRW),
9208 .RESVAL (4'h9),
9209 .Mubi (1'b1)
9210 ) u_bank1_info0_page_cfg_8_prog_en_8 (
9211 .clk_i (clk_i),
9212 .rst_ni (rst_ni),
9213
9214 // from register interface
9215 .we (bank1_info0_page_cfg_8_gated_we),
9216 .wd (bank1_info0_page_cfg_8_prog_en_8_wd),
9217
9218 // from internal hardware
9219 .de (1'b0),
9220 .d ('0),
9221
9222 // to internal hardware
9223 .qe (),
9224 .q (reg2hw.bank1_info0_page_cfg[8].prog_en.q),
9225 .ds (),
9226
9227 // to register interface (read)
9228 .qs (bank1_info0_page_cfg_8_prog_en_8_qs)
9229 );
9230
9231 // F[erase_en_8]: 15:12
9232 prim_subreg #(
9233 .DW (4),
9234 .SwAccess(prim_subreg_pkg::SwAccessRW),
9235 .RESVAL (4'h9),
9236 .Mubi (1'b1)
9237 ) u_bank1_info0_page_cfg_8_erase_en_8 (
9238 .clk_i (clk_i),
9239 .rst_ni (rst_ni),
9240
9241 // from register interface
9242 .we (bank1_info0_page_cfg_8_gated_we),
9243 .wd (bank1_info0_page_cfg_8_erase_en_8_wd),
9244
9245 // from internal hardware
9246 .de (1'b0),
9247 .d ('0),
9248
9249 // to internal hardware
9250 .qe (),
9251 .q (reg2hw.bank1_info0_page_cfg[8].erase_en.q),
9252 .ds (),
9253
9254 // to register interface (read)
9255 .qs (bank1_info0_page_cfg_8_erase_en_8_qs)
9256 );
9257
9258 // F[scramble_en_8]: 19:16
9259 prim_subreg #(
9260 .DW (4),
9261 .SwAccess(prim_subreg_pkg::SwAccessRW),
9262 .RESVAL (4'h9),
9263 .Mubi (1'b1)
9264 ) u_bank1_info0_page_cfg_8_scramble_en_8 (
9265 .clk_i (clk_i),
9266 .rst_ni (rst_ni),
9267
9268 // from register interface
9269 .we (bank1_info0_page_cfg_8_gated_we),
9270 .wd (bank1_info0_page_cfg_8_scramble_en_8_wd),
9271
9272 // from internal hardware
9273 .de (1'b0),
9274 .d ('0),
9275
9276 // to internal hardware
9277 .qe (),
9278 .q (reg2hw.bank1_info0_page_cfg[8].scramble_en.q),
9279 .ds (),
9280
9281 // to register interface (read)
9282 .qs (bank1_info0_page_cfg_8_scramble_en_8_qs)
9283 );
9284
9285 // F[ecc_en_8]: 23:20
9286 prim_subreg #(
9287 .DW (4),
9288 .SwAccess(prim_subreg_pkg::SwAccessRW),
9289 .RESVAL (4'h9),
9290 .Mubi (1'b1)
9291 ) u_bank1_info0_page_cfg_8_ecc_en_8 (
9292 .clk_i (clk_i),
9293 .rst_ni (rst_ni),
9294
9295 // from register interface
9296 .we (bank1_info0_page_cfg_8_gated_we),
9297 .wd (bank1_info0_page_cfg_8_ecc_en_8_wd),
9298
9299 // from internal hardware
9300 .de (1'b0),
9301 .d ('0),
9302
9303 // to internal hardware
9304 .qe (),
9305 .q (reg2hw.bank1_info0_page_cfg[8].ecc_en.q),
9306 .ds (),
9307
9308 // to register interface (read)
9309 .qs (bank1_info0_page_cfg_8_ecc_en_8_qs)
9310 );
9311
9312 // F[he_en_8]: 27:24
9313 prim_subreg #(
9314 .DW (4),
9315 .SwAccess(prim_subreg_pkg::SwAccessRW),
9316 .RESVAL (4'h9),
9317 .Mubi (1'b1)
9318 ) u_bank1_info0_page_cfg_8_he_en_8 (
9319 .clk_i (clk_i),
9320 .rst_ni (rst_ni),
9321
9322 // from register interface
9323 .we (bank1_info0_page_cfg_8_gated_we),
9324 .wd (bank1_info0_page_cfg_8_he_en_8_wd),
9325
9326 // from internal hardware
9327 .de (1'b0),
9328 .d ('0),
9329
9330 // to internal hardware
9331 .qe (),
9332 .q (reg2hw.bank1_info0_page_cfg[8].he_en.q),
9333 .ds (),
9334
9335 // to register interface (read)
9336 .qs (bank1_info0_page_cfg_8_he_en_8_qs)
9337 );
9338
9339
9340 // Subregister 9 of Multireg bank1_info0_page_cfg
9341 // R[bank1_info0_page_cfg_9]: V(False)
9342 // Create REGWEN-gated WE signal
9343 logic bank1_info0_page_cfg_9_gated_we;
9344 1/1 assign bank1_info0_page_cfg_9_gated_we = bank1_info0_page_cfg_9_we & bank1_info0_regwen_9_qs;
Tests: T1 T2 T3
9345 // F[en_9]: 3:0
9346 prim_subreg #(
9347 .DW (4),
9348 .SwAccess(prim_subreg_pkg::SwAccessRW),
9349 .RESVAL (4'h9),
9350 .Mubi (1'b1)
9351 ) u_bank1_info0_page_cfg_9_en_9 (
9352 .clk_i (clk_i),
9353 .rst_ni (rst_ni),
9354
9355 // from register interface
9356 .we (bank1_info0_page_cfg_9_gated_we),
9357 .wd (bank1_info0_page_cfg_9_en_9_wd),
9358
9359 // from internal hardware
9360 .de (1'b0),
9361 .d ('0),
9362
9363 // to internal hardware
9364 .qe (),
9365 .q (reg2hw.bank1_info0_page_cfg[9].en.q),
9366 .ds (),
9367
9368 // to register interface (read)
9369 .qs (bank1_info0_page_cfg_9_en_9_qs)
9370 );
9371
9372 // F[rd_en_9]: 7:4
9373 prim_subreg #(
9374 .DW (4),
9375 .SwAccess(prim_subreg_pkg::SwAccessRW),
9376 .RESVAL (4'h9),
9377 .Mubi (1'b1)
9378 ) u_bank1_info0_page_cfg_9_rd_en_9 (
9379 .clk_i (clk_i),
9380 .rst_ni (rst_ni),
9381
9382 // from register interface
9383 .we (bank1_info0_page_cfg_9_gated_we),
9384 .wd (bank1_info0_page_cfg_9_rd_en_9_wd),
9385
9386 // from internal hardware
9387 .de (1'b0),
9388 .d ('0),
9389
9390 // to internal hardware
9391 .qe (),
9392 .q (reg2hw.bank1_info0_page_cfg[9].rd_en.q),
9393 .ds (),
9394
9395 // to register interface (read)
9396 .qs (bank1_info0_page_cfg_9_rd_en_9_qs)
9397 );
9398
9399 // F[prog_en_9]: 11:8
9400 prim_subreg #(
9401 .DW (4),
9402 .SwAccess(prim_subreg_pkg::SwAccessRW),
9403 .RESVAL (4'h9),
9404 .Mubi (1'b1)
9405 ) u_bank1_info0_page_cfg_9_prog_en_9 (
9406 .clk_i (clk_i),
9407 .rst_ni (rst_ni),
9408
9409 // from register interface
9410 .we (bank1_info0_page_cfg_9_gated_we),
9411 .wd (bank1_info0_page_cfg_9_prog_en_9_wd),
9412
9413 // from internal hardware
9414 .de (1'b0),
9415 .d ('0),
9416
9417 // to internal hardware
9418 .qe (),
9419 .q (reg2hw.bank1_info0_page_cfg[9].prog_en.q),
9420 .ds (),
9421
9422 // to register interface (read)
9423 .qs (bank1_info0_page_cfg_9_prog_en_9_qs)
9424 );
9425
9426 // F[erase_en_9]: 15:12
9427 prim_subreg #(
9428 .DW (4),
9429 .SwAccess(prim_subreg_pkg::SwAccessRW),
9430 .RESVAL (4'h9),
9431 .Mubi (1'b1)
9432 ) u_bank1_info0_page_cfg_9_erase_en_9 (
9433 .clk_i (clk_i),
9434 .rst_ni (rst_ni),
9435
9436 // from register interface
9437 .we (bank1_info0_page_cfg_9_gated_we),
9438 .wd (bank1_info0_page_cfg_9_erase_en_9_wd),
9439
9440 // from internal hardware
9441 .de (1'b0),
9442 .d ('0),
9443
9444 // to internal hardware
9445 .qe (),
9446 .q (reg2hw.bank1_info0_page_cfg[9].erase_en.q),
9447 .ds (),
9448
9449 // to register interface (read)
9450 .qs (bank1_info0_page_cfg_9_erase_en_9_qs)
9451 );
9452
9453 // F[scramble_en_9]: 19:16
9454 prim_subreg #(
9455 .DW (4),
9456 .SwAccess(prim_subreg_pkg::SwAccessRW),
9457 .RESVAL (4'h9),
9458 .Mubi (1'b1)
9459 ) u_bank1_info0_page_cfg_9_scramble_en_9 (
9460 .clk_i (clk_i),
9461 .rst_ni (rst_ni),
9462
9463 // from register interface
9464 .we (bank1_info0_page_cfg_9_gated_we),
9465 .wd (bank1_info0_page_cfg_9_scramble_en_9_wd),
9466
9467 // from internal hardware
9468 .de (1'b0),
9469 .d ('0),
9470
9471 // to internal hardware
9472 .qe (),
9473 .q (reg2hw.bank1_info0_page_cfg[9].scramble_en.q),
9474 .ds (),
9475
9476 // to register interface (read)
9477 .qs (bank1_info0_page_cfg_9_scramble_en_9_qs)
9478 );
9479
9480 // F[ecc_en_9]: 23:20
9481 prim_subreg #(
9482 .DW (4),
9483 .SwAccess(prim_subreg_pkg::SwAccessRW),
9484 .RESVAL (4'h9),
9485 .Mubi (1'b1)
9486 ) u_bank1_info0_page_cfg_9_ecc_en_9 (
9487 .clk_i (clk_i),
9488 .rst_ni (rst_ni),
9489
9490 // from register interface
9491 .we (bank1_info0_page_cfg_9_gated_we),
9492 .wd (bank1_info0_page_cfg_9_ecc_en_9_wd),
9493
9494 // from internal hardware
9495 .de (1'b0),
9496 .d ('0),
9497
9498 // to internal hardware
9499 .qe (),
9500 .q (reg2hw.bank1_info0_page_cfg[9].ecc_en.q),
9501 .ds (),
9502
9503 // to register interface (read)
9504 .qs (bank1_info0_page_cfg_9_ecc_en_9_qs)
9505 );
9506
9507 // F[he_en_9]: 27:24
9508 prim_subreg #(
9509 .DW (4),
9510 .SwAccess(prim_subreg_pkg::SwAccessRW),
9511 .RESVAL (4'h9),
9512 .Mubi (1'b1)
9513 ) u_bank1_info0_page_cfg_9_he_en_9 (
9514 .clk_i (clk_i),
9515 .rst_ni (rst_ni),
9516
9517 // from register interface
9518 .we (bank1_info0_page_cfg_9_gated_we),
9519 .wd (bank1_info0_page_cfg_9_he_en_9_wd),
9520
9521 // from internal hardware
9522 .de (1'b0),
9523 .d ('0),
9524
9525 // to internal hardware
9526 .qe (),
9527 .q (reg2hw.bank1_info0_page_cfg[9].he_en.q),
9528 .ds (),
9529
9530 // to register interface (read)
9531 .qs (bank1_info0_page_cfg_9_he_en_9_qs)
9532 );
9533
9534
9535 // Subregister 0 of Multireg bank1_info1_regwen
9536 // R[bank1_info1_regwen]: V(False)
9537 prim_subreg #(
9538 .DW (1),
9539 .SwAccess(prim_subreg_pkg::SwAccessW0C),
9540 .RESVAL (1'h1),
9541 .Mubi (1'b0)
9542 ) u_bank1_info1_regwen (
9543 .clk_i (clk_i),
9544 .rst_ni (rst_ni),
9545
9546 // from register interface
9547 .we (bank1_info1_regwen_we),
9548 .wd (bank1_info1_regwen_wd),
9549
9550 // from internal hardware
9551 .de (1'b0),
9552 .d ('0),
9553
9554 // to internal hardware
9555 .qe (),
9556 .q (),
9557 .ds (),
9558
9559 // to register interface (read)
9560 .qs (bank1_info1_regwen_qs)
9561 );
9562
9563
9564 // Subregister 0 of Multireg bank1_info1_page_cfg
9565 // R[bank1_info1_page_cfg]: V(False)
9566 // Create REGWEN-gated WE signal
9567 logic bank1_info1_page_cfg_gated_we;
9568 1/1 assign bank1_info1_page_cfg_gated_we = bank1_info1_page_cfg_we & bank1_info1_regwen_qs;
Tests: T1 T2 T3
9569 // F[en_0]: 3:0
9570 prim_subreg #(
9571 .DW (4),
9572 .SwAccess(prim_subreg_pkg::SwAccessRW),
9573 .RESVAL (4'h9),
9574 .Mubi (1'b1)
9575 ) u_bank1_info1_page_cfg_en_0 (
9576 .clk_i (clk_i),
9577 .rst_ni (rst_ni),
9578
9579 // from register interface
9580 .we (bank1_info1_page_cfg_gated_we),
9581 .wd (bank1_info1_page_cfg_en_0_wd),
9582
9583 // from internal hardware
9584 .de (1'b0),
9585 .d ('0),
9586
9587 // to internal hardware
9588 .qe (),
9589 .q (reg2hw.bank1_info1_page_cfg[0].en.q),
9590 .ds (),
9591
9592 // to register interface (read)
9593 .qs (bank1_info1_page_cfg_en_0_qs)
9594 );
9595
9596 // F[rd_en_0]: 7:4
9597 prim_subreg #(
9598 .DW (4),
9599 .SwAccess(prim_subreg_pkg::SwAccessRW),
9600 .RESVAL (4'h9),
9601 .Mubi (1'b1)
9602 ) u_bank1_info1_page_cfg_rd_en_0 (
9603 .clk_i (clk_i),
9604 .rst_ni (rst_ni),
9605
9606 // from register interface
9607 .we (bank1_info1_page_cfg_gated_we),
9608 .wd (bank1_info1_page_cfg_rd_en_0_wd),
9609
9610 // from internal hardware
9611 .de (1'b0),
9612 .d ('0),
9613
9614 // to internal hardware
9615 .qe (),
9616 .q (reg2hw.bank1_info1_page_cfg[0].rd_en.q),
9617 .ds (),
9618
9619 // to register interface (read)
9620 .qs (bank1_info1_page_cfg_rd_en_0_qs)
9621 );
9622
9623 // F[prog_en_0]: 11:8
9624 prim_subreg #(
9625 .DW (4),
9626 .SwAccess(prim_subreg_pkg::SwAccessRW),
9627 .RESVAL (4'h9),
9628 .Mubi (1'b1)
9629 ) u_bank1_info1_page_cfg_prog_en_0 (
9630 .clk_i (clk_i),
9631 .rst_ni (rst_ni),
9632
9633 // from register interface
9634 .we (bank1_info1_page_cfg_gated_we),
9635 .wd (bank1_info1_page_cfg_prog_en_0_wd),
9636
9637 // from internal hardware
9638 .de (1'b0),
9639 .d ('0),
9640
9641 // to internal hardware
9642 .qe (),
9643 .q (reg2hw.bank1_info1_page_cfg[0].prog_en.q),
9644 .ds (),
9645
9646 // to register interface (read)
9647 .qs (bank1_info1_page_cfg_prog_en_0_qs)
9648 );
9649
9650 // F[erase_en_0]: 15:12
9651 prim_subreg #(
9652 .DW (4),
9653 .SwAccess(prim_subreg_pkg::SwAccessRW),
9654 .RESVAL (4'h9),
9655 .Mubi (1'b1)
9656 ) u_bank1_info1_page_cfg_erase_en_0 (
9657 .clk_i (clk_i),
9658 .rst_ni (rst_ni),
9659
9660 // from register interface
9661 .we (bank1_info1_page_cfg_gated_we),
9662 .wd (bank1_info1_page_cfg_erase_en_0_wd),
9663
9664 // from internal hardware
9665 .de (1'b0),
9666 .d ('0),
9667
9668 // to internal hardware
9669 .qe (),
9670 .q (reg2hw.bank1_info1_page_cfg[0].erase_en.q),
9671 .ds (),
9672
9673 // to register interface (read)
9674 .qs (bank1_info1_page_cfg_erase_en_0_qs)
9675 );
9676
9677 // F[scramble_en_0]: 19:16
9678 prim_subreg #(
9679 .DW (4),
9680 .SwAccess(prim_subreg_pkg::SwAccessRW),
9681 .RESVAL (4'h9),
9682 .Mubi (1'b1)
9683 ) u_bank1_info1_page_cfg_scramble_en_0 (
9684 .clk_i (clk_i),
9685 .rst_ni (rst_ni),
9686
9687 // from register interface
9688 .we (bank1_info1_page_cfg_gated_we),
9689 .wd (bank1_info1_page_cfg_scramble_en_0_wd),
9690
9691 // from internal hardware
9692 .de (1'b0),
9693 .d ('0),
9694
9695 // to internal hardware
9696 .qe (),
9697 .q (reg2hw.bank1_info1_page_cfg[0].scramble_en.q),
9698 .ds (),
9699
9700 // to register interface (read)
9701 .qs (bank1_info1_page_cfg_scramble_en_0_qs)
9702 );
9703
9704 // F[ecc_en_0]: 23:20
9705 prim_subreg #(
9706 .DW (4),
9707 .SwAccess(prim_subreg_pkg::SwAccessRW),
9708 .RESVAL (4'h9),
9709 .Mubi (1'b1)
9710 ) u_bank1_info1_page_cfg_ecc_en_0 (
9711 .clk_i (clk_i),
9712 .rst_ni (rst_ni),
9713
9714 // from register interface
9715 .we (bank1_info1_page_cfg_gated_we),
9716 .wd (bank1_info1_page_cfg_ecc_en_0_wd),
9717
9718 // from internal hardware
9719 .de (1'b0),
9720 .d ('0),
9721
9722 // to internal hardware
9723 .qe (),
9724 .q (reg2hw.bank1_info1_page_cfg[0].ecc_en.q),
9725 .ds (),
9726
9727 // to register interface (read)
9728 .qs (bank1_info1_page_cfg_ecc_en_0_qs)
9729 );
9730
9731 // F[he_en_0]: 27:24
9732 prim_subreg #(
9733 .DW (4),
9734 .SwAccess(prim_subreg_pkg::SwAccessRW),
9735 .RESVAL (4'h9),
9736 .Mubi (1'b1)
9737 ) u_bank1_info1_page_cfg_he_en_0 (
9738 .clk_i (clk_i),
9739 .rst_ni (rst_ni),
9740
9741 // from register interface
9742 .we (bank1_info1_page_cfg_gated_we),
9743 .wd (bank1_info1_page_cfg_he_en_0_wd),
9744
9745 // from internal hardware
9746 .de (1'b0),
9747 .d ('0),
9748
9749 // to internal hardware
9750 .qe (),
9751 .q (reg2hw.bank1_info1_page_cfg[0].he_en.q),
9752 .ds (),
9753
9754 // to register interface (read)
9755 .qs (bank1_info1_page_cfg_he_en_0_qs)
9756 );
9757
9758
9759 // Subregister 0 of Multireg bank1_info2_regwen
9760 // R[bank1_info2_regwen_0]: V(False)
9761 prim_subreg #(
9762 .DW (1),
9763 .SwAccess(prim_subreg_pkg::SwAccessW0C),
9764 .RESVAL (1'h1),
9765 .Mubi (1'b0)
9766 ) u_bank1_info2_regwen_0 (
9767 .clk_i (clk_i),
9768 .rst_ni (rst_ni),
9769
9770 // from register interface
9771 .we (bank1_info2_regwen_0_we),
9772 .wd (bank1_info2_regwen_0_wd),
9773
9774 // from internal hardware
9775 .de (1'b0),
9776 .d ('0),
9777
9778 // to internal hardware
9779 .qe (),
9780 .q (),
9781 .ds (),
9782
9783 // to register interface (read)
9784 .qs (bank1_info2_regwen_0_qs)
9785 );
9786
9787
9788 // Subregister 1 of Multireg bank1_info2_regwen
9789 // R[bank1_info2_regwen_1]: V(False)
9790 prim_subreg #(
9791 .DW (1),
9792 .SwAccess(prim_subreg_pkg::SwAccessW0C),
9793 .RESVAL (1'h1),
9794 .Mubi (1'b0)
9795 ) u_bank1_info2_regwen_1 (
9796 .clk_i (clk_i),
9797 .rst_ni (rst_ni),
9798
9799 // from register interface
9800 .we (bank1_info2_regwen_1_we),
9801 .wd (bank1_info2_regwen_1_wd),
9802
9803 // from internal hardware
9804 .de (1'b0),
9805 .d ('0),
9806
9807 // to internal hardware
9808 .qe (),
9809 .q (),
9810 .ds (),
9811
9812 // to register interface (read)
9813 .qs (bank1_info2_regwen_1_qs)
9814 );
9815
9816
9817 // Subregister 0 of Multireg bank1_info2_page_cfg
9818 // R[bank1_info2_page_cfg_0]: V(False)
9819 // Create REGWEN-gated WE signal
9820 logic bank1_info2_page_cfg_0_gated_we;
9821 1/1 assign bank1_info2_page_cfg_0_gated_we = bank1_info2_page_cfg_0_we & bank1_info2_regwen_0_qs;
Tests: T1 T2 T3
9822 // F[en_0]: 3:0
9823 prim_subreg #(
9824 .DW (4),
9825 .SwAccess(prim_subreg_pkg::SwAccessRW),
9826 .RESVAL (4'h9),
9827 .Mubi (1'b1)
9828 ) u_bank1_info2_page_cfg_0_en_0 (
9829 .clk_i (clk_i),
9830 .rst_ni (rst_ni),
9831
9832 // from register interface
9833 .we (bank1_info2_page_cfg_0_gated_we),
9834 .wd (bank1_info2_page_cfg_0_en_0_wd),
9835
9836 // from internal hardware
9837 .de (1'b0),
9838 .d ('0),
9839
9840 // to internal hardware
9841 .qe (),
9842 .q (reg2hw.bank1_info2_page_cfg[0].en.q),
9843 .ds (),
9844
9845 // to register interface (read)
9846 .qs (bank1_info2_page_cfg_0_en_0_qs)
9847 );
9848
9849 // F[rd_en_0]: 7:4
9850 prim_subreg #(
9851 .DW (4),
9852 .SwAccess(prim_subreg_pkg::SwAccessRW),
9853 .RESVAL (4'h9),
9854 .Mubi (1'b1)
9855 ) u_bank1_info2_page_cfg_0_rd_en_0 (
9856 .clk_i (clk_i),
9857 .rst_ni (rst_ni),
9858
9859 // from register interface
9860 .we (bank1_info2_page_cfg_0_gated_we),
9861 .wd (bank1_info2_page_cfg_0_rd_en_0_wd),
9862
9863 // from internal hardware
9864 .de (1'b0),
9865 .d ('0),
9866
9867 // to internal hardware
9868 .qe (),
9869 .q (reg2hw.bank1_info2_page_cfg[0].rd_en.q),
9870 .ds (),
9871
9872 // to register interface (read)
9873 .qs (bank1_info2_page_cfg_0_rd_en_0_qs)
9874 );
9875
9876 // F[prog_en_0]: 11:8
9877 prim_subreg #(
9878 .DW (4),
9879 .SwAccess(prim_subreg_pkg::SwAccessRW),
9880 .RESVAL (4'h9),
9881 .Mubi (1'b1)
9882 ) u_bank1_info2_page_cfg_0_prog_en_0 (
9883 .clk_i (clk_i),
9884 .rst_ni (rst_ni),
9885
9886 // from register interface
9887 .we (bank1_info2_page_cfg_0_gated_we),
9888 .wd (bank1_info2_page_cfg_0_prog_en_0_wd),
9889
9890 // from internal hardware
9891 .de (1'b0),
9892 .d ('0),
9893
9894 // to internal hardware
9895 .qe (),
9896 .q (reg2hw.bank1_info2_page_cfg[0].prog_en.q),
9897 .ds (),
9898
9899 // to register interface (read)
9900 .qs (bank1_info2_page_cfg_0_prog_en_0_qs)
9901 );
9902
9903 // F[erase_en_0]: 15:12
9904 prim_subreg #(
9905 .DW (4),
9906 .SwAccess(prim_subreg_pkg::SwAccessRW),
9907 .RESVAL (4'h9),
9908 .Mubi (1'b1)
9909 ) u_bank1_info2_page_cfg_0_erase_en_0 (
9910 .clk_i (clk_i),
9911 .rst_ni (rst_ni),
9912
9913 // from register interface
9914 .we (bank1_info2_page_cfg_0_gated_we),
9915 .wd (bank1_info2_page_cfg_0_erase_en_0_wd),
9916
9917 // from internal hardware
9918 .de (1'b0),
9919 .d ('0),
9920
9921 // to internal hardware
9922 .qe (),
9923 .q (reg2hw.bank1_info2_page_cfg[0].erase_en.q),
9924 .ds (),
9925
9926 // to register interface (read)
9927 .qs (bank1_info2_page_cfg_0_erase_en_0_qs)
9928 );
9929
9930 // F[scramble_en_0]: 19:16
9931 prim_subreg #(
9932 .DW (4),
9933 .SwAccess(prim_subreg_pkg::SwAccessRW),
9934 .RESVAL (4'h9),
9935 .Mubi (1'b1)
9936 ) u_bank1_info2_page_cfg_0_scramble_en_0 (
9937 .clk_i (clk_i),
9938 .rst_ni (rst_ni),
9939
9940 // from register interface
9941 .we (bank1_info2_page_cfg_0_gated_we),
9942 .wd (bank1_info2_page_cfg_0_scramble_en_0_wd),
9943
9944 // from internal hardware
9945 .de (1'b0),
9946 .d ('0),
9947
9948 // to internal hardware
9949 .qe (),
9950 .q (reg2hw.bank1_info2_page_cfg[0].scramble_en.q),
9951 .ds (),
9952
9953 // to register interface (read)
9954 .qs (bank1_info2_page_cfg_0_scramble_en_0_qs)
9955 );
9956
9957 // F[ecc_en_0]: 23:20
9958 prim_subreg #(
9959 .DW (4),
9960 .SwAccess(prim_subreg_pkg::SwAccessRW),
9961 .RESVAL (4'h9),
9962 .Mubi (1'b1)
9963 ) u_bank1_info2_page_cfg_0_ecc_en_0 (
9964 .clk_i (clk_i),
9965 .rst_ni (rst_ni),
9966
9967 // from register interface
9968 .we (bank1_info2_page_cfg_0_gated_we),
9969 .wd (bank1_info2_page_cfg_0_ecc_en_0_wd),
9970
9971 // from internal hardware
9972 .de (1'b0),
9973 .d ('0),
9974
9975 // to internal hardware
9976 .qe (),
9977 .q (reg2hw.bank1_info2_page_cfg[0].ecc_en.q),
9978 .ds (),
9979
9980 // to register interface (read)
9981 .qs (bank1_info2_page_cfg_0_ecc_en_0_qs)
9982 );
9983
9984 // F[he_en_0]: 27:24
9985 prim_subreg #(
9986 .DW (4),
9987 .SwAccess(prim_subreg_pkg::SwAccessRW),
9988 .RESVAL (4'h9),
9989 .Mubi (1'b1)
9990 ) u_bank1_info2_page_cfg_0_he_en_0 (
9991 .clk_i (clk_i),
9992 .rst_ni (rst_ni),
9993
9994 // from register interface
9995 .we (bank1_info2_page_cfg_0_gated_we),
9996 .wd (bank1_info2_page_cfg_0_he_en_0_wd),
9997
9998 // from internal hardware
9999 .de (1'b0),
10000 .d ('0),
10001
10002 // to internal hardware
10003 .qe (),
10004 .q (reg2hw.bank1_info2_page_cfg[0].he_en.q),
10005 .ds (),
10006
10007 // to register interface (read)
10008 .qs (bank1_info2_page_cfg_0_he_en_0_qs)
10009 );
10010
10011
10012 // Subregister 1 of Multireg bank1_info2_page_cfg
10013 // R[bank1_info2_page_cfg_1]: V(False)
10014 // Create REGWEN-gated WE signal
10015 logic bank1_info2_page_cfg_1_gated_we;
10016 1/1 assign bank1_info2_page_cfg_1_gated_we = bank1_info2_page_cfg_1_we & bank1_info2_regwen_1_qs;
Tests: T1 T2 T3
10017 // F[en_1]: 3:0
10018 prim_subreg #(
10019 .DW (4),
10020 .SwAccess(prim_subreg_pkg::SwAccessRW),
10021 .RESVAL (4'h9),
10022 .Mubi (1'b1)
10023 ) u_bank1_info2_page_cfg_1_en_1 (
10024 .clk_i (clk_i),
10025 .rst_ni (rst_ni),
10026
10027 // from register interface
10028 .we (bank1_info2_page_cfg_1_gated_we),
10029 .wd (bank1_info2_page_cfg_1_en_1_wd),
10030
10031 // from internal hardware
10032 .de (1'b0),
10033 .d ('0),
10034
10035 // to internal hardware
10036 .qe (),
10037 .q (reg2hw.bank1_info2_page_cfg[1].en.q),
10038 .ds (),
10039
10040 // to register interface (read)
10041 .qs (bank1_info2_page_cfg_1_en_1_qs)
10042 );
10043
10044 // F[rd_en_1]: 7:4
10045 prim_subreg #(
10046 .DW (4),
10047 .SwAccess(prim_subreg_pkg::SwAccessRW),
10048 .RESVAL (4'h9),
10049 .Mubi (1'b1)
10050 ) u_bank1_info2_page_cfg_1_rd_en_1 (
10051 .clk_i (clk_i),
10052 .rst_ni (rst_ni),
10053
10054 // from register interface
10055 .we (bank1_info2_page_cfg_1_gated_we),
10056 .wd (bank1_info2_page_cfg_1_rd_en_1_wd),
10057
10058 // from internal hardware
10059 .de (1'b0),
10060 .d ('0),
10061
10062 // to internal hardware
10063 .qe (),
10064 .q (reg2hw.bank1_info2_page_cfg[1].rd_en.q),
10065 .ds (),
10066
10067 // to register interface (read)
10068 .qs (bank1_info2_page_cfg_1_rd_en_1_qs)
10069 );
10070
10071 // F[prog_en_1]: 11:8
10072 prim_subreg #(
10073 .DW (4),
10074 .SwAccess(prim_subreg_pkg::SwAccessRW),
10075 .RESVAL (4'h9),
10076 .Mubi (1'b1)
10077 ) u_bank1_info2_page_cfg_1_prog_en_1 (
10078 .clk_i (clk_i),
10079 .rst_ni (rst_ni),
10080
10081 // from register interface
10082 .we (bank1_info2_page_cfg_1_gated_we),
10083 .wd (bank1_info2_page_cfg_1_prog_en_1_wd),
10084
10085 // from internal hardware
10086 .de (1'b0),
10087 .d ('0),
10088
10089 // to internal hardware
10090 .qe (),
10091 .q (reg2hw.bank1_info2_page_cfg[1].prog_en.q),
10092 .ds (),
10093
10094 // to register interface (read)
10095 .qs (bank1_info2_page_cfg_1_prog_en_1_qs)
10096 );
10097
10098 // F[erase_en_1]: 15:12
10099 prim_subreg #(
10100 .DW (4),
10101 .SwAccess(prim_subreg_pkg::SwAccessRW),
10102 .RESVAL (4'h9),
10103 .Mubi (1'b1)
10104 ) u_bank1_info2_page_cfg_1_erase_en_1 (
10105 .clk_i (clk_i),
10106 .rst_ni (rst_ni),
10107
10108 // from register interface
10109 .we (bank1_info2_page_cfg_1_gated_we),
10110 .wd (bank1_info2_page_cfg_1_erase_en_1_wd),
10111
10112 // from internal hardware
10113 .de (1'b0),
10114 .d ('0),
10115
10116 // to internal hardware
10117 .qe (),
10118 .q (reg2hw.bank1_info2_page_cfg[1].erase_en.q),
10119 .ds (),
10120
10121 // to register interface (read)
10122 .qs (bank1_info2_page_cfg_1_erase_en_1_qs)
10123 );
10124
10125 // F[scramble_en_1]: 19:16
10126 prim_subreg #(
10127 .DW (4),
10128 .SwAccess(prim_subreg_pkg::SwAccessRW),
10129 .RESVAL (4'h9),
10130 .Mubi (1'b1)
10131 ) u_bank1_info2_page_cfg_1_scramble_en_1 (
10132 .clk_i (clk_i),
10133 .rst_ni (rst_ni),
10134
10135 // from register interface
10136 .we (bank1_info2_page_cfg_1_gated_we),
10137 .wd (bank1_info2_page_cfg_1_scramble_en_1_wd),
10138
10139 // from internal hardware
10140 .de (1'b0),
10141 .d ('0),
10142
10143 // to internal hardware
10144 .qe (),
10145 .q (reg2hw.bank1_info2_page_cfg[1].scramble_en.q),
10146 .ds (),
10147
10148 // to register interface (read)
10149 .qs (bank1_info2_page_cfg_1_scramble_en_1_qs)
10150 );
10151
10152 // F[ecc_en_1]: 23:20
10153 prim_subreg #(
10154 .DW (4),
10155 .SwAccess(prim_subreg_pkg::SwAccessRW),
10156 .RESVAL (4'h9),
10157 .Mubi (1'b1)
10158 ) u_bank1_info2_page_cfg_1_ecc_en_1 (
10159 .clk_i (clk_i),
10160 .rst_ni (rst_ni),
10161
10162 // from register interface
10163 .we (bank1_info2_page_cfg_1_gated_we),
10164 .wd (bank1_info2_page_cfg_1_ecc_en_1_wd),
10165
10166 // from internal hardware
10167 .de (1'b0),
10168 .d ('0),
10169
10170 // to internal hardware
10171 .qe (),
10172 .q (reg2hw.bank1_info2_page_cfg[1].ecc_en.q),
10173 .ds (),
10174
10175 // to register interface (read)
10176 .qs (bank1_info2_page_cfg_1_ecc_en_1_qs)
10177 );
10178
10179 // F[he_en_1]: 27:24
10180 prim_subreg #(
10181 .DW (4),
10182 .SwAccess(prim_subreg_pkg::SwAccessRW),
10183 .RESVAL (4'h9),
10184 .Mubi (1'b1)
10185 ) u_bank1_info2_page_cfg_1_he_en_1 (
10186 .clk_i (clk_i),
10187 .rst_ni (rst_ni),
10188
10189 // from register interface
10190 .we (bank1_info2_page_cfg_1_gated_we),
10191 .wd (bank1_info2_page_cfg_1_he_en_1_wd),
10192
10193 // from internal hardware
10194 .de (1'b0),
10195 .d ('0),
10196
10197 // to internal hardware
10198 .qe (),
10199 .q (reg2hw.bank1_info2_page_cfg[1].he_en.q),
10200 .ds (),
10201
10202 // to register interface (read)
10203 .qs (bank1_info2_page_cfg_1_he_en_1_qs)
10204 );
10205
10206
10207 // R[hw_info_cfg_override]: V(False)
10208 // F[scramble_dis]: 3:0
10209 prim_subreg #(
10210 .DW (4),
10211 .SwAccess(prim_subreg_pkg::SwAccessRW),
10212 .RESVAL (4'h9),
10213 .Mubi (1'b1)
10214 ) u_hw_info_cfg_override_scramble_dis (
10215 .clk_i (clk_i),
10216 .rst_ni (rst_ni),
10217
10218 // from register interface
10219 .we (hw_info_cfg_override_we),
10220 .wd (hw_info_cfg_override_scramble_dis_wd),
10221
10222 // from internal hardware
10223 .de (1'b0),
10224 .d ('0),
10225
10226 // to internal hardware
10227 .qe (),
10228 .q (reg2hw.hw_info_cfg_override.scramble_dis.q),
10229 .ds (),
10230
10231 // to register interface (read)
10232 .qs (hw_info_cfg_override_scramble_dis_qs)
10233 );
10234
10235 // F[ecc_dis]: 7:4
10236 prim_subreg #(
10237 .DW (4),
10238 .SwAccess(prim_subreg_pkg::SwAccessRW),
10239 .RESVAL (4'h9),
10240 .Mubi (1'b1)
10241 ) u_hw_info_cfg_override_ecc_dis (
10242 .clk_i (clk_i),
10243 .rst_ni (rst_ni),
10244
10245 // from register interface
10246 .we (hw_info_cfg_override_we),
10247 .wd (hw_info_cfg_override_ecc_dis_wd),
10248
10249 // from internal hardware
10250 .de (1'b0),
10251 .d ('0),
10252
10253 // to internal hardware
10254 .qe (),
10255 .q (reg2hw.hw_info_cfg_override.ecc_dis.q),
10256 .ds (),
10257
10258 // to register interface (read)
10259 .qs (hw_info_cfg_override_ecc_dis_qs)
10260 );
10261
10262
10263 // R[bank_cfg_regwen]: V(False)
10264 prim_subreg #(
10265 .DW (1),
10266 .SwAccess(prim_subreg_pkg::SwAccessW0C),
10267 .RESVAL (1'h1),
10268 .Mubi (1'b0)
10269 ) u_bank_cfg_regwen (
10270 .clk_i (clk_i),
10271 .rst_ni (rst_ni),
10272
10273 // from register interface
10274 .we (bank_cfg_regwen_we),
10275 .wd (bank_cfg_regwen_wd),
10276
10277 // from internal hardware
10278 .de (1'b0),
10279 .d ('0),
10280
10281 // to internal hardware
10282 .qe (),
10283 .q (),
10284 .ds (),
10285
10286 // to register interface (read)
10287 .qs (bank_cfg_regwen_qs)
10288 );
10289
10290
10291 // Subregister 0 of Multireg mp_bank_cfg_shadowed
10292 // R[mp_bank_cfg_shadowed]: V(False)
10293 // Create REGWEN-gated WE signal
10294 logic mp_bank_cfg_shadowed_gated_we;
10295 1/1 assign mp_bank_cfg_shadowed_gated_we = mp_bank_cfg_shadowed_we & bank_cfg_regwen_qs;
Tests: T1 T2 T3
10296 // F[erase_en_0]: 0:0
10297 prim_subreg_shadow #(
10298 .DW (1),
10299 .SwAccess(prim_subreg_pkg::SwAccessRW),
10300 .RESVAL (1'h0),
10301 .Mubi (1'b0)
10302 ) u_mp_bank_cfg_shadowed_erase_en_0 (
10303 .clk_i (clk_i),
10304 .rst_ni (rst_ni),
10305 .rst_shadowed_ni (rst_shadowed_ni),
10306
10307 // from register interface
10308 .re (mp_bank_cfg_shadowed_re),
10309 .we (mp_bank_cfg_shadowed_gated_we),
10310 .wd (mp_bank_cfg_shadowed_erase_en_0_wd),
10311
10312 // from internal hardware
10313 .de (1'b0),
10314 .d ('0),
10315
10316 // to internal hardware
10317 .qe (),
10318 .q (reg2hw.mp_bank_cfg_shadowed[0].q),
10319 .ds (),
10320
10321 // to register interface (read)
10322 .qs (mp_bank_cfg_shadowed_erase_en_0_qs),
10323
10324 // Shadow register phase. Relevant for hwext only.
10325 .phase (),
10326
10327 // Shadow register error conditions
10328 .err_update (mp_bank_cfg_shadowed_erase_en_0_update_err),
10329 .err_storage (mp_bank_cfg_shadowed_erase_en_0_storage_err)
10330 );
10331
10332 // F[erase_en_1]: 1:1
10333 prim_subreg_shadow #(
10334 .DW (1),
10335 .SwAccess(prim_subreg_pkg::SwAccessRW),
10336 .RESVAL (1'h0),
10337 .Mubi (1'b0)
10338 ) u_mp_bank_cfg_shadowed_erase_en_1 (
10339 .clk_i (clk_i),
10340 .rst_ni (rst_ni),
10341 .rst_shadowed_ni (rst_shadowed_ni),
10342
10343 // from register interface
10344 .re (mp_bank_cfg_shadowed_re),
10345 .we (mp_bank_cfg_shadowed_gated_we),
10346 .wd (mp_bank_cfg_shadowed_erase_en_1_wd),
10347
10348 // from internal hardware
10349 .de (1'b0),
10350 .d ('0),
10351
10352 // to internal hardware
10353 .qe (),
10354 .q (reg2hw.mp_bank_cfg_shadowed[1].q),
10355 .ds (),
10356
10357 // to register interface (read)
10358 .qs (mp_bank_cfg_shadowed_erase_en_1_qs),
10359
10360 // Shadow register phase. Relevant for hwext only.
10361 .phase (),
10362
10363 // Shadow register error conditions
10364 .err_update (mp_bank_cfg_shadowed_erase_en_1_update_err),
10365 .err_storage (mp_bank_cfg_shadowed_erase_en_1_storage_err)
10366 );
10367
10368
10369 // R[op_status]: V(False)
10370 // F[done]: 0:0
10371 prim_subreg #(
10372 .DW (1),
10373 .SwAccess(prim_subreg_pkg::SwAccessRW),
10374 .RESVAL (1'h0),
10375 .Mubi (1'b0)
10376 ) u_op_status_done (
10377 .clk_i (clk_i),
10378 .rst_ni (rst_ni),
10379
10380 // from register interface
10381 .we (op_status_we),
10382 .wd (op_status_done_wd),
10383
10384 // from internal hardware
10385 .de (hw2reg.op_status.done.de),
10386 .d (hw2reg.op_status.done.d),
10387
10388 // to internal hardware
10389 .qe (),
10390 .q (),
10391 .ds (),
10392
10393 // to register interface (read)
10394 .qs (op_status_done_qs)
10395 );
10396
10397 // F[err]: 1:1
10398 prim_subreg #(
10399 .DW (1),
10400 .SwAccess(prim_subreg_pkg::SwAccessRW),
10401 .RESVAL (1'h0),
10402 .Mubi (1'b0)
10403 ) u_op_status_err (
10404 .clk_i (clk_i),
10405 .rst_ni (rst_ni),
10406
10407 // from register interface
10408 .we (op_status_we),
10409 .wd (op_status_err_wd),
10410
10411 // from internal hardware
10412 .de (hw2reg.op_status.err.de),
10413 .d (hw2reg.op_status.err.d),
10414
10415 // to internal hardware
10416 .qe (),
10417 .q (),
10418 .ds (),
10419
10420 // to register interface (read)
10421 .qs (op_status_err_qs)
10422 );
10423
10424
10425 // R[status]: V(False)
10426 // F[rd_full]: 0:0
10427 prim_subreg #(
10428 .DW (1),
10429 .SwAccess(prim_subreg_pkg::SwAccessRO),
10430 .RESVAL (1'h0),
10431 .Mubi (1'b0)
10432 ) u_status_rd_full (
10433 .clk_i (clk_i),
10434 .rst_ni (rst_ni),
10435
10436 // from register interface
10437 .we (1'b0),
10438 .wd ('0),
10439
10440 // from internal hardware
10441 .de (hw2reg.status.rd_full.de),
10442 .d (hw2reg.status.rd_full.d),
10443
10444 // to internal hardware
10445 .qe (),
10446 .q (),
10447 .ds (),
10448
10449 // to register interface (read)
10450 .qs (status_rd_full_qs)
10451 );
10452
10453 // F[rd_empty]: 1:1
10454 prim_subreg #(
10455 .DW (1),
10456 .SwAccess(prim_subreg_pkg::SwAccessRO),
10457 .RESVAL (1'h1),
10458 .Mubi (1'b0)
10459 ) u_status_rd_empty (
10460 .clk_i (clk_i),
10461 .rst_ni (rst_ni),
10462
10463 // from register interface
10464 .we (1'b0),
10465 .wd ('0),
10466
10467 // from internal hardware
10468 .de (hw2reg.status.rd_empty.de),
10469 .d (hw2reg.status.rd_empty.d),
10470
10471 // to internal hardware
10472 .qe (),
10473 .q (),
10474 .ds (),
10475
10476 // to register interface (read)
10477 .qs (status_rd_empty_qs)
10478 );
10479
10480 // F[prog_full]: 2:2
10481 prim_subreg #(
10482 .DW (1),
10483 .SwAccess(prim_subreg_pkg::SwAccessRO),
10484 .RESVAL (1'h0),
10485 .Mubi (1'b0)
10486 ) u_status_prog_full (
10487 .clk_i (clk_i),
10488 .rst_ni (rst_ni),
10489
10490 // from register interface
10491 .we (1'b0),
10492 .wd ('0),
10493
10494 // from internal hardware
10495 .de (hw2reg.status.prog_full.de),
10496 .d (hw2reg.status.prog_full.d),
10497
10498 // to internal hardware
10499 .qe (),
10500 .q (),
10501 .ds (),
10502
10503 // to register interface (read)
10504 .qs (status_prog_full_qs)
10505 );
10506
10507 // F[prog_empty]: 3:3
10508 prim_subreg #(
10509 .DW (1),
10510 .SwAccess(prim_subreg_pkg::SwAccessRO),
10511 .RESVAL (1'h1),
10512 .Mubi (1'b0)
10513 ) u_status_prog_empty (
10514 .clk_i (clk_i),
10515 .rst_ni (rst_ni),
10516
10517 // from register interface
10518 .we (1'b0),
10519 .wd ('0),
10520
10521 // from internal hardware
10522 .de (hw2reg.status.prog_empty.de),
10523 .d (hw2reg.status.prog_empty.d),
10524
10525 // to internal hardware
10526 .qe (),
10527 .q (),
10528 .ds (),
10529
10530 // to register interface (read)
10531 .qs (status_prog_empty_qs)
10532 );
10533
10534 // F[init_wip]: 4:4
10535 prim_subreg #(
10536 .DW (1),
10537 .SwAccess(prim_subreg_pkg::SwAccessRO),
10538 .RESVAL (1'h0),
10539 .Mubi (1'b0)
10540 ) u_status_init_wip (
10541 .clk_i (clk_i),
10542 .rst_ni (rst_ni),
10543
10544 // from register interface
10545 .we (1'b0),
10546 .wd ('0),
10547
10548 // from internal hardware
10549 .de (hw2reg.status.init_wip.de),
10550 .d (hw2reg.status.init_wip.d),
10551
10552 // to internal hardware
10553 .qe (),
10554 .q (),
10555 .ds (),
10556
10557 // to register interface (read)
10558 .qs (status_init_wip_qs)
10559 );
10560
10561 // F[initialized]: 5:5
10562 prim_subreg #(
10563 .DW (1),
10564 .SwAccess(prim_subreg_pkg::SwAccessRO),
10565 .RESVAL (1'h0),
10566 .Mubi (1'b0)
10567 ) u_status_initialized (
10568 .clk_i (clk_i),
10569 .rst_ni (rst_ni),
10570
10571 // from register interface
10572 .we (1'b0),
10573 .wd ('0),
10574
10575 // from internal hardware
10576 .de (hw2reg.status.initialized.de),
10577 .d (hw2reg.status.initialized.d),
10578
10579 // to internal hardware
10580 .qe (),
10581 .q (),
10582 .ds (),
10583
10584 // to register interface (read)
10585 .qs (status_initialized_qs)
10586 );
10587
10588
10589 // R[debug_state]: V(True)
10590 prim_subreg_ext #(
10591 .DW (11)
10592 ) u_debug_state (
10593 .re (debug_state_re),
10594 .we (1'b0),
10595 .wd ('0),
10596 .d (hw2reg.debug_state.d),
10597 .qre (),
10598 .qe (),
10599 .q (),
10600 .ds (),
10601 .qs (debug_state_qs)
10602 );
10603
10604
10605 // R[err_code]: V(False)
10606 // F[op_err]: 0:0
10607 prim_subreg #(
10608 .DW (1),
10609 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10610 .RESVAL (1'h0),
10611 .Mubi (1'b0)
10612 ) u_err_code_op_err (
10613 .clk_i (clk_i),
10614 .rst_ni (rst_ni),
10615
10616 // from register interface
10617 .we (err_code_we),
10618 .wd (err_code_op_err_wd),
10619
10620 // from internal hardware
10621 .de (hw2reg.err_code.op_err.de),
10622 .d (hw2reg.err_code.op_err.d),
10623
10624 // to internal hardware
10625 .qe (),
10626 .q (),
10627 .ds (),
10628
10629 // to register interface (read)
10630 .qs (err_code_op_err_qs)
10631 );
10632
10633 // F[mp_err]: 1:1
10634 prim_subreg #(
10635 .DW (1),
10636 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10637 .RESVAL (1'h0),
10638 .Mubi (1'b0)
10639 ) u_err_code_mp_err (
10640 .clk_i (clk_i),
10641 .rst_ni (rst_ni),
10642
10643 // from register interface
10644 .we (err_code_we),
10645 .wd (err_code_mp_err_wd),
10646
10647 // from internal hardware
10648 .de (hw2reg.err_code.mp_err.de),
10649 .d (hw2reg.err_code.mp_err.d),
10650
10651 // to internal hardware
10652 .qe (),
10653 .q (),
10654 .ds (),
10655
10656 // to register interface (read)
10657 .qs (err_code_mp_err_qs)
10658 );
10659
10660 // F[rd_err]: 2:2
10661 prim_subreg #(
10662 .DW (1),
10663 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10664 .RESVAL (1'h0),
10665 .Mubi (1'b0)
10666 ) u_err_code_rd_err (
10667 .clk_i (clk_i),
10668 .rst_ni (rst_ni),
10669
10670 // from register interface
10671 .we (err_code_we),
10672 .wd (err_code_rd_err_wd),
10673
10674 // from internal hardware
10675 .de (hw2reg.err_code.rd_err.de),
10676 .d (hw2reg.err_code.rd_err.d),
10677
10678 // to internal hardware
10679 .qe (),
10680 .q (),
10681 .ds (),
10682
10683 // to register interface (read)
10684 .qs (err_code_rd_err_qs)
10685 );
10686
10687 // F[prog_err]: 3:3
10688 prim_subreg #(
10689 .DW (1),
10690 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10691 .RESVAL (1'h0),
10692 .Mubi (1'b0)
10693 ) u_err_code_prog_err (
10694 .clk_i (clk_i),
10695 .rst_ni (rst_ni),
10696
10697 // from register interface
10698 .we (err_code_we),
10699 .wd (err_code_prog_err_wd),
10700
10701 // from internal hardware
10702 .de (hw2reg.err_code.prog_err.de),
10703 .d (hw2reg.err_code.prog_err.d),
10704
10705 // to internal hardware
10706 .qe (),
10707 .q (),
10708 .ds (),
10709
10710 // to register interface (read)
10711 .qs (err_code_prog_err_qs)
10712 );
10713
10714 // F[prog_win_err]: 4:4
10715 prim_subreg #(
10716 .DW (1),
10717 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10718 .RESVAL (1'h0),
10719 .Mubi (1'b0)
10720 ) u_err_code_prog_win_err (
10721 .clk_i (clk_i),
10722 .rst_ni (rst_ni),
10723
10724 // from register interface
10725 .we (err_code_we),
10726 .wd (err_code_prog_win_err_wd),
10727
10728 // from internal hardware
10729 .de (hw2reg.err_code.prog_win_err.de),
10730 .d (hw2reg.err_code.prog_win_err.d),
10731
10732 // to internal hardware
10733 .qe (),
10734 .q (),
10735 .ds (),
10736
10737 // to register interface (read)
10738 .qs (err_code_prog_win_err_qs)
10739 );
10740
10741 // F[prog_type_err]: 5:5
10742 prim_subreg #(
10743 .DW (1),
10744 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10745 .RESVAL (1'h0),
10746 .Mubi (1'b0)
10747 ) u_err_code_prog_type_err (
10748 .clk_i (clk_i),
10749 .rst_ni (rst_ni),
10750
10751 // from register interface
10752 .we (err_code_we),
10753 .wd (err_code_prog_type_err_wd),
10754
10755 // from internal hardware
10756 .de (hw2reg.err_code.prog_type_err.de),
10757 .d (hw2reg.err_code.prog_type_err.d),
10758
10759 // to internal hardware
10760 .qe (),
10761 .q (),
10762 .ds (),
10763
10764 // to register interface (read)
10765 .qs (err_code_prog_type_err_qs)
10766 );
10767
10768 // F[update_err]: 6:6
10769 prim_subreg #(
10770 .DW (1),
10771 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10772 .RESVAL (1'h0),
10773 .Mubi (1'b0)
10774 ) u_err_code_update_err (
10775 .clk_i (clk_i),
10776 .rst_ni (rst_ni),
10777
10778 // from register interface
10779 .we (err_code_we),
10780 .wd (err_code_update_err_wd),
10781
10782 // from internal hardware
10783 .de (hw2reg.err_code.update_err.de),
10784 .d (hw2reg.err_code.update_err.d),
10785
10786 // to internal hardware
10787 .qe (),
10788 .q (),
10789 .ds (),
10790
10791 // to register interface (read)
10792 .qs (err_code_update_err_qs)
10793 );
10794
10795 // F[macro_err]: 7:7
10796 prim_subreg #(
10797 .DW (1),
10798 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10799 .RESVAL (1'h0),
10800 .Mubi (1'b0)
10801 ) u_err_code_macro_err (
10802 .clk_i (clk_i),
10803 .rst_ni (rst_ni),
10804
10805 // from register interface
10806 .we (err_code_we),
10807 .wd (err_code_macro_err_wd),
10808
10809 // from internal hardware
10810 .de (hw2reg.err_code.macro_err.de),
10811 .d (hw2reg.err_code.macro_err.d),
10812
10813 // to internal hardware
10814 .qe (),
10815 .q (),
10816 .ds (),
10817
10818 // to register interface (read)
10819 .qs (err_code_macro_err_qs)
10820 );
10821
10822
10823 // R[std_fault_status]: V(False)
10824 // F[reg_intg_err]: 0:0
10825 prim_subreg #(
10826 .DW (1),
10827 .SwAccess(prim_subreg_pkg::SwAccessRO),
10828 .RESVAL (1'h0),
10829 .Mubi (1'b0)
10830 ) u_std_fault_status_reg_intg_err (
10831 .clk_i (clk_i),
10832 .rst_ni (rst_ni),
10833
10834 // from register interface
10835 .we (1'b0),
10836 .wd ('0),
10837
10838 // from internal hardware
10839 .de (hw2reg.std_fault_status.reg_intg_err.de),
10840 .d (hw2reg.std_fault_status.reg_intg_err.d),
10841
10842 // to internal hardware
10843 .qe (),
10844 .q (reg2hw.std_fault_status.reg_intg_err.q),
10845 .ds (),
10846
10847 // to register interface (read)
10848 .qs (std_fault_status_reg_intg_err_qs)
10849 );
10850
10851 // F[prog_intg_err]: 1:1
10852 prim_subreg #(
10853 .DW (1),
10854 .SwAccess(prim_subreg_pkg::SwAccessRO),
10855 .RESVAL (1'h0),
10856 .Mubi (1'b0)
10857 ) u_std_fault_status_prog_intg_err (
10858 .clk_i (clk_i),
10859 .rst_ni (rst_ni),
10860
10861 // from register interface
10862 .we (1'b0),
10863 .wd ('0),
10864
10865 // from internal hardware
10866 .de (hw2reg.std_fault_status.prog_intg_err.de),
10867 .d (hw2reg.std_fault_status.prog_intg_err.d),
10868
10869 // to internal hardware
10870 .qe (),
10871 .q (reg2hw.std_fault_status.prog_intg_err.q),
10872 .ds (),
10873
10874 // to register interface (read)
10875 .qs (std_fault_status_prog_intg_err_qs)
10876 );
10877
10878 // F[lcmgr_err]: 2:2
10879 prim_subreg #(
10880 .DW (1),
10881 .SwAccess(prim_subreg_pkg::SwAccessRO),
10882 .RESVAL (1'h0),
10883 .Mubi (1'b0)
10884 ) u_std_fault_status_lcmgr_err (
10885 .clk_i (clk_i),
10886 .rst_ni (rst_ni),
10887
10888 // from register interface
10889 .we (1'b0),
10890 .wd ('0),
10891
10892 // from internal hardware
10893 .de (hw2reg.std_fault_status.lcmgr_err.de),
10894 .d (hw2reg.std_fault_status.lcmgr_err.d),
10895
10896 // to internal hardware
10897 .qe (),
10898 .q (reg2hw.std_fault_status.lcmgr_err.q),
10899 .ds (),
10900
10901 // to register interface (read)
10902 .qs (std_fault_status_lcmgr_err_qs)
10903 );
10904
10905 // F[lcmgr_intg_err]: 3:3
10906 prim_subreg #(
10907 .DW (1),
10908 .SwAccess(prim_subreg_pkg::SwAccessRO),
10909 .RESVAL (1'h0),
10910 .Mubi (1'b0)
10911 ) u_std_fault_status_lcmgr_intg_err (
10912 .clk_i (clk_i),
10913 .rst_ni (rst_ni),
10914
10915 // from register interface
10916 .we (1'b0),
10917 .wd ('0),
10918
10919 // from internal hardware
10920 .de (hw2reg.std_fault_status.lcmgr_intg_err.de),
10921 .d (hw2reg.std_fault_status.lcmgr_intg_err.d),
10922
10923 // to internal hardware
10924 .qe (),
10925 .q (reg2hw.std_fault_status.lcmgr_intg_err.q),
10926 .ds (),
10927
10928 // to register interface (read)
10929 .qs (std_fault_status_lcmgr_intg_err_qs)
10930 );
10931
10932 // F[arb_fsm_err]: 4:4
10933 prim_subreg #(
10934 .DW (1),
10935 .SwAccess(prim_subreg_pkg::SwAccessRO),
10936 .RESVAL (1'h0),
10937 .Mubi (1'b0)
10938 ) u_std_fault_status_arb_fsm_err (
10939 .clk_i (clk_i),
10940 .rst_ni (rst_ni),
10941
10942 // from register interface
10943 .we (1'b0),
10944 .wd ('0),
10945
10946 // from internal hardware
10947 .de (hw2reg.std_fault_status.arb_fsm_err.de),
10948 .d (hw2reg.std_fault_status.arb_fsm_err.d),
10949
10950 // to internal hardware
10951 .qe (),
10952 .q (reg2hw.std_fault_status.arb_fsm_err.q),
10953 .ds (),
10954
10955 // to register interface (read)
10956 .qs (std_fault_status_arb_fsm_err_qs)
10957 );
10958
10959 // F[storage_err]: 5:5
10960 prim_subreg #(
10961 .DW (1),
10962 .SwAccess(prim_subreg_pkg::SwAccessRO),
10963 .RESVAL (1'h0),
10964 .Mubi (1'b0)
10965 ) u_std_fault_status_storage_err (
10966 .clk_i (clk_i),
10967 .rst_ni (rst_ni),
10968
10969 // from register interface
10970 .we (1'b0),
10971 .wd ('0),
10972
10973 // from internal hardware
10974 .de (hw2reg.std_fault_status.storage_err.de),
10975 .d (hw2reg.std_fault_status.storage_err.d),
10976
10977 // to internal hardware
10978 .qe (),
10979 .q (reg2hw.std_fault_status.storage_err.q),
10980 .ds (),
10981
10982 // to register interface (read)
10983 .qs (std_fault_status_storage_err_qs)
10984 );
10985
10986 // F[phy_fsm_err]: 6:6
10987 prim_subreg #(
10988 .DW (1),
10989 .SwAccess(prim_subreg_pkg::SwAccessRO),
10990 .RESVAL (1'h0),
10991 .Mubi (1'b0)
10992 ) u_std_fault_status_phy_fsm_err (
10993 .clk_i (clk_i),
10994 .rst_ni (rst_ni),
10995
10996 // from register interface
10997 .we (1'b0),
10998 .wd ('0),
10999
11000 // from internal hardware
11001 .de (hw2reg.std_fault_status.phy_fsm_err.de),
11002 .d (hw2reg.std_fault_status.phy_fsm_err.d),
11003
11004 // to internal hardware
11005 .qe (),
11006 .q (reg2hw.std_fault_status.phy_fsm_err.q),
11007 .ds (),
11008
11009 // to register interface (read)
11010 .qs (std_fault_status_phy_fsm_err_qs)
11011 );
11012
11013 // F[ctrl_cnt_err]: 7:7
11014 prim_subreg #(
11015 .DW (1),
11016 .SwAccess(prim_subreg_pkg::SwAccessRO),
11017 .RESVAL (1'h0),
11018 .Mubi (1'b0)
11019 ) u_std_fault_status_ctrl_cnt_err (
11020 .clk_i (clk_i),
11021 .rst_ni (rst_ni),
11022
11023 // from register interface
11024 .we (1'b0),
11025 .wd ('0),
11026
11027 // from internal hardware
11028 .de (hw2reg.std_fault_status.ctrl_cnt_err.de),
11029 .d (hw2reg.std_fault_status.ctrl_cnt_err.d),
11030
11031 // to internal hardware
11032 .qe (),
11033 .q (reg2hw.std_fault_status.ctrl_cnt_err.q),
11034 .ds (),
11035
11036 // to register interface (read)
11037 .qs (std_fault_status_ctrl_cnt_err_qs)
11038 );
11039
11040 // F[fifo_err]: 8:8
11041 prim_subreg #(
11042 .DW (1),
11043 .SwAccess(prim_subreg_pkg::SwAccessRO),
11044 .RESVAL (1'h0),
11045 .Mubi (1'b0)
11046 ) u_std_fault_status_fifo_err (
11047 .clk_i (clk_i),
11048 .rst_ni (rst_ni),
11049
11050 // from register interface
11051 .we (1'b0),
11052 .wd ('0),
11053
11054 // from internal hardware
11055 .de (hw2reg.std_fault_status.fifo_err.de),
11056 .d (hw2reg.std_fault_status.fifo_err.d),
11057
11058 // to internal hardware
11059 .qe (),
11060 .q (reg2hw.std_fault_status.fifo_err.q),
11061 .ds (),
11062
11063 // to register interface (read)
11064 .qs (std_fault_status_fifo_err_qs)
11065 );
11066
11067
11068 // R[fault_status]: V(False)
11069 // F[op_err]: 0:0
11070 prim_subreg #(
11071 .DW (1),
11072 .SwAccess(prim_subreg_pkg::SwAccessRO),
11073 .RESVAL (1'h0),
11074 .Mubi (1'b0)
11075 ) u_fault_status_op_err (
11076 .clk_i (clk_i),
11077 .rst_ni (rst_ni),
11078
11079 // from register interface
11080 .we (1'b0),
11081 .wd ('0),
11082
11083 // from internal hardware
11084 .de (hw2reg.fault_status.op_err.de),
11085 .d (hw2reg.fault_status.op_err.d),
11086
11087 // to internal hardware
11088 .qe (),
11089 .q (reg2hw.fault_status.op_err.q),
11090 .ds (),
11091
11092 // to register interface (read)
11093 .qs (fault_status_op_err_qs)
11094 );
11095
11096 // F[mp_err]: 1:1
11097 prim_subreg #(
11098 .DW (1),
11099 .SwAccess(prim_subreg_pkg::SwAccessRO),
11100 .RESVAL (1'h0),
11101 .Mubi (1'b0)
11102 ) u_fault_status_mp_err (
11103 .clk_i (clk_i),
11104 .rst_ni (rst_ni),
11105
11106 // from register interface
11107 .we (1'b0),
11108 .wd ('0),
11109
11110 // from internal hardware
11111 .de (hw2reg.fault_status.mp_err.de),
11112 .d (hw2reg.fault_status.mp_err.d),
11113
11114 // to internal hardware
11115 .qe (),
11116 .q (reg2hw.fault_status.mp_err.q),
11117 .ds (),
11118
11119 // to register interface (read)
11120 .qs (fault_status_mp_err_qs)
11121 );
11122
11123 // F[rd_err]: 2:2
11124 prim_subreg #(
11125 .DW (1),
11126 .SwAccess(prim_subreg_pkg::SwAccessRO),
11127 .RESVAL (1'h0),
11128 .Mubi (1'b0)
11129 ) u_fault_status_rd_err (
11130 .clk_i (clk_i),
11131 .rst_ni (rst_ni),
11132
11133 // from register interface
11134 .we (1'b0),
11135 .wd ('0),
11136
11137 // from internal hardware
11138 .de (hw2reg.fault_status.rd_err.de),
11139 .d (hw2reg.fault_status.rd_err.d),
11140
11141 // to internal hardware
11142 .qe (),
11143 .q (reg2hw.fault_status.rd_err.q),
11144 .ds (),
11145
11146 // to register interface (read)
11147 .qs (fault_status_rd_err_qs)
11148 );
11149
11150 // F[prog_err]: 3:3
11151 prim_subreg #(
11152 .DW (1),
11153 .SwAccess(prim_subreg_pkg::SwAccessRO),
11154 .RESVAL (1'h0),
11155 .Mubi (1'b0)
11156 ) u_fault_status_prog_err (
11157 .clk_i (clk_i),
11158 .rst_ni (rst_ni),
11159
11160 // from register interface
11161 .we (1'b0),
11162 .wd ('0),
11163
11164 // from internal hardware
11165 .de (hw2reg.fault_status.prog_err.de),
11166 .d (hw2reg.fault_status.prog_err.d),
11167
11168 // to internal hardware
11169 .qe (),
11170 .q (reg2hw.fault_status.prog_err.q),
11171 .ds (),
11172
11173 // to register interface (read)
11174 .qs (fault_status_prog_err_qs)
11175 );
11176
11177 // F[prog_win_err]: 4:4
11178 prim_subreg #(
11179 .DW (1),
11180 .SwAccess(prim_subreg_pkg::SwAccessRO),
11181 .RESVAL (1'h0),
11182 .Mubi (1'b0)
11183 ) u_fault_status_prog_win_err (
11184 .clk_i (clk_i),
11185 .rst_ni (rst_ni),
11186
11187 // from register interface
11188 .we (1'b0),
11189 .wd ('0),
11190
11191 // from internal hardware
11192 .de (hw2reg.fault_status.prog_win_err.de),
11193 .d (hw2reg.fault_status.prog_win_err.d),
11194
11195 // to internal hardware
11196 .qe (),
11197 .q (reg2hw.fault_status.prog_win_err.q),
11198 .ds (),
11199
11200 // to register interface (read)
11201 .qs (fault_status_prog_win_err_qs)
11202 );
11203
11204 // F[prog_type_err]: 5:5
11205 prim_subreg #(
11206 .DW (1),
11207 .SwAccess(prim_subreg_pkg::SwAccessRO),
11208 .RESVAL (1'h0),
11209 .Mubi (1'b0)
11210 ) u_fault_status_prog_type_err (
11211 .clk_i (clk_i),
11212 .rst_ni (rst_ni),
11213
11214 // from register interface
11215 .we (1'b0),
11216 .wd ('0),
11217
11218 // from internal hardware
11219 .de (hw2reg.fault_status.prog_type_err.de),
11220 .d (hw2reg.fault_status.prog_type_err.d),
11221
11222 // to internal hardware
11223 .qe (),
11224 .q (reg2hw.fault_status.prog_type_err.q),
11225 .ds (),
11226
11227 // to register interface (read)
11228 .qs (fault_status_prog_type_err_qs)
11229 );
11230
11231 // F[seed_err]: 6:6
11232 prim_subreg #(
11233 .DW (1),
11234 .SwAccess(prim_subreg_pkg::SwAccessRO),
11235 .RESVAL (1'h0),
11236 .Mubi (1'b0)
11237 ) u_fault_status_seed_err (
11238 .clk_i (clk_i),
11239 .rst_ni (rst_ni),
11240
11241 // from register interface
11242 .we (1'b0),
11243 .wd ('0),
11244
11245 // from internal hardware
11246 .de (hw2reg.fault_status.seed_err.de),
11247 .d (hw2reg.fault_status.seed_err.d),
11248
11249 // to internal hardware
11250 .qe (),
11251 .q (reg2hw.fault_status.seed_err.q),
11252 .ds (),
11253
11254 // to register interface (read)
11255 .qs (fault_status_seed_err_qs)
11256 );
11257
11258 // F[phy_relbl_err]: 7:7
11259 prim_subreg #(
11260 .DW (1),
11261 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11262 .RESVAL (1'h0),
11263 .Mubi (1'b0)
11264 ) u_fault_status_phy_relbl_err (
11265 .clk_i (clk_i),
11266 .rst_ni (rst_ni),
11267
11268 // from register interface
11269 .we (fault_status_we),
11270 .wd (fault_status_phy_relbl_err_wd),
11271
11272 // from internal hardware
11273 .de (hw2reg.fault_status.phy_relbl_err.de),
11274 .d (hw2reg.fault_status.phy_relbl_err.d),
11275
11276 // to internal hardware
11277 .qe (),
11278 .q (reg2hw.fault_status.phy_relbl_err.q),
11279 .ds (),
11280
11281 // to register interface (read)
11282 .qs (fault_status_phy_relbl_err_qs)
11283 );
11284
11285 // F[phy_storage_err]: 8:8
11286 prim_subreg #(
11287 .DW (1),
11288 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11289 .RESVAL (1'h0),
11290 .Mubi (1'b0)
11291 ) u_fault_status_phy_storage_err (
11292 .clk_i (clk_i),
11293 .rst_ni (rst_ni),
11294
11295 // from register interface
11296 .we (fault_status_we),
11297 .wd (fault_status_phy_storage_err_wd),
11298
11299 // from internal hardware
11300 .de (hw2reg.fault_status.phy_storage_err.de),
11301 .d (hw2reg.fault_status.phy_storage_err.d),
11302
11303 // to internal hardware
11304 .qe (),
11305 .q (reg2hw.fault_status.phy_storage_err.q),
11306 .ds (),
11307
11308 // to register interface (read)
11309 .qs (fault_status_phy_storage_err_qs)
11310 );
11311
11312 // F[spurious_ack]: 9:9
11313 prim_subreg #(
11314 .DW (1),
11315 .SwAccess(prim_subreg_pkg::SwAccessRO),
11316 .RESVAL (1'h0),
11317 .Mubi (1'b0)
11318 ) u_fault_status_spurious_ack (
11319 .clk_i (clk_i),
11320 .rst_ni (rst_ni),
11321
11322 // from register interface
11323 .we (1'b0),
11324 .wd ('0),
11325
11326 // from internal hardware
11327 .de (hw2reg.fault_status.spurious_ack.de),
11328 .d (hw2reg.fault_status.spurious_ack.d),
11329
11330 // to internal hardware
11331 .qe (),
11332 .q (reg2hw.fault_status.spurious_ack.q),
11333 .ds (),
11334
11335 // to register interface (read)
11336 .qs (fault_status_spurious_ack_qs)
11337 );
11338
11339 // F[arb_err]: 10:10
11340 prim_subreg #(
11341 .DW (1),
11342 .SwAccess(prim_subreg_pkg::SwAccessRO),
11343 .RESVAL (1'h0),
11344 .Mubi (1'b0)
11345 ) u_fault_status_arb_err (
11346 .clk_i (clk_i),
11347 .rst_ni (rst_ni),
11348
11349 // from register interface
11350 .we (1'b0),
11351 .wd ('0),
11352
11353 // from internal hardware
11354 .de (hw2reg.fault_status.arb_err.de),
11355 .d (hw2reg.fault_status.arb_err.d),
11356
11357 // to internal hardware
11358 .qe (),
11359 .q (reg2hw.fault_status.arb_err.q),
11360 .ds (),
11361
11362 // to register interface (read)
11363 .qs (fault_status_arb_err_qs)
11364 );
11365
11366 // F[host_gnt_err]: 11:11
11367 prim_subreg #(
11368 .DW (1),
11369 .SwAccess(prim_subreg_pkg::SwAccessRO),
11370 .RESVAL (1'h0),
11371 .Mubi (1'b0)
11372 ) u_fault_status_host_gnt_err (
11373 .clk_i (clk_i),
11374 .rst_ni (rst_ni),
11375
11376 // from register interface
11377 .we (1'b0),
11378 .wd ('0),
11379
11380 // from internal hardware
11381 .de (hw2reg.fault_status.host_gnt_err.de),
11382 .d (hw2reg.fault_status.host_gnt_err.d),
11383
11384 // to internal hardware
11385 .qe (),
11386 .q (reg2hw.fault_status.host_gnt_err.q),
11387 .ds (),
11388
11389 // to register interface (read)
11390 .qs (fault_status_host_gnt_err_qs)
11391 );
11392
11393
11394 // R[err_addr]: V(False)
11395 prim_subreg #(
11396 .DW (20),
11397 .SwAccess(prim_subreg_pkg::SwAccessRO),
11398 .RESVAL (20'h0),
11399 .Mubi (1'b0)
11400 ) u_err_addr (
11401 .clk_i (clk_i),
11402 .rst_ni (rst_ni),
11403
11404 // from register interface
11405 .we (1'b0),
11406 .wd ('0),
11407
11408 // from internal hardware
11409 .de (hw2reg.err_addr.de),
11410 .d (hw2reg.err_addr.d),
11411
11412 // to internal hardware
11413 .qe (),
11414 .q (),
11415 .ds (),
11416
11417 // to register interface (read)
11418 .qs (err_addr_qs)
11419 );
11420
11421
11422 // Subregister 0 of Multireg ecc_single_err_cnt
11423 // R[ecc_single_err_cnt]: V(False)
11424 // F[ecc_single_err_cnt_0]: 7:0
11425 prim_subreg #(
11426 .DW (8),
11427 .SwAccess(prim_subreg_pkg::SwAccessRW),
11428 .RESVAL (8'h0),
11429 .Mubi (1'b0)
11430 ) u_ecc_single_err_cnt_ecc_single_err_cnt_0 (
11431 .clk_i (clk_i),
11432 .rst_ni (rst_ni),
11433
11434 // from register interface
11435 .we (ecc_single_err_cnt_we),
11436 .wd (ecc_single_err_cnt_ecc_single_err_cnt_0_wd),
11437
11438 // from internal hardware
11439 .de (hw2reg.ecc_single_err_cnt[0].de),
11440 .d (hw2reg.ecc_single_err_cnt[0].d),
11441
11442 // to internal hardware
11443 .qe (),
11444 .q (reg2hw.ecc_single_err_cnt[0].q),
11445 .ds (),
11446
11447 // to register interface (read)
11448 .qs (ecc_single_err_cnt_ecc_single_err_cnt_0_qs)
11449 );
11450
11451 // F[ecc_single_err_cnt_1]: 15:8
11452 prim_subreg #(
11453 .DW (8),
11454 .SwAccess(prim_subreg_pkg::SwAccessRW),
11455 .RESVAL (8'h0),
11456 .Mubi (1'b0)
11457 ) u_ecc_single_err_cnt_ecc_single_err_cnt_1 (
11458 .clk_i (clk_i),
11459 .rst_ni (rst_ni),
11460
11461 // from register interface
11462 .we (ecc_single_err_cnt_we),
11463 .wd (ecc_single_err_cnt_ecc_single_err_cnt_1_wd),
11464
11465 // from internal hardware
11466 .de (hw2reg.ecc_single_err_cnt[1].de),
11467 .d (hw2reg.ecc_single_err_cnt[1].d),
11468
11469 // to internal hardware
11470 .qe (),
11471 .q (reg2hw.ecc_single_err_cnt[1].q),
11472 .ds (),
11473
11474 // to register interface (read)
11475 .qs (ecc_single_err_cnt_ecc_single_err_cnt_1_qs)
11476 );
11477
11478
11479 // Subregister 0 of Multireg ecc_single_err_addr
11480 // R[ecc_single_err_addr_0]: V(False)
11481 prim_subreg #(
11482 .DW (20),
11483 .SwAccess(prim_subreg_pkg::SwAccessRO),
11484 .RESVAL (20'h0),
11485 .Mubi (1'b0)
11486 ) u_ecc_single_err_addr_0 (
11487 .clk_i (clk_i),
11488 .rst_ni (rst_ni),
11489
11490 // from register interface
11491 .we (1'b0),
11492 .wd ('0),
11493
11494 // from internal hardware
11495 .de (hw2reg.ecc_single_err_addr[0].de),
11496 .d (hw2reg.ecc_single_err_addr[0].d),
11497
11498 // to internal hardware
11499 .qe (),
11500 .q (),
11501 .ds (),
11502
11503 // to register interface (read)
11504 .qs (ecc_single_err_addr_0_qs)
11505 );
11506
11507
11508 // Subregister 1 of Multireg ecc_single_err_addr
11509 // R[ecc_single_err_addr_1]: V(False)
11510 prim_subreg #(
11511 .DW (20),
11512 .SwAccess(prim_subreg_pkg::SwAccessRO),
11513 .RESVAL (20'h0),
11514 .Mubi (1'b0)
11515 ) u_ecc_single_err_addr_1 (
11516 .clk_i (clk_i),
11517 .rst_ni (rst_ni),
11518
11519 // from register interface
11520 .we (1'b0),
11521 .wd ('0),
11522
11523 // from internal hardware
11524 .de (hw2reg.ecc_single_err_addr[1].de),
11525 .d (hw2reg.ecc_single_err_addr[1].d),
11526
11527 // to internal hardware
11528 .qe (),
11529 .q (),
11530 .ds (),
11531
11532 // to register interface (read)
11533 .qs (ecc_single_err_addr_1_qs)
11534 );
11535
11536
11537 // R[phy_alert_cfg]: V(False)
11538 // F[alert_ack]: 0:0
11539 prim_subreg #(
11540 .DW (1),
11541 .SwAccess(prim_subreg_pkg::SwAccessRW),
11542 .RESVAL (1'h0),
11543 .Mubi (1'b0)
11544 ) u_phy_alert_cfg_alert_ack (
11545 .clk_i (clk_i),
11546 .rst_ni (rst_ni),
11547
11548 // from register interface
11549 .we (phy_alert_cfg_we),
11550 .wd (phy_alert_cfg_alert_ack_wd),
11551
11552 // from internal hardware
11553 .de (1'b0),
11554 .d ('0),
11555
11556 // to internal hardware
11557 .qe (),
11558 .q (reg2hw.phy_alert_cfg.alert_ack.q),
11559 .ds (),
11560
11561 // to register interface (read)
11562 .qs (phy_alert_cfg_alert_ack_qs)
11563 );
11564
11565 // F[alert_trig]: 1:1
11566 prim_subreg #(
11567 .DW (1),
11568 .SwAccess(prim_subreg_pkg::SwAccessRW),
11569 .RESVAL (1'h0),
11570 .Mubi (1'b0)
11571 ) u_phy_alert_cfg_alert_trig (
11572 .clk_i (clk_i),
11573 .rst_ni (rst_ni),
11574
11575 // from register interface
11576 .we (phy_alert_cfg_we),
11577 .wd (phy_alert_cfg_alert_trig_wd),
11578
11579 // from internal hardware
11580 .de (1'b0),
11581 .d ('0),
11582
11583 // to internal hardware
11584 .qe (),
11585 .q (reg2hw.phy_alert_cfg.alert_trig.q),
11586 .ds (),
11587
11588 // to register interface (read)
11589 .qs (phy_alert_cfg_alert_trig_qs)
11590 );
11591
11592
11593 // R[phy_status]: V(False)
11594 // F[init_wip]: 0:0
11595 prim_subreg #(
11596 .DW (1),
11597 .SwAccess(prim_subreg_pkg::SwAccessRO),
11598 .RESVAL (1'h0),
11599 .Mubi (1'b0)
11600 ) u_phy_status_init_wip (
11601 .clk_i (clk_i),
11602 .rst_ni (rst_ni),
11603
11604 // from register interface
11605 .we (1'b0),
11606 .wd ('0),
11607
11608 // from internal hardware
11609 .de (hw2reg.phy_status.init_wip.de),
11610 .d (hw2reg.phy_status.init_wip.d),
11611
11612 // to internal hardware
11613 .qe (),
11614 .q (),
11615 .ds (),
11616
11617 // to register interface (read)
11618 .qs (phy_status_init_wip_qs)
11619 );
11620
11621 // F[prog_normal_avail]: 1:1
11622 prim_subreg #(
11623 .DW (1),
11624 .SwAccess(prim_subreg_pkg::SwAccessRO),
11625 .RESVAL (1'h1),
11626 .Mubi (1'b0)
11627 ) u_phy_status_prog_normal_avail (
11628 .clk_i (clk_i),
11629 .rst_ni (rst_ni),
11630
11631 // from register interface
11632 .we (1'b0),
11633 .wd ('0),
11634
11635 // from internal hardware
11636 .de (hw2reg.phy_status.prog_normal_avail.de),
11637 .d (hw2reg.phy_status.prog_normal_avail.d),
11638
11639 // to internal hardware
11640 .qe (),
11641 .q (),
11642 .ds (),
11643
11644 // to register interface (read)
11645 .qs (phy_status_prog_normal_avail_qs)
11646 );
11647
11648 // F[prog_repair_avail]: 2:2
11649 prim_subreg #(
11650 .DW (1),
11651 .SwAccess(prim_subreg_pkg::SwAccessRO),
11652 .RESVAL (1'h1),
11653 .Mubi (1'b0)
11654 ) u_phy_status_prog_repair_avail (
11655 .clk_i (clk_i),
11656 .rst_ni (rst_ni),
11657
11658 // from register interface
11659 .we (1'b0),
11660 .wd ('0),
11661
11662 // from internal hardware
11663 .de (hw2reg.phy_status.prog_repair_avail.de),
11664 .d (hw2reg.phy_status.prog_repair_avail.d),
11665
11666 // to internal hardware
11667 .qe (),
11668 .q (),
11669 .ds (),
11670
11671 // to register interface (read)
11672 .qs (phy_status_prog_repair_avail_qs)
11673 );
11674
11675
11676 // R[scratch]: V(False)
11677 prim_subreg #(
11678 .DW (32),
11679 .SwAccess(prim_subreg_pkg::SwAccessRW),
11680 .RESVAL (32'h0),
11681 .Mubi (1'b0)
11682 ) u_scratch (
11683 .clk_i (clk_i),
11684 .rst_ni (rst_ni),
11685
11686 // from register interface
11687 .we (scratch_we),
11688 .wd (scratch_wd),
11689
11690 // from internal hardware
11691 .de (1'b0),
11692 .d ('0),
11693
11694 // to internal hardware
11695 .qe (),
11696 .q (reg2hw.scratch.q),
11697 .ds (),
11698
11699 // to register interface (read)
11700 .qs (scratch_qs)
11701 );
11702
11703
11704 // R[fifo_lvl]: V(False)
11705 // F[prog]: 4:0
11706 prim_subreg #(
11707 .DW (5),
11708 .SwAccess(prim_subreg_pkg::SwAccessRW),
11709 .RESVAL (5'hf),
11710 .Mubi (1'b0)
11711 ) u_fifo_lvl_prog (
11712 .clk_i (clk_i),
11713 .rst_ni (rst_ni),
11714
11715 // from register interface
11716 .we (fifo_lvl_we),
11717 .wd (fifo_lvl_prog_wd),
11718
11719 // from internal hardware
11720 .de (1'b0),
11721 .d ('0),
11722
11723 // to internal hardware
11724 .qe (),
11725 .q (reg2hw.fifo_lvl.prog.q),
11726 .ds (),
11727
11728 // to register interface (read)
11729 .qs (fifo_lvl_prog_qs)
11730 );
11731
11732 // F[rd]: 12:8
11733 prim_subreg #(
11734 .DW (5),
11735 .SwAccess(prim_subreg_pkg::SwAccessRW),
11736 .RESVAL (5'hf),
11737 .Mubi (1'b0)
11738 ) u_fifo_lvl_rd (
11739 .clk_i (clk_i),
11740 .rst_ni (rst_ni),
11741
11742 // from register interface
11743 .we (fifo_lvl_we),
11744 .wd (fifo_lvl_rd_wd),
11745
11746 // from internal hardware
11747 .de (1'b0),
11748 .d ('0),
11749
11750 // to internal hardware
11751 .qe (),
11752 .q (reg2hw.fifo_lvl.rd.q),
11753 .ds (),
11754
11755 // to register interface (read)
11756 .qs (fifo_lvl_rd_qs)
11757 );
11758
11759
11760 // R[fifo_rst]: V(False)
11761 prim_subreg #(
11762 .DW (1),
11763 .SwAccess(prim_subreg_pkg::SwAccessRW),
11764 .RESVAL (1'h0),
11765 .Mubi (1'b0)
11766 ) u_fifo_rst (
11767 .clk_i (clk_i),
11768 .rst_ni (rst_ni),
11769
11770 // from register interface
11771 .we (fifo_rst_we),
11772 .wd (fifo_rst_wd),
11773
11774 // from internal hardware
11775 .de (1'b0),
11776 .d ('0),
11777
11778 // to internal hardware
11779 .qe (),
11780 .q (reg2hw.fifo_rst.q),
11781 .ds (),
11782
11783 // to register interface (read)
11784 .qs (fifo_rst_qs)
11785 );
11786
11787
11788 // R[curr_fifo_lvl]: V(True)
11789 // F[prog]: 4:0
11790 prim_subreg_ext #(
11791 .DW (5)
11792 ) u_curr_fifo_lvl_prog (
11793 .re (curr_fifo_lvl_re),
11794 .we (1'b0),
11795 .wd ('0),
11796 .d (hw2reg.curr_fifo_lvl.prog.d),
11797 .qre (),
11798 .qe (),
11799 .q (),
11800 .ds (),
11801 .qs (curr_fifo_lvl_prog_qs)
11802 );
11803
11804 // F[rd]: 12:8
11805 prim_subreg_ext #(
11806 .DW (5)
11807 ) u_curr_fifo_lvl_rd (
11808 .re (curr_fifo_lvl_re),
11809 .we (1'b0),
11810 .wd ('0),
11811 .d (hw2reg.curr_fifo_lvl.rd.d),
11812 .qre (),
11813 .qe (),
11814 .q (),
11815 .ds (),
11816 .qs (curr_fifo_lvl_rd_qs)
11817 );
11818
11819
11820
11821 logic [107:0] addr_hit;
11822 always_comb begin
11823 1/1 addr_hit = '0;
Tests: T1 T2 T3
11824 1/1 addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
Tests: T1 T2 T3
11825 1/1 addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
11826 1/1 addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
Tests: T1 T2 T3
11827 1/1 addr_hit[ 3] = (reg_addr == FLASH_CTRL_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
11828 1/1 addr_hit[ 4] = (reg_addr == FLASH_CTRL_DIS_OFFSET);
Tests: T1 T2 T3
11829 1/1 addr_hit[ 5] = (reg_addr == FLASH_CTRL_EXEC_OFFSET);
Tests: T1 T2 T3
11830 1/1 addr_hit[ 6] = (reg_addr == FLASH_CTRL_INIT_OFFSET);
Tests: T1 T2 T3
11831 1/1 addr_hit[ 7] = (reg_addr == FLASH_CTRL_CTRL_REGWEN_OFFSET);
Tests: T1 T2 T3
11832 1/1 addr_hit[ 8] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
Tests: T1 T2 T3
11833 1/1 addr_hit[ 9] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
Tests: T1 T2 T3
11834 1/1 addr_hit[ 10] = (reg_addr == FLASH_CTRL_PROG_TYPE_EN_OFFSET);
Tests: T1 T2 T3
11835 1/1 addr_hit[ 11] = (reg_addr == FLASH_CTRL_ERASE_SUSPEND_OFFSET);
Tests: T1 T2 T3
11836 1/1 addr_hit[ 12] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_0_OFFSET);
Tests: T1 T2 T3
11837 1/1 addr_hit[ 13] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_1_OFFSET);
Tests: T1 T2 T3
11838 1/1 addr_hit[ 14] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_2_OFFSET);
Tests: T1 T2 T3
11839 1/1 addr_hit[ 15] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_3_OFFSET);
Tests: T1 T2 T3
11840 1/1 addr_hit[ 16] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_4_OFFSET);
Tests: T1 T2 T3
11841 1/1 addr_hit[ 17] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_5_OFFSET);
Tests: T1 T2 T3
11842 1/1 addr_hit[ 18] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_6_OFFSET);
Tests: T1 T2 T3
11843 1/1 addr_hit[ 19] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_7_OFFSET);
Tests: T1 T2 T3
11844 1/1 addr_hit[ 20] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_0_OFFSET);
Tests: T1 T2 T3
11845 1/1 addr_hit[ 21] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_1_OFFSET);
Tests: T1 T2 T3
11846 1/1 addr_hit[ 22] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_2_OFFSET);
Tests: T1 T2 T3
11847 1/1 addr_hit[ 23] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_3_OFFSET);
Tests: T1 T2 T3
11848 1/1 addr_hit[ 24] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_4_OFFSET);
Tests: T1 T2 T3
11849 1/1 addr_hit[ 25] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_5_OFFSET);
Tests: T1 T2 T3
11850 1/1 addr_hit[ 26] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_6_OFFSET);
Tests: T1 T2 T3
11851 1/1 addr_hit[ 27] = (reg_addr == FLASH_CTRL_MP_REGION_CFG_7_OFFSET);
Tests: T1 T2 T3
11852 1/1 addr_hit[ 28] = (reg_addr == FLASH_CTRL_MP_REGION_0_OFFSET);
Tests: T1 T2 T3
11853 1/1 addr_hit[ 29] = (reg_addr == FLASH_CTRL_MP_REGION_1_OFFSET);
Tests: T1 T2 T3
11854 1/1 addr_hit[ 30] = (reg_addr == FLASH_CTRL_MP_REGION_2_OFFSET);
Tests: T1 T2 T3
11855 1/1 addr_hit[ 31] = (reg_addr == FLASH_CTRL_MP_REGION_3_OFFSET);
Tests: T1 T2 T3
11856 1/1 addr_hit[ 32] = (reg_addr == FLASH_CTRL_MP_REGION_4_OFFSET);
Tests: T1 T2 T3
11857 1/1 addr_hit[ 33] = (reg_addr == FLASH_CTRL_MP_REGION_5_OFFSET);
Tests: T1 T2 T3
11858 1/1 addr_hit[ 34] = (reg_addr == FLASH_CTRL_MP_REGION_6_OFFSET);
Tests: T1 T2 T3
11859 1/1 addr_hit[ 35] = (reg_addr == FLASH_CTRL_MP_REGION_7_OFFSET);
Tests: T1 T2 T3
11860 1/1 addr_hit[ 36] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
Tests: T1 T2 T3
11861 1/1 addr_hit[ 37] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_0_OFFSET);
Tests: T1 T2 T3
11862 1/1 addr_hit[ 38] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_1_OFFSET);
Tests: T1 T2 T3
11863 1/1 addr_hit[ 39] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_2_OFFSET);
Tests: T1 T2 T3
11864 1/1 addr_hit[ 40] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_3_OFFSET);
Tests: T1 T2 T3
11865 1/1 addr_hit[ 41] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_4_OFFSET);
Tests: T1 T2 T3
11866 1/1 addr_hit[ 42] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_5_OFFSET);
Tests: T1 T2 T3
11867 1/1 addr_hit[ 43] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_6_OFFSET);
Tests: T1 T2 T3
11868 1/1 addr_hit[ 44] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_7_OFFSET);
Tests: T1 T2 T3
11869 1/1 addr_hit[ 45] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_8_OFFSET);
Tests: T1 T2 T3
11870 1/1 addr_hit[ 46] = (reg_addr == FLASH_CTRL_BANK0_INFO0_REGWEN_9_OFFSET);
Tests: T1 T2 T3
11871 1/1 addr_hit[ 47] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_OFFSET);
Tests: T1 T2 T3
11872 1/1 addr_hit[ 48] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_OFFSET);
Tests: T1 T2 T3
11873 1/1 addr_hit[ 49] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_OFFSET);
Tests: T1 T2 T3
11874 1/1 addr_hit[ 50] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_OFFSET);
Tests: T1 T2 T3
11875 1/1 addr_hit[ 51] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_OFFSET);
Tests: T1 T2 T3
11876 1/1 addr_hit[ 52] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_OFFSET);
Tests: T1 T2 T3
11877 1/1 addr_hit[ 53] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_OFFSET);
Tests: T1 T2 T3
11878 1/1 addr_hit[ 54] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_OFFSET);
Tests: T1 T2 T3
11879 1/1 addr_hit[ 55] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_OFFSET);
Tests: T1 T2 T3
11880 1/1 addr_hit[ 56] = (reg_addr == FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_OFFSET);
Tests: T1 T2 T3
11881 1/1 addr_hit[ 57] = (reg_addr == FLASH_CTRL_BANK0_INFO1_REGWEN_OFFSET);
Tests: T1 T2 T3
11882 1/1 addr_hit[ 58] = (reg_addr == FLASH_CTRL_BANK0_INFO1_PAGE_CFG_OFFSET);
Tests: T1 T2 T3
11883 1/1 addr_hit[ 59] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_0_OFFSET);
Tests: T1 T2 T3
11884 1/1 addr_hit[ 60] = (reg_addr == FLASH_CTRL_BANK0_INFO2_REGWEN_1_OFFSET);
Tests: T1 T2 T3
11885 1/1 addr_hit[ 61] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_OFFSET);
Tests: T1 T2 T3
11886 1/1 addr_hit[ 62] = (reg_addr == FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_OFFSET);
Tests: T1 T2 T3
11887 1/1 addr_hit[ 63] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_0_OFFSET);
Tests: T1 T2 T3
11888 1/1 addr_hit[ 64] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_1_OFFSET);
Tests: T1 T2 T3
11889 1/1 addr_hit[ 65] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_2_OFFSET);
Tests: T1 T2 T3
11890 1/1 addr_hit[ 66] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_3_OFFSET);
Tests: T1 T2 T3
11891 1/1 addr_hit[ 67] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_4_OFFSET);
Tests: T1 T2 T3
11892 1/1 addr_hit[ 68] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_5_OFFSET);
Tests: T1 T2 T3
11893 1/1 addr_hit[ 69] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_6_OFFSET);
Tests: T1 T2 T3
11894 1/1 addr_hit[ 70] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_7_OFFSET);
Tests: T1 T2 T3
11895 1/1 addr_hit[ 71] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_8_OFFSET);
Tests: T1 T2 T3
11896 1/1 addr_hit[ 72] = (reg_addr == FLASH_CTRL_BANK1_INFO0_REGWEN_9_OFFSET);
Tests: T1 T2 T3
11897 1/1 addr_hit[ 73] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_OFFSET);
Tests: T1 T2 T3
11898 1/1 addr_hit[ 74] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_OFFSET);
Tests: T1 T2 T3
11899 1/1 addr_hit[ 75] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_OFFSET);
Tests: T1 T2 T3
11900 1/1 addr_hit[ 76] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_OFFSET);
Tests: T1 T2 T3
11901 1/1 addr_hit[ 77] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_OFFSET);
Tests: T1 T2 T3
11902 1/1 addr_hit[ 78] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_OFFSET);
Tests: T1 T2 T3
11903 1/1 addr_hit[ 79] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_OFFSET);
Tests: T1 T2 T3
11904 1/1 addr_hit[ 80] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_OFFSET);
Tests: T1 T2 T3
11905 1/1 addr_hit[ 81] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_OFFSET);
Tests: T1 T2 T3
11906 1/1 addr_hit[ 82] = (reg_addr == FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_OFFSET);
Tests: T1 T2 T3
11907 1/1 addr_hit[ 83] = (reg_addr == FLASH_CTRL_BANK1_INFO1_REGWEN_OFFSET);
Tests: T1 T2 T3
11908 1/1 addr_hit[ 84] = (reg_addr == FLASH_CTRL_BANK1_INFO1_PAGE_CFG_OFFSET);
Tests: T1 T2 T3
11909 1/1 addr_hit[ 85] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_0_OFFSET);
Tests: T1 T2 T3
11910 1/1 addr_hit[ 86] = (reg_addr == FLASH_CTRL_BANK1_INFO2_REGWEN_1_OFFSET);
Tests: T1 T2 T3
11911 1/1 addr_hit[ 87] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_OFFSET);
Tests: T1 T2 T3
11912 1/1 addr_hit[ 88] = (reg_addr == FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_OFFSET);
Tests: T1 T2 T3
11913 1/1 addr_hit[ 89] = (reg_addr == FLASH_CTRL_HW_INFO_CFG_OVERRIDE_OFFSET);
Tests: T1 T2 T3
11914 1/1 addr_hit[ 90] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
Tests: T1 T2 T3
11915 1/1 addr_hit[ 91] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_SHADOWED_OFFSET);
Tests: T1 T2 T3
11916 1/1 addr_hit[ 92] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
Tests: T1 T2 T3
11917 1/1 addr_hit[ 93] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
Tests: T1 T2 T3
11918 1/1 addr_hit[ 94] = (reg_addr == FLASH_CTRL_DEBUG_STATE_OFFSET);
Tests: T1 T2 T3
11919 1/1 addr_hit[ 95] = (reg_addr == FLASH_CTRL_ERR_CODE_OFFSET);
Tests: T1 T2 T3
11920 1/1 addr_hit[ 96] = (reg_addr == FLASH_CTRL_STD_FAULT_STATUS_OFFSET);
Tests: T1 T2 T3
11921 1/1 addr_hit[ 97] = (reg_addr == FLASH_CTRL_FAULT_STATUS_OFFSET);
Tests: T1 T2 T3
11922 1/1 addr_hit[ 98] = (reg_addr == FLASH_CTRL_ERR_ADDR_OFFSET);
Tests: T1 T2 T3
11923 1/1 addr_hit[ 99] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_CNT_OFFSET);
Tests: T1 T2 T3
11924 1/1 addr_hit[100] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_OFFSET);
Tests: T1 T2 T3
11925 1/1 addr_hit[101] = (reg_addr == FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_OFFSET);
Tests: T1 T2 T3
11926 1/1 addr_hit[102] = (reg_addr == FLASH_CTRL_PHY_ALERT_CFG_OFFSET);
Tests: T1 T2 T3
11927 1/1 addr_hit[103] = (reg_addr == FLASH_CTRL_PHY_STATUS_OFFSET);
Tests: T1 T2 T3
11928 1/1 addr_hit[104] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
Tests: T1 T2 T3
11929 1/1 addr_hit[105] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
Tests: T1 T2 T3
11930 1/1 addr_hit[106] = (reg_addr == FLASH_CTRL_FIFO_RST_OFFSET);
Tests: T1 T2 T3
11931 1/1 addr_hit[107] = (reg_addr == FLASH_CTRL_CURR_FIFO_LVL_OFFSET);
Tests: T1 T2 T3
11932 end
11933
11934 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
11935
11936 // Check sub-word write is permitted
11937 always_comb begin
11938 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
11939 ((addr_hit[ 0] & (|(FLASH_CTRL_CORE_PERMIT[ 0] & ~reg_be))) |
11940 (addr_hit[ 1] & (|(FLASH_CTRL_CORE_PERMIT[ 1] & ~reg_be))) |
11941 (addr_hit[ 2] & (|(FLASH_CTRL_CORE_PERMIT[ 2] & ~reg_be))) |
11942 (addr_hit[ 3] & (|(FLASH_CTRL_CORE_PERMIT[ 3] & ~reg_be))) |
11943 (addr_hit[ 4] & (|(FLASH_CTRL_CORE_PERMIT[ 4] & ~reg_be))) |
11944 (addr_hit[ 5] & (|(FLASH_CTRL_CORE_PERMIT[ 5] & ~reg_be))) |
11945 (addr_hit[ 6] & (|(FLASH_CTRL_CORE_PERMIT[ 6] & ~reg_be))) |
11946 (addr_hit[ 7] & (|(FLASH_CTRL_CORE_PERMIT[ 7] & ~reg_be))) |
11947 (addr_hit[ 8] & (|(FLASH_CTRL_CORE_PERMIT[ 8] & ~reg_be))) |
11948 (addr_hit[ 9] & (|(FLASH_CTRL_CORE_PERMIT[ 9] & ~reg_be))) |
11949 (addr_hit[ 10] & (|(FLASH_CTRL_CORE_PERMIT[ 10] & ~reg_be))) |
11950 (addr_hit[ 11] & (|(FLASH_CTRL_CORE_PERMIT[ 11] & ~reg_be))) |
11951 (addr_hit[ 12] & (|(FLASH_CTRL_CORE_PERMIT[ 12] & ~reg_be))) |
11952 (addr_hit[ 13] & (|(FLASH_CTRL_CORE_PERMIT[ 13] & ~reg_be))) |
11953 (addr_hit[ 14] & (|(FLASH_CTRL_CORE_PERMIT[ 14] & ~reg_be))) |
11954 (addr_hit[ 15] & (|(FLASH_CTRL_CORE_PERMIT[ 15] & ~reg_be))) |
11955 (addr_hit[ 16] & (|(FLASH_CTRL_CORE_PERMIT[ 16] & ~reg_be))) |
11956 (addr_hit[ 17] & (|(FLASH_CTRL_CORE_PERMIT[ 17] & ~reg_be))) |
11957 (addr_hit[ 18] & (|(FLASH_CTRL_CORE_PERMIT[ 18] & ~reg_be))) |
11958 (addr_hit[ 19] & (|(FLASH_CTRL_CORE_PERMIT[ 19] & ~reg_be))) |
11959 (addr_hit[ 20] & (|(FLASH_CTRL_CORE_PERMIT[ 20] & ~reg_be))) |
11960 (addr_hit[ 21] & (|(FLASH_CTRL_CORE_PERMIT[ 21] & ~reg_be))) |
11961 (addr_hit[ 22] & (|(FLASH_CTRL_CORE_PERMIT[ 22] & ~reg_be))) |
11962 (addr_hit[ 23] & (|(FLASH_CTRL_CORE_PERMIT[ 23] & ~reg_be))) |
11963 (addr_hit[ 24] & (|(FLASH_CTRL_CORE_PERMIT[ 24] & ~reg_be))) |
11964 (addr_hit[ 25] & (|(FLASH_CTRL_CORE_PERMIT[ 25] & ~reg_be))) |
11965 (addr_hit[ 26] & (|(FLASH_CTRL_CORE_PERMIT[ 26] & ~reg_be))) |
11966 (addr_hit[ 27] & (|(FLASH_CTRL_CORE_PERMIT[ 27] & ~reg_be))) |
11967 (addr_hit[ 28] & (|(FLASH_CTRL_CORE_PERMIT[ 28] & ~reg_be))) |
11968 (addr_hit[ 29] & (|(FLASH_CTRL_CORE_PERMIT[ 29] & ~reg_be))) |
11969 (addr_hit[ 30] & (|(FLASH_CTRL_CORE_PERMIT[ 30] & ~reg_be))) |
11970 (addr_hit[ 31] & (|(FLASH_CTRL_CORE_PERMIT[ 31] & ~reg_be))) |
11971 (addr_hit[ 32] & (|(FLASH_CTRL_CORE_PERMIT[ 32] & ~reg_be))) |
11972 (addr_hit[ 33] & (|(FLASH_CTRL_CORE_PERMIT[ 33] & ~reg_be))) |
11973 (addr_hit[ 34] & (|(FLASH_CTRL_CORE_PERMIT[ 34] & ~reg_be))) |
11974 (addr_hit[ 35] & (|(FLASH_CTRL_CORE_PERMIT[ 35] & ~reg_be))) |
11975 (addr_hit[ 36] & (|(FLASH_CTRL_CORE_PERMIT[ 36] & ~reg_be))) |
11976 (addr_hit[ 37] & (|(FLASH_CTRL_CORE_PERMIT[ 37] & ~reg_be))) |
11977 (addr_hit[ 38] & (|(FLASH_CTRL_CORE_PERMIT[ 38] & ~reg_be))) |
11978 (addr_hit[ 39] & (|(FLASH_CTRL_CORE_PERMIT[ 39] & ~reg_be))) |
11979 (addr_hit[ 40] & (|(FLASH_CTRL_CORE_PERMIT[ 40] & ~reg_be))) |
11980 (addr_hit[ 41] & (|(FLASH_CTRL_CORE_PERMIT[ 41] & ~reg_be))) |
11981 (addr_hit[ 42] & (|(FLASH_CTRL_CORE_PERMIT[ 42] & ~reg_be))) |
11982 (addr_hit[ 43] & (|(FLASH_CTRL_CORE_PERMIT[ 43] & ~reg_be))) |
11983 (addr_hit[ 44] & (|(FLASH_CTRL_CORE_PERMIT[ 44] & ~reg_be))) |
11984 (addr_hit[ 45] & (|(FLASH_CTRL_CORE_PERMIT[ 45] & ~reg_be))) |
11985 (addr_hit[ 46] & (|(FLASH_CTRL_CORE_PERMIT[ 46] & ~reg_be))) |
11986 (addr_hit[ 47] & (|(FLASH_CTRL_CORE_PERMIT[ 47] & ~reg_be))) |
11987 (addr_hit[ 48] & (|(FLASH_CTRL_CORE_PERMIT[ 48] & ~reg_be))) |
11988 (addr_hit[ 49] & (|(FLASH_CTRL_CORE_PERMIT[ 49] & ~reg_be))) |
11989 (addr_hit[ 50] & (|(FLASH_CTRL_CORE_PERMIT[ 50] & ~reg_be))) |
11990 (addr_hit[ 51] & (|(FLASH_CTRL_CORE_PERMIT[ 51] & ~reg_be))) |
11991 (addr_hit[ 52] & (|(FLASH_CTRL_CORE_PERMIT[ 52] & ~reg_be))) |
11992 (addr_hit[ 53] & (|(FLASH_CTRL_CORE_PERMIT[ 53] & ~reg_be))) |
11993 (addr_hit[ 54] & (|(FLASH_CTRL_CORE_PERMIT[ 54] & ~reg_be))) |
11994 (addr_hit[ 55] & (|(FLASH_CTRL_CORE_PERMIT[ 55] & ~reg_be))) |
11995 (addr_hit[ 56] & (|(FLASH_CTRL_CORE_PERMIT[ 56] & ~reg_be))) |
11996 (addr_hit[ 57] & (|(FLASH_CTRL_CORE_PERMIT[ 57] & ~reg_be))) |
11997 (addr_hit[ 58] & (|(FLASH_CTRL_CORE_PERMIT[ 58] & ~reg_be))) |
11998 (addr_hit[ 59] & (|(FLASH_CTRL_CORE_PERMIT[ 59] & ~reg_be))) |
11999 (addr_hit[ 60] & (|(FLASH_CTRL_CORE_PERMIT[ 60] & ~reg_be))) |
12000 (addr_hit[ 61] & (|(FLASH_CTRL_CORE_PERMIT[ 61] & ~reg_be))) |
12001 (addr_hit[ 62] & (|(FLASH_CTRL_CORE_PERMIT[ 62] & ~reg_be))) |
12002 (addr_hit[ 63] & (|(FLASH_CTRL_CORE_PERMIT[ 63] & ~reg_be))) |
12003 (addr_hit[ 64] & (|(FLASH_CTRL_CORE_PERMIT[ 64] & ~reg_be))) |
12004 (addr_hit[ 65] & (|(FLASH_CTRL_CORE_PERMIT[ 65] & ~reg_be))) |
12005 (addr_hit[ 66] & (|(FLASH_CTRL_CORE_PERMIT[ 66] & ~reg_be))) |
12006 (addr_hit[ 67] & (|(FLASH_CTRL_CORE_PERMIT[ 67] & ~reg_be))) |
12007 (addr_hit[ 68] & (|(FLASH_CTRL_CORE_PERMIT[ 68] & ~reg_be))) |
12008 (addr_hit[ 69] & (|(FLASH_CTRL_CORE_PERMIT[ 69] & ~reg_be))) |
12009 (addr_hit[ 70] & (|(FLASH_CTRL_CORE_PERMIT[ 70] & ~reg_be))) |
12010 (addr_hit[ 71] & (|(FLASH_CTRL_CORE_PERMIT[ 71] & ~reg_be))) |
12011 (addr_hit[ 72] & (|(FLASH_CTRL_CORE_PERMIT[ 72] & ~reg_be))) |
12012 (addr_hit[ 73] & (|(FLASH_CTRL_CORE_PERMIT[ 73] & ~reg_be))) |
12013 (addr_hit[ 74] & (|(FLASH_CTRL_CORE_PERMIT[ 74] & ~reg_be))) |
12014 (addr_hit[ 75] & (|(FLASH_CTRL_CORE_PERMIT[ 75] & ~reg_be))) |
12015 (addr_hit[ 76] & (|(FLASH_CTRL_CORE_PERMIT[ 76] & ~reg_be))) |
12016 (addr_hit[ 77] & (|(FLASH_CTRL_CORE_PERMIT[ 77] & ~reg_be))) |
12017 (addr_hit[ 78] & (|(FLASH_CTRL_CORE_PERMIT[ 78] & ~reg_be))) |
12018 (addr_hit[ 79] & (|(FLASH_CTRL_CORE_PERMIT[ 79] & ~reg_be))) |
12019 (addr_hit[ 80] & (|(FLASH_CTRL_CORE_PERMIT[ 80] & ~reg_be))) |
12020 (addr_hit[ 81] & (|(FLASH_CTRL_CORE_PERMIT[ 81] & ~reg_be))) |
12021 (addr_hit[ 82] & (|(FLASH_CTRL_CORE_PERMIT[ 82] & ~reg_be))) |
12022 (addr_hit[ 83] & (|(FLASH_CTRL_CORE_PERMIT[ 83] & ~reg_be))) |
12023 (addr_hit[ 84] & (|(FLASH_CTRL_CORE_PERMIT[ 84] & ~reg_be))) |
12024 (addr_hit[ 85] & (|(FLASH_CTRL_CORE_PERMIT[ 85] & ~reg_be))) |
12025 (addr_hit[ 86] & (|(FLASH_CTRL_CORE_PERMIT[ 86] & ~reg_be))) |
12026 (addr_hit[ 87] & (|(FLASH_CTRL_CORE_PERMIT[ 87] & ~reg_be))) |
12027 (addr_hit[ 88] & (|(FLASH_CTRL_CORE_PERMIT[ 88] & ~reg_be))) |
12028 (addr_hit[ 89] & (|(FLASH_CTRL_CORE_PERMIT[ 89] & ~reg_be))) |
12029 (addr_hit[ 90] & (|(FLASH_CTRL_CORE_PERMIT[ 90] & ~reg_be))) |
12030 (addr_hit[ 91] & (|(FLASH_CTRL_CORE_PERMIT[ 91] & ~reg_be))) |
12031 (addr_hit[ 92] & (|(FLASH_CTRL_CORE_PERMIT[ 92] & ~reg_be))) |
12032 (addr_hit[ 93] & (|(FLASH_CTRL_CORE_PERMIT[ 93] & ~reg_be))) |
12033 (addr_hit[ 94] & (|(FLASH_CTRL_CORE_PERMIT[ 94] & ~reg_be))) |
12034 (addr_hit[ 95] & (|(FLASH_CTRL_CORE_PERMIT[ 95] & ~reg_be))) |
12035 (addr_hit[ 96] & (|(FLASH_CTRL_CORE_PERMIT[ 96] & ~reg_be))) |
12036 (addr_hit[ 97] & (|(FLASH_CTRL_CORE_PERMIT[ 97] & ~reg_be))) |
12037 (addr_hit[ 98] & (|(FLASH_CTRL_CORE_PERMIT[ 98] & ~reg_be))) |
12038 (addr_hit[ 99] & (|(FLASH_CTRL_CORE_PERMIT[ 99] & ~reg_be))) |
12039 (addr_hit[100] & (|(FLASH_CTRL_CORE_PERMIT[100] & ~reg_be))) |
12040 (addr_hit[101] & (|(FLASH_CTRL_CORE_PERMIT[101] & ~reg_be))) |
12041 (addr_hit[102] & (|(FLASH_CTRL_CORE_PERMIT[102] & ~reg_be))) |
12042 (addr_hit[103] & (|(FLASH_CTRL_CORE_PERMIT[103] & ~reg_be))) |
12043 (addr_hit[104] & (|(FLASH_CTRL_CORE_PERMIT[104] & ~reg_be))) |
12044 (addr_hit[105] & (|(FLASH_CTRL_CORE_PERMIT[105] & ~reg_be))) |
12045 (addr_hit[106] & (|(FLASH_CTRL_CORE_PERMIT[106] & ~reg_be))) |
12046 (addr_hit[107] & (|(FLASH_CTRL_CORE_PERMIT[107] & ~reg_be)))));
12047 end
12048
12049 // Generate write-enables
12050 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
12051
12052 1/1 assign intr_state_op_done_wd = reg_wdata[4];
Tests: T1 T2 T3
12053
12054 1/1 assign intr_state_corr_err_wd = reg_wdata[5];
Tests: T1 T2 T3
12055 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
12056
12057 1/1 assign intr_enable_prog_empty_wd = reg_wdata[0];
Tests: T1 T2 T3
12058
12059 1/1 assign intr_enable_prog_lvl_wd = reg_wdata[1];
Tests: T1 T2 T3
12060
12061 1/1 assign intr_enable_rd_full_wd = reg_wdata[2];
Tests: T1 T2 T3
12062
12063 1/1 assign intr_enable_rd_lvl_wd = reg_wdata[3];
Tests: T1 T2 T3
12064
12065 1/1 assign intr_enable_op_done_wd = reg_wdata[4];
Tests: T1 T2 T3
12066
12067 1/1 assign intr_enable_corr_err_wd = reg_wdata[5];
Tests: T1 T2 T3
12068 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
12069
12070 1/1 assign intr_test_prog_empty_wd = reg_wdata[0];
Tests: T1 T2 T3
12071
12072 1/1 assign intr_test_prog_lvl_wd = reg_wdata[1];
Tests: T1 T2 T3
12073
12074 1/1 assign intr_test_rd_full_wd = reg_wdata[2];
Tests: T1 T2 T3
12075
12076 1/1 assign intr_test_rd_lvl_wd = reg_wdata[3];
Tests: T1 T2 T3
12077
12078 1/1 assign intr_test_op_done_wd = reg_wdata[4];
Tests: T1 T2 T3
12079
12080 1/1 assign intr_test_corr_err_wd = reg_wdata[5];
Tests: T1 T2 T3
12081 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
12082
12083 1/1 assign alert_test_recov_err_wd = reg_wdata[0];
Tests: T1 T2 T3
12084
12085 1/1 assign alert_test_fatal_std_err_wd = reg_wdata[1];
Tests: T1 T2 T3
12086
12087 1/1 assign alert_test_fatal_err_wd = reg_wdata[2];
Tests: T1 T2 T3
12088
12089 1/1 assign alert_test_fatal_prim_flash_alert_wd = reg_wdata[3];
Tests: T1 T2 T3
12090
12091 1/1 assign alert_test_recov_prim_flash_alert_wd = reg_wdata[4];
Tests: T1 T2 T3
12092 1/1 assign dis_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
12093
12094 1/1 assign dis_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12095 1/1 assign exec_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
12096
12097 1/1 assign exec_wd = reg_wdata[31:0];
Tests: T1 T2 T3
12098 1/1 assign init_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
12099
12100 1/1 assign init_wd = reg_wdata[0];
Tests: T1 T2 T3
12101 1/1 assign ctrl_regwen_re = addr_hit[7] & reg_re & !reg_error;
Tests: T1 T2 T3
12102 1/1 assign control_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
12103
12104 1/1 assign control_start_wd = reg_wdata[0];
Tests: T1 T2 T3
12105
12106 1/1 assign control_op_wd = reg_wdata[5:4];
Tests: T1 T2 T3
12107
12108 1/1 assign control_prog_sel_wd = reg_wdata[6];
Tests: T1 T2 T3
12109
12110 1/1 assign control_erase_sel_wd = reg_wdata[7];
Tests: T1 T2 T3
12111
12112 1/1 assign control_partition_sel_wd = reg_wdata[8];
Tests: T1 T2 T3
12113
12114 1/1 assign control_info_sel_wd = reg_wdata[10:9];
Tests: T1 T2 T3
12115
12116 1/1 assign control_num_wd = reg_wdata[27:16];
Tests: T1 T2 T3
12117 1/1 assign addr_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
12118
12119 1/1 assign addr_wd = reg_wdata[19:0];
Tests: T1 T2 T3
12120 1/1 assign prog_type_en_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
12121
12122 1/1 assign prog_type_en_normal_wd = reg_wdata[0];
Tests: T1 T2 T3
12123
12124 1/1 assign prog_type_en_repair_wd = reg_wdata[1];
Tests: T1 T2 T3
12125 1/1 assign erase_suspend_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
12126
12127 1/1 assign erase_suspend_wd = reg_wdata[0];
Tests: T1 T2 T3
12128 1/1 assign region_cfg_regwen_0_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
12129
12130 1/1 assign region_cfg_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
12131 1/1 assign region_cfg_regwen_1_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
12132
12133 1/1 assign region_cfg_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
12134 1/1 assign region_cfg_regwen_2_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
12135
12136 1/1 assign region_cfg_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
12137 1/1 assign region_cfg_regwen_3_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
12138
12139 1/1 assign region_cfg_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
12140 1/1 assign region_cfg_regwen_4_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
12141
12142 1/1 assign region_cfg_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
12143 1/1 assign region_cfg_regwen_5_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
12144
12145 1/1 assign region_cfg_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
12146 1/1 assign region_cfg_regwen_6_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
12147
12148 1/1 assign region_cfg_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
12149 1/1 assign region_cfg_regwen_7_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
12150
12151 1/1 assign region_cfg_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
12152 1/1 assign mp_region_cfg_0_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
12153
12154 1/1 assign mp_region_cfg_0_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12155
12156 1/1 assign mp_region_cfg_0_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12157
12158 1/1 assign mp_region_cfg_0_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12159
12160 1/1 assign mp_region_cfg_0_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12161
12162 1/1 assign mp_region_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12163
12164 1/1 assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12165
12166 1/1 assign mp_region_cfg_0_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12167 1/1 assign mp_region_cfg_1_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
12168
12169 1/1 assign mp_region_cfg_1_en_1_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12170
12171 1/1 assign mp_region_cfg_1_rd_en_1_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12172
12173 1/1 assign mp_region_cfg_1_prog_en_1_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12174
12175 1/1 assign mp_region_cfg_1_erase_en_1_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12176
12177 1/1 assign mp_region_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12178
12179 1/1 assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12180
12181 1/1 assign mp_region_cfg_1_he_en_1_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12182 1/1 assign mp_region_cfg_2_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
12183
12184 1/1 assign mp_region_cfg_2_en_2_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12185
12186 1/1 assign mp_region_cfg_2_rd_en_2_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12187
12188 1/1 assign mp_region_cfg_2_prog_en_2_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12189
12190 1/1 assign mp_region_cfg_2_erase_en_2_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12191
12192 1/1 assign mp_region_cfg_2_scramble_en_2_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12193
12194 1/1 assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12195
12196 1/1 assign mp_region_cfg_2_he_en_2_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12197 1/1 assign mp_region_cfg_3_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
12198
12199 1/1 assign mp_region_cfg_3_en_3_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12200
12201 1/1 assign mp_region_cfg_3_rd_en_3_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12202
12203 1/1 assign mp_region_cfg_3_prog_en_3_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12204
12205 1/1 assign mp_region_cfg_3_erase_en_3_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12206
12207 1/1 assign mp_region_cfg_3_scramble_en_3_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12208
12209 1/1 assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12210
12211 1/1 assign mp_region_cfg_3_he_en_3_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12212 1/1 assign mp_region_cfg_4_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
12213
12214 1/1 assign mp_region_cfg_4_en_4_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12215
12216 1/1 assign mp_region_cfg_4_rd_en_4_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12217
12218 1/1 assign mp_region_cfg_4_prog_en_4_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12219
12220 1/1 assign mp_region_cfg_4_erase_en_4_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12221
12222 1/1 assign mp_region_cfg_4_scramble_en_4_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12223
12224 1/1 assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12225
12226 1/1 assign mp_region_cfg_4_he_en_4_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12227 1/1 assign mp_region_cfg_5_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
12228
12229 1/1 assign mp_region_cfg_5_en_5_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12230
12231 1/1 assign mp_region_cfg_5_rd_en_5_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12232
12233 1/1 assign mp_region_cfg_5_prog_en_5_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12234
12235 1/1 assign mp_region_cfg_5_erase_en_5_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12236
12237 1/1 assign mp_region_cfg_5_scramble_en_5_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12238
12239 1/1 assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12240
12241 1/1 assign mp_region_cfg_5_he_en_5_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12242 1/1 assign mp_region_cfg_6_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
12243
12244 1/1 assign mp_region_cfg_6_en_6_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12245
12246 1/1 assign mp_region_cfg_6_rd_en_6_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12247
12248 1/1 assign mp_region_cfg_6_prog_en_6_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12249
12250 1/1 assign mp_region_cfg_6_erase_en_6_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12251
12252 1/1 assign mp_region_cfg_6_scramble_en_6_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12253
12254 1/1 assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12255
12256 1/1 assign mp_region_cfg_6_he_en_6_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12257 1/1 assign mp_region_cfg_7_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
12258
12259 1/1 assign mp_region_cfg_7_en_7_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12260
12261 1/1 assign mp_region_cfg_7_rd_en_7_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12262
12263 1/1 assign mp_region_cfg_7_prog_en_7_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12264
12265 1/1 assign mp_region_cfg_7_erase_en_7_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12266
12267 1/1 assign mp_region_cfg_7_scramble_en_7_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12268
12269 1/1 assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12270
12271 1/1 assign mp_region_cfg_7_he_en_7_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12272 1/1 assign mp_region_0_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
12273
12274 1/1 assign mp_region_0_base_0_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12275
12276 1/1 assign mp_region_0_size_0_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12277 1/1 assign mp_region_1_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
12278
12279 1/1 assign mp_region_1_base_1_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12280
12281 1/1 assign mp_region_1_size_1_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12282 1/1 assign mp_region_2_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
12283
12284 1/1 assign mp_region_2_base_2_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12285
12286 1/1 assign mp_region_2_size_2_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12287 1/1 assign mp_region_3_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
12288
12289 1/1 assign mp_region_3_base_3_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12290
12291 1/1 assign mp_region_3_size_3_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12292 1/1 assign mp_region_4_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
12293
12294 1/1 assign mp_region_4_base_4_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12295
12296 1/1 assign mp_region_4_size_4_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12297 1/1 assign mp_region_5_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
12298
12299 1/1 assign mp_region_5_base_5_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12300
12301 1/1 assign mp_region_5_size_5_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12302 1/1 assign mp_region_6_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
12303
12304 1/1 assign mp_region_6_base_6_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12305
12306 1/1 assign mp_region_6_size_6_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12307 1/1 assign mp_region_7_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
12308
12309 1/1 assign mp_region_7_base_7_wd = reg_wdata[8:0];
Tests: T1 T2 T3
12310
12311 1/1 assign mp_region_7_size_7_wd = reg_wdata[18:9];
Tests: T1 T2 T3
12312 1/1 assign default_region_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
12313
12314 1/1 assign default_region_rd_en_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12315
12316 1/1 assign default_region_prog_en_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12317
12318 1/1 assign default_region_erase_en_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12319
12320 1/1 assign default_region_scramble_en_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12321
12322 1/1 assign default_region_ecc_en_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12323
12324 1/1 assign default_region_he_en_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12325 1/1 assign bank0_info0_regwen_0_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T3
12326
12327 1/1 assign bank0_info0_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
12328 1/1 assign bank0_info0_regwen_1_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
12329
12330 1/1 assign bank0_info0_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
12331 1/1 assign bank0_info0_regwen_2_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
12332
12333 1/1 assign bank0_info0_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
12334 1/1 assign bank0_info0_regwen_3_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
12335
12336 1/1 assign bank0_info0_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
12337 1/1 assign bank0_info0_regwen_4_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
12338
12339 1/1 assign bank0_info0_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
12340 1/1 assign bank0_info0_regwen_5_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T3
12341
12342 1/1 assign bank0_info0_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
12343 1/1 assign bank0_info0_regwen_6_we = addr_hit[43] & reg_we & !reg_error;
Tests: T1 T2 T3
12344
12345 1/1 assign bank0_info0_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
12346 1/1 assign bank0_info0_regwen_7_we = addr_hit[44] & reg_we & !reg_error;
Tests: T1 T2 T3
12347
12348 1/1 assign bank0_info0_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
12349 1/1 assign bank0_info0_regwen_8_we = addr_hit[45] & reg_we & !reg_error;
Tests: T1 T2 T3
12350
12351 1/1 assign bank0_info0_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
12352 1/1 assign bank0_info0_regwen_9_we = addr_hit[46] & reg_we & !reg_error;
Tests: T1 T2 T3
12353
12354 1/1 assign bank0_info0_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
12355 1/1 assign bank0_info0_page_cfg_0_we = addr_hit[47] & reg_we & !reg_error;
Tests: T1 T2 T3
12356
12357 1/1 assign bank0_info0_page_cfg_0_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12358
12359 1/1 assign bank0_info0_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12360
12361 1/1 assign bank0_info0_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12362
12363 1/1 assign bank0_info0_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12364
12365 1/1 assign bank0_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12366
12367 1/1 assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12368
12369 1/1 assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12370 1/1 assign bank0_info0_page_cfg_1_we = addr_hit[48] & reg_we & !reg_error;
Tests: T1 T2 T3
12371
12372 1/1 assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12373
12374 1/1 assign bank0_info0_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12375
12376 1/1 assign bank0_info0_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12377
12378 1/1 assign bank0_info0_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12379
12380 1/1 assign bank0_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12381
12382 1/1 assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12383
12384 1/1 assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12385 1/1 assign bank0_info0_page_cfg_2_we = addr_hit[49] & reg_we & !reg_error;
Tests: T1 T2 T3
12386
12387 1/1 assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12388
12389 1/1 assign bank0_info0_page_cfg_2_rd_en_2_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12390
12391 1/1 assign bank0_info0_page_cfg_2_prog_en_2_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12392
12393 1/1 assign bank0_info0_page_cfg_2_erase_en_2_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12394
12395 1/1 assign bank0_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12396
12397 1/1 assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12398
12399 1/1 assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12400 1/1 assign bank0_info0_page_cfg_3_we = addr_hit[50] & reg_we & !reg_error;
Tests: T1 T2 T3
12401
12402 1/1 assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12403
12404 1/1 assign bank0_info0_page_cfg_3_rd_en_3_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12405
12406 1/1 assign bank0_info0_page_cfg_3_prog_en_3_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12407
12408 1/1 assign bank0_info0_page_cfg_3_erase_en_3_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12409
12410 1/1 assign bank0_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12411
12412 1/1 assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12413
12414 1/1 assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12415 1/1 assign bank0_info0_page_cfg_4_we = addr_hit[51] & reg_we & !reg_error;
Tests: T1 T2 T3
12416
12417 1/1 assign bank0_info0_page_cfg_4_en_4_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12418
12419 1/1 assign bank0_info0_page_cfg_4_rd_en_4_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12420
12421 1/1 assign bank0_info0_page_cfg_4_prog_en_4_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12422
12423 1/1 assign bank0_info0_page_cfg_4_erase_en_4_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12424
12425 1/1 assign bank0_info0_page_cfg_4_scramble_en_4_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12426
12427 1/1 assign bank0_info0_page_cfg_4_ecc_en_4_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12428
12429 1/1 assign bank0_info0_page_cfg_4_he_en_4_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12430 1/1 assign bank0_info0_page_cfg_5_we = addr_hit[52] & reg_we & !reg_error;
Tests: T1 T2 T3
12431
12432 1/1 assign bank0_info0_page_cfg_5_en_5_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12433
12434 1/1 assign bank0_info0_page_cfg_5_rd_en_5_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12435
12436 1/1 assign bank0_info0_page_cfg_5_prog_en_5_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12437
12438 1/1 assign bank0_info0_page_cfg_5_erase_en_5_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12439
12440 1/1 assign bank0_info0_page_cfg_5_scramble_en_5_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12441
12442 1/1 assign bank0_info0_page_cfg_5_ecc_en_5_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12443
12444 1/1 assign bank0_info0_page_cfg_5_he_en_5_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12445 1/1 assign bank0_info0_page_cfg_6_we = addr_hit[53] & reg_we & !reg_error;
Tests: T1 T2 T3
12446
12447 1/1 assign bank0_info0_page_cfg_6_en_6_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12448
12449 1/1 assign bank0_info0_page_cfg_6_rd_en_6_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12450
12451 1/1 assign bank0_info0_page_cfg_6_prog_en_6_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12452
12453 1/1 assign bank0_info0_page_cfg_6_erase_en_6_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12454
12455 1/1 assign bank0_info0_page_cfg_6_scramble_en_6_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12456
12457 1/1 assign bank0_info0_page_cfg_6_ecc_en_6_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12458
12459 1/1 assign bank0_info0_page_cfg_6_he_en_6_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12460 1/1 assign bank0_info0_page_cfg_7_we = addr_hit[54] & reg_we & !reg_error;
Tests: T1 T2 T3
12461
12462 1/1 assign bank0_info0_page_cfg_7_en_7_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12463
12464 1/1 assign bank0_info0_page_cfg_7_rd_en_7_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12465
12466 1/1 assign bank0_info0_page_cfg_7_prog_en_7_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12467
12468 1/1 assign bank0_info0_page_cfg_7_erase_en_7_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12469
12470 1/1 assign bank0_info0_page_cfg_7_scramble_en_7_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12471
12472 1/1 assign bank0_info0_page_cfg_7_ecc_en_7_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12473
12474 1/1 assign bank0_info0_page_cfg_7_he_en_7_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12475 1/1 assign bank0_info0_page_cfg_8_we = addr_hit[55] & reg_we & !reg_error;
Tests: T1 T2 T3
12476
12477 1/1 assign bank0_info0_page_cfg_8_en_8_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12478
12479 1/1 assign bank0_info0_page_cfg_8_rd_en_8_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12480
12481 1/1 assign bank0_info0_page_cfg_8_prog_en_8_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12482
12483 1/1 assign bank0_info0_page_cfg_8_erase_en_8_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12484
12485 1/1 assign bank0_info0_page_cfg_8_scramble_en_8_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12486
12487 1/1 assign bank0_info0_page_cfg_8_ecc_en_8_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12488
12489 1/1 assign bank0_info0_page_cfg_8_he_en_8_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12490 1/1 assign bank0_info0_page_cfg_9_we = addr_hit[56] & reg_we & !reg_error;
Tests: T1 T2 T3
12491
12492 1/1 assign bank0_info0_page_cfg_9_en_9_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12493
12494 1/1 assign bank0_info0_page_cfg_9_rd_en_9_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12495
12496 1/1 assign bank0_info0_page_cfg_9_prog_en_9_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12497
12498 1/1 assign bank0_info0_page_cfg_9_erase_en_9_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12499
12500 1/1 assign bank0_info0_page_cfg_9_scramble_en_9_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12501
12502 1/1 assign bank0_info0_page_cfg_9_ecc_en_9_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12503
12504 1/1 assign bank0_info0_page_cfg_9_he_en_9_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12505 1/1 assign bank0_info1_regwen_we = addr_hit[57] & reg_we & !reg_error;
Tests: T1 T2 T3
12506
12507 1/1 assign bank0_info1_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
12508 1/1 assign bank0_info1_page_cfg_we = addr_hit[58] & reg_we & !reg_error;
Tests: T1 T2 T3
12509
12510 1/1 assign bank0_info1_page_cfg_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12511
12512 1/1 assign bank0_info1_page_cfg_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12513
12514 1/1 assign bank0_info1_page_cfg_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12515
12516 1/1 assign bank0_info1_page_cfg_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12517
12518 1/1 assign bank0_info1_page_cfg_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12519
12520 1/1 assign bank0_info1_page_cfg_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12521
12522 1/1 assign bank0_info1_page_cfg_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12523 1/1 assign bank0_info2_regwen_0_we = addr_hit[59] & reg_we & !reg_error;
Tests: T1 T2 T3
12524
12525 1/1 assign bank0_info2_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
12526 1/1 assign bank0_info2_regwen_1_we = addr_hit[60] & reg_we & !reg_error;
Tests: T1 T2 T3
12527
12528 1/1 assign bank0_info2_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
12529 1/1 assign bank0_info2_page_cfg_0_we = addr_hit[61] & reg_we & !reg_error;
Tests: T1 T2 T3
12530
12531 1/1 assign bank0_info2_page_cfg_0_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12532
12533 1/1 assign bank0_info2_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12534
12535 1/1 assign bank0_info2_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12536
12537 1/1 assign bank0_info2_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12538
12539 1/1 assign bank0_info2_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12540
12541 1/1 assign bank0_info2_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12542
12543 1/1 assign bank0_info2_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12544 1/1 assign bank0_info2_page_cfg_1_we = addr_hit[62] & reg_we & !reg_error;
Tests: T1 T2 T3
12545
12546 1/1 assign bank0_info2_page_cfg_1_en_1_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12547
12548 1/1 assign bank0_info2_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12549
12550 1/1 assign bank0_info2_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12551
12552 1/1 assign bank0_info2_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12553
12554 1/1 assign bank0_info2_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12555
12556 1/1 assign bank0_info2_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12557
12558 1/1 assign bank0_info2_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12559 1/1 assign bank1_info0_regwen_0_we = addr_hit[63] & reg_we & !reg_error;
Tests: T1 T2 T3
12560
12561 1/1 assign bank1_info0_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
12562 1/1 assign bank1_info0_regwen_1_we = addr_hit[64] & reg_we & !reg_error;
Tests: T1 T2 T3
12563
12564 1/1 assign bank1_info0_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
12565 1/1 assign bank1_info0_regwen_2_we = addr_hit[65] & reg_we & !reg_error;
Tests: T1 T2 T3
12566
12567 1/1 assign bank1_info0_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
12568 1/1 assign bank1_info0_regwen_3_we = addr_hit[66] & reg_we & !reg_error;
Tests: T1 T2 T3
12569
12570 1/1 assign bank1_info0_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
12571 1/1 assign bank1_info0_regwen_4_we = addr_hit[67] & reg_we & !reg_error;
Tests: T1 T2 T3
12572
12573 1/1 assign bank1_info0_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
12574 1/1 assign bank1_info0_regwen_5_we = addr_hit[68] & reg_we & !reg_error;
Tests: T1 T2 T3
12575
12576 1/1 assign bank1_info0_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
12577 1/1 assign bank1_info0_regwen_6_we = addr_hit[69] & reg_we & !reg_error;
Tests: T1 T2 T3
12578
12579 1/1 assign bank1_info0_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
12580 1/1 assign bank1_info0_regwen_7_we = addr_hit[70] & reg_we & !reg_error;
Tests: T1 T2 T3
12581
12582 1/1 assign bank1_info0_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
12583 1/1 assign bank1_info0_regwen_8_we = addr_hit[71] & reg_we & !reg_error;
Tests: T1 T2 T3
12584
12585 1/1 assign bank1_info0_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
12586 1/1 assign bank1_info0_regwen_9_we = addr_hit[72] & reg_we & !reg_error;
Tests: T1 T2 T3
12587
12588 1/1 assign bank1_info0_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
12589 1/1 assign bank1_info0_page_cfg_0_we = addr_hit[73] & reg_we & !reg_error;
Tests: T1 T2 T3
12590
12591 1/1 assign bank1_info0_page_cfg_0_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12592
12593 1/1 assign bank1_info0_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12594
12595 1/1 assign bank1_info0_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12596
12597 1/1 assign bank1_info0_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12598
12599 1/1 assign bank1_info0_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12600
12601 1/1 assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12602
12603 1/1 assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12604 1/1 assign bank1_info0_page_cfg_1_we = addr_hit[74] & reg_we & !reg_error;
Tests: T1 T2 T3
12605
12606 1/1 assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12607
12608 1/1 assign bank1_info0_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12609
12610 1/1 assign bank1_info0_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12611
12612 1/1 assign bank1_info0_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12613
12614 1/1 assign bank1_info0_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12615
12616 1/1 assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12617
12618 1/1 assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12619 1/1 assign bank1_info0_page_cfg_2_we = addr_hit[75] & reg_we & !reg_error;
Tests: T1 T2 T3
12620
12621 1/1 assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12622
12623 1/1 assign bank1_info0_page_cfg_2_rd_en_2_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12624
12625 1/1 assign bank1_info0_page_cfg_2_prog_en_2_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12626
12627 1/1 assign bank1_info0_page_cfg_2_erase_en_2_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12628
12629 1/1 assign bank1_info0_page_cfg_2_scramble_en_2_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12630
12631 1/1 assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12632
12633 1/1 assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12634 1/1 assign bank1_info0_page_cfg_3_we = addr_hit[76] & reg_we & !reg_error;
Tests: T1 T2 T3
12635
12636 1/1 assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12637
12638 1/1 assign bank1_info0_page_cfg_3_rd_en_3_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12639
12640 1/1 assign bank1_info0_page_cfg_3_prog_en_3_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12641
12642 1/1 assign bank1_info0_page_cfg_3_erase_en_3_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12643
12644 1/1 assign bank1_info0_page_cfg_3_scramble_en_3_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12645
12646 1/1 assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12647
12648 1/1 assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12649 1/1 assign bank1_info0_page_cfg_4_we = addr_hit[77] & reg_we & !reg_error;
Tests: T1 T2 T3
12650
12651 1/1 assign bank1_info0_page_cfg_4_en_4_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12652
12653 1/1 assign bank1_info0_page_cfg_4_rd_en_4_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12654
12655 1/1 assign bank1_info0_page_cfg_4_prog_en_4_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12656
12657 1/1 assign bank1_info0_page_cfg_4_erase_en_4_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12658
12659 1/1 assign bank1_info0_page_cfg_4_scramble_en_4_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12660
12661 1/1 assign bank1_info0_page_cfg_4_ecc_en_4_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12662
12663 1/1 assign bank1_info0_page_cfg_4_he_en_4_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12664 1/1 assign bank1_info0_page_cfg_5_we = addr_hit[78] & reg_we & !reg_error;
Tests: T1 T2 T3
12665
12666 1/1 assign bank1_info0_page_cfg_5_en_5_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12667
12668 1/1 assign bank1_info0_page_cfg_5_rd_en_5_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12669
12670 1/1 assign bank1_info0_page_cfg_5_prog_en_5_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12671
12672 1/1 assign bank1_info0_page_cfg_5_erase_en_5_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12673
12674 1/1 assign bank1_info0_page_cfg_5_scramble_en_5_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12675
12676 1/1 assign bank1_info0_page_cfg_5_ecc_en_5_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12677
12678 1/1 assign bank1_info0_page_cfg_5_he_en_5_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12679 1/1 assign bank1_info0_page_cfg_6_we = addr_hit[79] & reg_we & !reg_error;
Tests: T1 T2 T3
12680
12681 1/1 assign bank1_info0_page_cfg_6_en_6_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12682
12683 1/1 assign bank1_info0_page_cfg_6_rd_en_6_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12684
12685 1/1 assign bank1_info0_page_cfg_6_prog_en_6_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12686
12687 1/1 assign bank1_info0_page_cfg_6_erase_en_6_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12688
12689 1/1 assign bank1_info0_page_cfg_6_scramble_en_6_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12690
12691 1/1 assign bank1_info0_page_cfg_6_ecc_en_6_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12692
12693 1/1 assign bank1_info0_page_cfg_6_he_en_6_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12694 1/1 assign bank1_info0_page_cfg_7_we = addr_hit[80] & reg_we & !reg_error;
Tests: T1 T2 T3
12695
12696 1/1 assign bank1_info0_page_cfg_7_en_7_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12697
12698 1/1 assign bank1_info0_page_cfg_7_rd_en_7_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12699
12700 1/1 assign bank1_info0_page_cfg_7_prog_en_7_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12701
12702 1/1 assign bank1_info0_page_cfg_7_erase_en_7_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12703
12704 1/1 assign bank1_info0_page_cfg_7_scramble_en_7_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12705
12706 1/1 assign bank1_info0_page_cfg_7_ecc_en_7_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12707
12708 1/1 assign bank1_info0_page_cfg_7_he_en_7_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12709 1/1 assign bank1_info0_page_cfg_8_we = addr_hit[81] & reg_we & !reg_error;
Tests: T1 T2 T3
12710
12711 1/1 assign bank1_info0_page_cfg_8_en_8_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12712
12713 1/1 assign bank1_info0_page_cfg_8_rd_en_8_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12714
12715 1/1 assign bank1_info0_page_cfg_8_prog_en_8_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12716
12717 1/1 assign bank1_info0_page_cfg_8_erase_en_8_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12718
12719 1/1 assign bank1_info0_page_cfg_8_scramble_en_8_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12720
12721 1/1 assign bank1_info0_page_cfg_8_ecc_en_8_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12722
12723 1/1 assign bank1_info0_page_cfg_8_he_en_8_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12724 1/1 assign bank1_info0_page_cfg_9_we = addr_hit[82] & reg_we & !reg_error;
Tests: T1 T2 T3
12725
12726 1/1 assign bank1_info0_page_cfg_9_en_9_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12727
12728 1/1 assign bank1_info0_page_cfg_9_rd_en_9_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12729
12730 1/1 assign bank1_info0_page_cfg_9_prog_en_9_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12731
12732 1/1 assign bank1_info0_page_cfg_9_erase_en_9_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12733
12734 1/1 assign bank1_info0_page_cfg_9_scramble_en_9_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12735
12736 1/1 assign bank1_info0_page_cfg_9_ecc_en_9_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12737
12738 1/1 assign bank1_info0_page_cfg_9_he_en_9_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12739 1/1 assign bank1_info1_regwen_we = addr_hit[83] & reg_we & !reg_error;
Tests: T1 T2 T3
12740
12741 1/1 assign bank1_info1_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
12742 1/1 assign bank1_info1_page_cfg_we = addr_hit[84] & reg_we & !reg_error;
Tests: T1 T2 T3
12743
12744 1/1 assign bank1_info1_page_cfg_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12745
12746 1/1 assign bank1_info1_page_cfg_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12747
12748 1/1 assign bank1_info1_page_cfg_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12749
12750 1/1 assign bank1_info1_page_cfg_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12751
12752 1/1 assign bank1_info1_page_cfg_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12753
12754 1/1 assign bank1_info1_page_cfg_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12755
12756 1/1 assign bank1_info1_page_cfg_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12757 1/1 assign bank1_info2_regwen_0_we = addr_hit[85] & reg_we & !reg_error;
Tests: T1 T2 T3
12758
12759 1/1 assign bank1_info2_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
12760 1/1 assign bank1_info2_regwen_1_we = addr_hit[86] & reg_we & !reg_error;
Tests: T1 T2 T3
12761
12762 1/1 assign bank1_info2_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
12763 1/1 assign bank1_info2_page_cfg_0_we = addr_hit[87] & reg_we & !reg_error;
Tests: T1 T2 T3
12764
12765 1/1 assign bank1_info2_page_cfg_0_en_0_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12766
12767 1/1 assign bank1_info2_page_cfg_0_rd_en_0_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12768
12769 1/1 assign bank1_info2_page_cfg_0_prog_en_0_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12770
12771 1/1 assign bank1_info2_page_cfg_0_erase_en_0_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12772
12773 1/1 assign bank1_info2_page_cfg_0_scramble_en_0_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12774
12775 1/1 assign bank1_info2_page_cfg_0_ecc_en_0_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12776
12777 1/1 assign bank1_info2_page_cfg_0_he_en_0_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12778 1/1 assign bank1_info2_page_cfg_1_we = addr_hit[88] & reg_we & !reg_error;
Tests: T1 T2 T3
12779
12780 1/1 assign bank1_info2_page_cfg_1_en_1_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12781
12782 1/1 assign bank1_info2_page_cfg_1_rd_en_1_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12783
12784 1/1 assign bank1_info2_page_cfg_1_prog_en_1_wd = reg_wdata[11:8];
Tests: T1 T2 T3
12785
12786 1/1 assign bank1_info2_page_cfg_1_erase_en_1_wd = reg_wdata[15:12];
Tests: T1 T2 T3
12787
12788 1/1 assign bank1_info2_page_cfg_1_scramble_en_1_wd = reg_wdata[19:16];
Tests: T1 T2 T3
12789
12790 1/1 assign bank1_info2_page_cfg_1_ecc_en_1_wd = reg_wdata[23:20];
Tests: T1 T2 T3
12791
12792 1/1 assign bank1_info2_page_cfg_1_he_en_1_wd = reg_wdata[27:24];
Tests: T1 T2 T3
12793 1/1 assign hw_info_cfg_override_we = addr_hit[89] & reg_we & !reg_error;
Tests: T1 T2 T3
12794
12795 1/1 assign hw_info_cfg_override_scramble_dis_wd = reg_wdata[3:0];
Tests: T1 T2 T3
12796
12797 1/1 assign hw_info_cfg_override_ecc_dis_wd = reg_wdata[7:4];
Tests: T1 T2 T3
12798 1/1 assign bank_cfg_regwen_we = addr_hit[90] & reg_we & !reg_error;
Tests: T1 T2 T3
12799
12800 1/1 assign bank_cfg_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
12801 1/1 assign mp_bank_cfg_shadowed_re = addr_hit[91] & reg_re & !reg_error;
Tests: T1 T2 T3
12802 1/1 assign mp_bank_cfg_shadowed_we = addr_hit[91] & reg_we & !reg_error;
Tests: T1 T2 T3
12803
12804 1/1 assign mp_bank_cfg_shadowed_erase_en_0_wd = reg_wdata[0];
Tests: T1 T2 T3
12805
12806 1/1 assign mp_bank_cfg_shadowed_erase_en_1_wd = reg_wdata[1];
Tests: T1 T2 T3
12807 1/1 assign op_status_we = addr_hit[92] & reg_we & !reg_error;
Tests: T1 T2 T3
12808
12809 1/1 assign op_status_done_wd = reg_wdata[0];
Tests: T1 T2 T3
12810
12811 1/1 assign op_status_err_wd = reg_wdata[1];
Tests: T1 T2 T3
12812 1/1 assign debug_state_re = addr_hit[94] & reg_re & !reg_error;
Tests: T1 T2 T3
12813 1/1 assign err_code_we = addr_hit[95] & reg_we & !reg_error;
Tests: T1 T2 T3
12814
12815 1/1 assign err_code_op_err_wd = reg_wdata[0];
Tests: T1 T2 T3
12816
12817 1/1 assign err_code_mp_err_wd = reg_wdata[1];
Tests: T1 T2 T3
12818
12819 1/1 assign err_code_rd_err_wd = reg_wdata[2];
Tests: T1 T2 T3
12820
12821 1/1 assign err_code_prog_err_wd = reg_wdata[3];
Tests: T1 T2 T3
12822
12823 1/1 assign err_code_prog_win_err_wd = reg_wdata[4];
Tests: T1 T2 T3
12824
12825 1/1 assign err_code_prog_type_err_wd = reg_wdata[5];
Tests: T1 T2 T3
12826
12827 1/1 assign err_code_update_err_wd = reg_wdata[6];
Tests: T1 T2 T3
12828
12829 1/1 assign err_code_macro_err_wd = reg_wdata[7];
Tests: T1 T2 T3
12830 1/1 assign fault_status_we = addr_hit[97] & reg_we & !reg_error;
Tests: T1 T2 T3
12831
12832 1/1 assign fault_status_phy_relbl_err_wd = reg_wdata[7];
Tests: T1 T2 T3
12833
12834 1/1 assign fault_status_phy_storage_err_wd = reg_wdata[8];
Tests: T1 T2 T3
12835 1/1 assign ecc_single_err_cnt_we = addr_hit[99] & reg_we & !reg_error;
Tests: T1 T2 T3
12836
12837 1/1 assign ecc_single_err_cnt_ecc_single_err_cnt_0_wd = reg_wdata[7:0];
Tests: T1 T2 T3
12838
12839 1/1 assign ecc_single_err_cnt_ecc_single_err_cnt_1_wd = reg_wdata[15:8];
Tests: T1 T2 T3
12840 1/1 assign phy_alert_cfg_we = addr_hit[102] & reg_we & !reg_error;
Tests: T1 T2 T3
12841
12842 1/1 assign phy_alert_cfg_alert_ack_wd = reg_wdata[0];
Tests: T1 T2 T3
12843
12844 1/1 assign phy_alert_cfg_alert_trig_wd = reg_wdata[1];
Tests: T1 T2 T3
12845 1/1 assign scratch_we = addr_hit[104] & reg_we & !reg_error;
Tests: T1 T2 T3
12846
12847 1/1 assign scratch_wd = reg_wdata[31:0];
Tests: T1 T2 T3
12848 1/1 assign fifo_lvl_we = addr_hit[105] & reg_we & !reg_error;
Tests: T1 T2 T3
12849
12850 1/1 assign fifo_lvl_prog_wd = reg_wdata[4:0];
Tests: T1 T2 T3
12851
12852 1/1 assign fifo_lvl_rd_wd = reg_wdata[12:8];
Tests: T1 T2 T3
12853 1/1 assign fifo_rst_we = addr_hit[106] & reg_we & !reg_error;
Tests: T1 T2 T3
12854
12855 1/1 assign fifo_rst_wd = reg_wdata[0];
Tests: T1 T2 T3
12856 1/1 assign curr_fifo_lvl_re = addr_hit[107] & reg_re & !reg_error;
Tests: T1 T2 T3
12857
12858 // Assign write-enables to checker logic vector.
12859 always_comb begin
12860 1/1 reg_we_check = '0;
Tests: T1 T2 T3
12861 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
12862 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
12863 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
12864 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
12865 1/1 reg_we_check[4] = dis_we;
Tests: T1 T2 T3
12866 1/1 reg_we_check[5] = exec_we;
Tests: T1 T2 T3
12867 1/1 reg_we_check[6] = init_we;
Tests: T1 T2 T3
12868 1/1 reg_we_check[7] = 1'b0;
Tests: T1 T2 T3
12869 1/1 reg_we_check[8] = control_gated_we;
Tests: T1 T2 T3
12870 1/1 reg_we_check[9] = addr_gated_we;
Tests: T1 T2 T3
12871 1/1 reg_we_check[10] = prog_type_en_gated_we;
Tests: T1 T2 T3
12872 1/1 reg_we_check[11] = erase_suspend_we;
Tests: T1 T2 T3
12873 1/1 reg_we_check[12] = region_cfg_regwen_0_we;
Tests: T1 T2 T3
12874 1/1 reg_we_check[13] = region_cfg_regwen_1_we;
Tests: T1 T2 T3
12875 1/1 reg_we_check[14] = region_cfg_regwen_2_we;
Tests: T1 T2 T3
12876 1/1 reg_we_check[15] = region_cfg_regwen_3_we;
Tests: T1 T2 T3
12877 1/1 reg_we_check[16] = region_cfg_regwen_4_we;
Tests: T1 T2 T3
12878 1/1 reg_we_check[17] = region_cfg_regwen_5_we;
Tests: T1 T2 T3
12879 1/1 reg_we_check[18] = region_cfg_regwen_6_we;
Tests: T1 T2 T3
12880 1/1 reg_we_check[19] = region_cfg_regwen_7_we;
Tests: T1 T2 T3
12881 1/1 reg_we_check[20] = mp_region_cfg_0_gated_we;
Tests: T1 T2 T3
12882 1/1 reg_we_check[21] = mp_region_cfg_1_gated_we;
Tests: T1 T2 T3
12883 1/1 reg_we_check[22] = mp_region_cfg_2_gated_we;
Tests: T1 T2 T3
12884 1/1 reg_we_check[23] = mp_region_cfg_3_gated_we;
Tests: T1 T2 T3
12885 1/1 reg_we_check[24] = mp_region_cfg_4_gated_we;
Tests: T1 T2 T3
12886 1/1 reg_we_check[25] = mp_region_cfg_5_gated_we;
Tests: T1 T2 T3
12887 1/1 reg_we_check[26] = mp_region_cfg_6_gated_we;
Tests: T1 T2 T3
12888 1/1 reg_we_check[27] = mp_region_cfg_7_gated_we;
Tests: T1 T2 T3
12889 1/1 reg_we_check[28] = mp_region_0_gated_we;
Tests: T1 T2 T3
12890 1/1 reg_we_check[29] = mp_region_1_gated_we;
Tests: T1 T2 T3
12891 1/1 reg_we_check[30] = mp_region_2_gated_we;
Tests: T1 T2 T3
12892 1/1 reg_we_check[31] = mp_region_3_gated_we;
Tests: T1 T2 T3
12893 1/1 reg_we_check[32] = mp_region_4_gated_we;
Tests: T1 T2 T3
12894 1/1 reg_we_check[33] = mp_region_5_gated_we;
Tests: T1 T2 T3
12895 1/1 reg_we_check[34] = mp_region_6_gated_we;
Tests: T1 T2 T3
12896 1/1 reg_we_check[35] = mp_region_7_gated_we;
Tests: T1 T2 T3
12897 1/1 reg_we_check[36] = default_region_we;
Tests: T1 T2 T3
12898 1/1 reg_we_check[37] = bank0_info0_regwen_0_we;
Tests: T1 T2 T3
12899 1/1 reg_we_check[38] = bank0_info0_regwen_1_we;
Tests: T1 T2 T3
12900 1/1 reg_we_check[39] = bank0_info0_regwen_2_we;
Tests: T1 T2 T3
12901 1/1 reg_we_check[40] = bank0_info0_regwen_3_we;
Tests: T1 T2 T3
12902 1/1 reg_we_check[41] = bank0_info0_regwen_4_we;
Tests: T1 T2 T3
12903 1/1 reg_we_check[42] = bank0_info0_regwen_5_we;
Tests: T1 T2 T3
12904 1/1 reg_we_check[43] = bank0_info0_regwen_6_we;
Tests: T1 T2 T3
12905 1/1 reg_we_check[44] = bank0_info0_regwen_7_we;
Tests: T1 T2 T3
12906 1/1 reg_we_check[45] = bank0_info0_regwen_8_we;
Tests: T1 T2 T3
12907 1/1 reg_we_check[46] = bank0_info0_regwen_9_we;
Tests: T1 T2 T3
12908 1/1 reg_we_check[47] = bank0_info0_page_cfg_0_gated_we;
Tests: T1 T2 T3
12909 1/1 reg_we_check[48] = bank0_info0_page_cfg_1_gated_we;
Tests: T1 T2 T3
12910 1/1 reg_we_check[49] = bank0_info0_page_cfg_2_gated_we;
Tests: T1 T2 T3
12911 1/1 reg_we_check[50] = bank0_info0_page_cfg_3_gated_we;
Tests: T1 T2 T3
12912 1/1 reg_we_check[51] = bank0_info0_page_cfg_4_gated_we;
Tests: T1 T2 T3
12913 1/1 reg_we_check[52] = bank0_info0_page_cfg_5_gated_we;
Tests: T1 T2 T3
12914 1/1 reg_we_check[53] = bank0_info0_page_cfg_6_gated_we;
Tests: T1 T2 T3
12915 1/1 reg_we_check[54] = bank0_info0_page_cfg_7_gated_we;
Tests: T1 T2 T3
12916 1/1 reg_we_check[55] = bank0_info0_page_cfg_8_gated_we;
Tests: T1 T2 T3
12917 1/1 reg_we_check[56] = bank0_info0_page_cfg_9_gated_we;
Tests: T1 T2 T3
12918 1/1 reg_we_check[57] = bank0_info1_regwen_we;
Tests: T1 T2 T3
12919 1/1 reg_we_check[58] = bank0_info1_page_cfg_gated_we;
Tests: T1 T2 T3
12920 1/1 reg_we_check[59] = bank0_info2_regwen_0_we;
Tests: T1 T2 T3
12921 1/1 reg_we_check[60] = bank0_info2_regwen_1_we;
Tests: T1 T2 T3
12922 1/1 reg_we_check[61] = bank0_info2_page_cfg_0_gated_we;
Tests: T1 T2 T3
12923 1/1 reg_we_check[62] = bank0_info2_page_cfg_1_gated_we;
Tests: T1 T2 T3
12924 1/1 reg_we_check[63] = bank1_info0_regwen_0_we;
Tests: T1 T2 T3
12925 1/1 reg_we_check[64] = bank1_info0_regwen_1_we;
Tests: T1 T2 T3
12926 1/1 reg_we_check[65] = bank1_info0_regwen_2_we;
Tests: T1 T2 T3
12927 1/1 reg_we_check[66] = bank1_info0_regwen_3_we;
Tests: T1 T2 T3
12928 1/1 reg_we_check[67] = bank1_info0_regwen_4_we;
Tests: T1 T2 T3
12929 1/1 reg_we_check[68] = bank1_info0_regwen_5_we;
Tests: T1 T2 T3
12930 1/1 reg_we_check[69] = bank1_info0_regwen_6_we;
Tests: T1 T2 T3
12931 1/1 reg_we_check[70] = bank1_info0_regwen_7_we;
Tests: T1 T2 T3
12932 1/1 reg_we_check[71] = bank1_info0_regwen_8_we;
Tests: T1 T2 T3
12933 1/1 reg_we_check[72] = bank1_info0_regwen_9_we;
Tests: T1 T2 T3
12934 1/1 reg_we_check[73] = bank1_info0_page_cfg_0_gated_we;
Tests: T1 T2 T3
12935 1/1 reg_we_check[74] = bank1_info0_page_cfg_1_gated_we;
Tests: T1 T2 T3
12936 1/1 reg_we_check[75] = bank1_info0_page_cfg_2_gated_we;
Tests: T1 T2 T3
12937 1/1 reg_we_check[76] = bank1_info0_page_cfg_3_gated_we;
Tests: T1 T2 T3
12938 1/1 reg_we_check[77] = bank1_info0_page_cfg_4_gated_we;
Tests: T1 T2 T3
12939 1/1 reg_we_check[78] = bank1_info0_page_cfg_5_gated_we;
Tests: T1 T2 T3
12940 1/1 reg_we_check[79] = bank1_info0_page_cfg_6_gated_we;
Tests: T1 T2 T3
12941 1/1 reg_we_check[80] = bank1_info0_page_cfg_7_gated_we;
Tests: T1 T2 T3
12942 1/1 reg_we_check[81] = bank1_info0_page_cfg_8_gated_we;
Tests: T1 T2 T3
12943 1/1 reg_we_check[82] = bank1_info0_page_cfg_9_gated_we;
Tests: T1 T2 T3
12944 1/1 reg_we_check[83] = bank1_info1_regwen_we;
Tests: T1 T2 T3
12945 1/1 reg_we_check[84] = bank1_info1_page_cfg_gated_we;
Tests: T1 T2 T3
12946 1/1 reg_we_check[85] = bank1_info2_regwen_0_we;
Tests: T1 T2 T3
12947 1/1 reg_we_check[86] = bank1_info2_regwen_1_we;
Tests: T1 T2 T3
12948 1/1 reg_we_check[87] = bank1_info2_page_cfg_0_gated_we;
Tests: T1 T2 T3
12949 1/1 reg_we_check[88] = bank1_info2_page_cfg_1_gated_we;
Tests: T1 T2 T3
12950 1/1 reg_we_check[89] = hw_info_cfg_override_we;
Tests: T1 T2 T3
12951 1/1 reg_we_check[90] = bank_cfg_regwen_we;
Tests: T1 T2 T3
12952 1/1 reg_we_check[91] = mp_bank_cfg_shadowed_gated_we;
Tests: T1 T2 T3
12953 1/1 reg_we_check[92] = op_status_we;
Tests: T1 T2 T3
12954 1/1 reg_we_check[93] = 1'b0;
Tests: T1 T2 T3
12955 1/1 reg_we_check[94] = 1'b0;
Tests: T1 T2 T3
12956 1/1 reg_we_check[95] = err_code_we;
Tests: T1 T2 T3
12957 1/1 reg_we_check[96] = 1'b0;
Tests: T1 T2 T3
12958 1/1 reg_we_check[97] = fault_status_we;
Tests: T1 T2 T3
12959 1/1 reg_we_check[98] = 1'b0;
Tests: T1 T2 T3
12960 1/1 reg_we_check[99] = ecc_single_err_cnt_we;
Tests: T1 T2 T3
12961 1/1 reg_we_check[100] = 1'b0;
Tests: T1 T2 T3
12962 1/1 reg_we_check[101] = 1'b0;
Tests: T1 T2 T3
12963 1/1 reg_we_check[102] = phy_alert_cfg_we;
Tests: T1 T2 T3
12964 1/1 reg_we_check[103] = 1'b0;
Tests: T1 T2 T3
12965 1/1 reg_we_check[104] = scratch_we;
Tests: T1 T2 T3
12966 1/1 reg_we_check[105] = fifo_lvl_we;
Tests: T1 T2 T3
12967 1/1 reg_we_check[106] = fifo_rst_we;
Tests: T1 T2 T3
12968 1/1 reg_we_check[107] = 1'b0;
Tests: T1 T2 T3
12969 end
12970
12971 // Read data return
12972 always_comb begin
12973 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
12974 1/1 unique case (1'b1)
Tests: T1 T2 T3
12975 addr_hit[0]: begin
12976 1/1 reg_rdata_next[0] = intr_state_prog_empty_qs;
Tests: T1 T2 T3
12977 1/1 reg_rdata_next[1] = intr_state_prog_lvl_qs;
Tests: T1 T2 T3
12978 1/1 reg_rdata_next[2] = intr_state_rd_full_qs;
Tests: T1 T2 T3
12979 1/1 reg_rdata_next[3] = intr_state_rd_lvl_qs;
Tests: T1 T2 T3
12980 1/1 reg_rdata_next[4] = intr_state_op_done_qs;
Tests: T1 T2 T3
12981 1/1 reg_rdata_next[5] = intr_state_corr_err_qs;
Tests: T1 T2 T3
12982 end
12983
12984 addr_hit[1]: begin
12985 1/1 reg_rdata_next[0] = intr_enable_prog_empty_qs;
Tests: T1 T2 T3
12986 1/1 reg_rdata_next[1] = intr_enable_prog_lvl_qs;
Tests: T1 T2 T3
12987 1/1 reg_rdata_next[2] = intr_enable_rd_full_qs;
Tests: T1 T2 T3
12988 1/1 reg_rdata_next[3] = intr_enable_rd_lvl_qs;
Tests: T1 T2 T3
12989 1/1 reg_rdata_next[4] = intr_enable_op_done_qs;
Tests: T1 T2 T3
12990 1/1 reg_rdata_next[5] = intr_enable_corr_err_qs;
Tests: T1 T2 T3
12991 end
12992
12993 addr_hit[2]: begin
12994 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
12995 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
12996 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
12997 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T3
12998 1/1 reg_rdata_next[4] = '0;
Tests: T1 T2 T3
12999 1/1 reg_rdata_next[5] = '0;
Tests: T1 T2 T3
13000 end
13001
13002 addr_hit[3]: begin
13003 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
13004 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
13005 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
13006 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T3
13007 1/1 reg_rdata_next[4] = '0;
Tests: T1 T2 T3
13008 end
13009
13010 addr_hit[4]: begin
13011 1/1 reg_rdata_next[3:0] = dis_qs;
Tests: T1 T2 T3
13012 end
13013
13014 addr_hit[5]: begin
13015 1/1 reg_rdata_next[31:0] = exec_qs;
Tests: T1 T2 T3
13016 end
13017
13018 addr_hit[6]: begin
13019 1/1 reg_rdata_next[0] = init_qs;
Tests: T1 T2 T3
13020 end
13021
13022 addr_hit[7]: begin
13023 1/1 reg_rdata_next[0] = ctrl_regwen_qs;
Tests: T1 T2 T3
13024 end
13025
13026 addr_hit[8]: begin
13027 1/1 reg_rdata_next[0] = control_start_qs;
Tests: T1 T2 T3
13028 1/1 reg_rdata_next[5:4] = control_op_qs;
Tests: T1 T2 T3
13029 1/1 reg_rdata_next[6] = control_prog_sel_qs;
Tests: T1 T2 T3
13030 1/1 reg_rdata_next[7] = control_erase_sel_qs;
Tests: T1 T2 T3
13031 1/1 reg_rdata_next[8] = control_partition_sel_qs;
Tests: T1 T2 T3
13032 1/1 reg_rdata_next[10:9] = control_info_sel_qs;
Tests: T1 T2 T3
13033 1/1 reg_rdata_next[27:16] = control_num_qs;
Tests: T1 T2 T3
13034 end
13035
13036 addr_hit[9]: begin
13037 1/1 reg_rdata_next[19:0] = addr_qs;
Tests: T1 T2 T3
13038 end
13039
13040 addr_hit[10]: begin
13041 1/1 reg_rdata_next[0] = prog_type_en_normal_qs;
Tests: T1 T2 T3
13042 1/1 reg_rdata_next[1] = prog_type_en_repair_qs;
Tests: T1 T2 T3
13043 end
13044
13045 addr_hit[11]: begin
13046 1/1 reg_rdata_next[0] = erase_suspend_qs;
Tests: T1 T2 T3
13047 end
13048
13049 addr_hit[12]: begin
13050 1/1 reg_rdata_next[0] = region_cfg_regwen_0_qs;
Tests: T1 T2 T3
13051 end
13052
13053 addr_hit[13]: begin
13054 1/1 reg_rdata_next[0] = region_cfg_regwen_1_qs;
Tests: T1 T2 T3
13055 end
13056
13057 addr_hit[14]: begin
13058 1/1 reg_rdata_next[0] = region_cfg_regwen_2_qs;
Tests: T1 T2 T3
13059 end
13060
13061 addr_hit[15]: begin
13062 1/1 reg_rdata_next[0] = region_cfg_regwen_3_qs;
Tests: T1 T2 T3
13063 end
13064
13065 addr_hit[16]: begin
13066 1/1 reg_rdata_next[0] = region_cfg_regwen_4_qs;
Tests: T1 T2 T3
13067 end
13068
13069 addr_hit[17]: begin
13070 1/1 reg_rdata_next[0] = region_cfg_regwen_5_qs;
Tests: T1 T2 T3
13071 end
13072
13073 addr_hit[18]: begin
13074 1/1 reg_rdata_next[0] = region_cfg_regwen_6_qs;
Tests: T1 T2 T3
13075 end
13076
13077 addr_hit[19]: begin
13078 1/1 reg_rdata_next[0] = region_cfg_regwen_7_qs;
Tests: T1 T2 T3
13079 end
13080
13081 addr_hit[20]: begin
13082 1/1 reg_rdata_next[3:0] = mp_region_cfg_0_en_0_qs;
Tests: T1 T2 T3
13083 1/1 reg_rdata_next[7:4] = mp_region_cfg_0_rd_en_0_qs;
Tests: T1 T2 T3
13084 1/1 reg_rdata_next[11:8] = mp_region_cfg_0_prog_en_0_qs;
Tests: T1 T2 T3
13085 1/1 reg_rdata_next[15:12] = mp_region_cfg_0_erase_en_0_qs;
Tests: T1 T2 T3
13086 1/1 reg_rdata_next[19:16] = mp_region_cfg_0_scramble_en_0_qs;
Tests: T1 T2 T3
13087 1/1 reg_rdata_next[23:20] = mp_region_cfg_0_ecc_en_0_qs;
Tests: T1 T2 T3
13088 1/1 reg_rdata_next[27:24] = mp_region_cfg_0_he_en_0_qs;
Tests: T1 T2 T3
13089 end
13090
13091 addr_hit[21]: begin
13092 1/1 reg_rdata_next[3:0] = mp_region_cfg_1_en_1_qs;
Tests: T1 T2 T3
13093 1/1 reg_rdata_next[7:4] = mp_region_cfg_1_rd_en_1_qs;
Tests: T1 T2 T3
13094 1/1 reg_rdata_next[11:8] = mp_region_cfg_1_prog_en_1_qs;
Tests: T1 T2 T3
13095 1/1 reg_rdata_next[15:12] = mp_region_cfg_1_erase_en_1_qs;
Tests: T1 T2 T3
13096 1/1 reg_rdata_next[19:16] = mp_region_cfg_1_scramble_en_1_qs;
Tests: T1 T2 T3
13097 1/1 reg_rdata_next[23:20] = mp_region_cfg_1_ecc_en_1_qs;
Tests: T1 T2 T3
13098 1/1 reg_rdata_next[27:24] = mp_region_cfg_1_he_en_1_qs;
Tests: T1 T2 T3
13099 end
13100
13101 addr_hit[22]: begin
13102 1/1 reg_rdata_next[3:0] = mp_region_cfg_2_en_2_qs;
Tests: T1 T2 T3
13103 1/1 reg_rdata_next[7:4] = mp_region_cfg_2_rd_en_2_qs;
Tests: T1 T2 T3
13104 1/1 reg_rdata_next[11:8] = mp_region_cfg_2_prog_en_2_qs;
Tests: T1 T2 T3
13105 1/1 reg_rdata_next[15:12] = mp_region_cfg_2_erase_en_2_qs;
Tests: T1 T2 T3
13106 1/1 reg_rdata_next[19:16] = mp_region_cfg_2_scramble_en_2_qs;
Tests: T1 T2 T3
13107 1/1 reg_rdata_next[23:20] = mp_region_cfg_2_ecc_en_2_qs;
Tests: T1 T2 T3
13108 1/1 reg_rdata_next[27:24] = mp_region_cfg_2_he_en_2_qs;
Tests: T1 T2 T3
13109 end
13110
13111 addr_hit[23]: begin
13112 1/1 reg_rdata_next[3:0] = mp_region_cfg_3_en_3_qs;
Tests: T1 T2 T3
13113 1/1 reg_rdata_next[7:4] = mp_region_cfg_3_rd_en_3_qs;
Tests: T1 T2 T3
13114 1/1 reg_rdata_next[11:8] = mp_region_cfg_3_prog_en_3_qs;
Tests: T1 T2 T3
13115 1/1 reg_rdata_next[15:12] = mp_region_cfg_3_erase_en_3_qs;
Tests: T1 T2 T3
13116 1/1 reg_rdata_next[19:16] = mp_region_cfg_3_scramble_en_3_qs;
Tests: T1 T2 T3
13117 1/1 reg_rdata_next[23:20] = mp_region_cfg_3_ecc_en_3_qs;
Tests: T1 T2 T3
13118 1/1 reg_rdata_next[27:24] = mp_region_cfg_3_he_en_3_qs;
Tests: T1 T2 T3
13119 end
13120
13121 addr_hit[24]: begin
13122 1/1 reg_rdata_next[3:0] = mp_region_cfg_4_en_4_qs;
Tests: T1 T2 T3
13123 1/1 reg_rdata_next[7:4] = mp_region_cfg_4_rd_en_4_qs;
Tests: T1 T2 T3
13124 1/1 reg_rdata_next[11:8] = mp_region_cfg_4_prog_en_4_qs;
Tests: T1 T2 T3
13125 1/1 reg_rdata_next[15:12] = mp_region_cfg_4_erase_en_4_qs;
Tests: T1 T2 T3
13126 1/1 reg_rdata_next[19:16] = mp_region_cfg_4_scramble_en_4_qs;
Tests: T1 T2 T3
13127 1/1 reg_rdata_next[23:20] = mp_region_cfg_4_ecc_en_4_qs;
Tests: T1 T2 T3
13128 1/1 reg_rdata_next[27:24] = mp_region_cfg_4_he_en_4_qs;
Tests: T1 T2 T3
13129 end
13130
13131 addr_hit[25]: begin
13132 1/1 reg_rdata_next[3:0] = mp_region_cfg_5_en_5_qs;
Tests: T1 T2 T3
13133 1/1 reg_rdata_next[7:4] = mp_region_cfg_5_rd_en_5_qs;
Tests: T1 T2 T3
13134 1/1 reg_rdata_next[11:8] = mp_region_cfg_5_prog_en_5_qs;
Tests: T1 T2 T3
13135 1/1 reg_rdata_next[15:12] = mp_region_cfg_5_erase_en_5_qs;
Tests: T1 T2 T3
13136 1/1 reg_rdata_next[19:16] = mp_region_cfg_5_scramble_en_5_qs;
Tests: T1 T2 T3
13137 1/1 reg_rdata_next[23:20] = mp_region_cfg_5_ecc_en_5_qs;
Tests: T1 T2 T3
13138 1/1 reg_rdata_next[27:24] = mp_region_cfg_5_he_en_5_qs;
Tests: T1 T2 T3
13139 end
13140
13141 addr_hit[26]: begin
13142 1/1 reg_rdata_next[3:0] = mp_region_cfg_6_en_6_qs;
Tests: T1 T2 T3
13143 1/1 reg_rdata_next[7:4] = mp_region_cfg_6_rd_en_6_qs;
Tests: T1 T2 T3
13144 1/1 reg_rdata_next[11:8] = mp_region_cfg_6_prog_en_6_qs;
Tests: T1 T2 T3
13145 1/1 reg_rdata_next[15:12] = mp_region_cfg_6_erase_en_6_qs;
Tests: T1 T2 T3
13146 1/1 reg_rdata_next[19:16] = mp_region_cfg_6_scramble_en_6_qs;
Tests: T1 T2 T3
13147 1/1 reg_rdata_next[23:20] = mp_region_cfg_6_ecc_en_6_qs;
Tests: T1 T2 T3
13148 1/1 reg_rdata_next[27:24] = mp_region_cfg_6_he_en_6_qs;
Tests: T1 T2 T3
13149 end
13150
13151 addr_hit[27]: begin
13152 1/1 reg_rdata_next[3:0] = mp_region_cfg_7_en_7_qs;
Tests: T1 T2 T3
13153 1/1 reg_rdata_next[7:4] = mp_region_cfg_7_rd_en_7_qs;
Tests: T1 T2 T3
13154 1/1 reg_rdata_next[11:8] = mp_region_cfg_7_prog_en_7_qs;
Tests: T1 T2 T3
13155 1/1 reg_rdata_next[15:12] = mp_region_cfg_7_erase_en_7_qs;
Tests: T1 T2 T3
13156 1/1 reg_rdata_next[19:16] = mp_region_cfg_7_scramble_en_7_qs;
Tests: T1 T2 T3
13157 1/1 reg_rdata_next[23:20] = mp_region_cfg_7_ecc_en_7_qs;
Tests: T1 T2 T3
13158 1/1 reg_rdata_next[27:24] = mp_region_cfg_7_he_en_7_qs;
Tests: T1 T2 T3
13159 end
13160
13161 addr_hit[28]: begin
13162 1/1 reg_rdata_next[8:0] = mp_region_0_base_0_qs;
Tests: T1 T2 T3
13163 1/1 reg_rdata_next[18:9] = mp_region_0_size_0_qs;
Tests: T1 T2 T3
13164 end
13165
13166 addr_hit[29]: begin
13167 1/1 reg_rdata_next[8:0] = mp_region_1_base_1_qs;
Tests: T1 T2 T3
13168 1/1 reg_rdata_next[18:9] = mp_region_1_size_1_qs;
Tests: T1 T2 T3
13169 end
13170
13171 addr_hit[30]: begin
13172 1/1 reg_rdata_next[8:0] = mp_region_2_base_2_qs;
Tests: T1 T2 T3
13173 1/1 reg_rdata_next[18:9] = mp_region_2_size_2_qs;
Tests: T1 T2 T3
13174 end
13175
13176 addr_hit[31]: begin
13177 1/1 reg_rdata_next[8:0] = mp_region_3_base_3_qs;
Tests: T1 T2 T3
13178 1/1 reg_rdata_next[18:9] = mp_region_3_size_3_qs;
Tests: T1 T2 T3
13179 end
13180
13181 addr_hit[32]: begin
13182 1/1 reg_rdata_next[8:0] = mp_region_4_base_4_qs;
Tests: T1 T2 T3
13183 1/1 reg_rdata_next[18:9] = mp_region_4_size_4_qs;
Tests: T1 T2 T3
13184 end
13185
13186 addr_hit[33]: begin
13187 1/1 reg_rdata_next[8:0] = mp_region_5_base_5_qs;
Tests: T1 T2 T3
13188 1/1 reg_rdata_next[18:9] = mp_region_5_size_5_qs;
Tests: T1 T2 T3
13189 end
13190
13191 addr_hit[34]: begin
13192 1/1 reg_rdata_next[8:0] = mp_region_6_base_6_qs;
Tests: T1 T2 T3
13193 1/1 reg_rdata_next[18:9] = mp_region_6_size_6_qs;
Tests: T1 T2 T3
13194 end
13195
13196 addr_hit[35]: begin
13197 1/1 reg_rdata_next[8:0] = mp_region_7_base_7_qs;
Tests: T1 T2 T3
13198 1/1 reg_rdata_next[18:9] = mp_region_7_size_7_qs;
Tests: T1 T2 T3
13199 end
13200
13201 addr_hit[36]: begin
13202 1/1 reg_rdata_next[3:0] = default_region_rd_en_qs;
Tests: T1 T2 T3
13203 1/1 reg_rdata_next[7:4] = default_region_prog_en_qs;
Tests: T1 T2 T3
13204 1/1 reg_rdata_next[11:8] = default_region_erase_en_qs;
Tests: T1 T2 T3
13205 1/1 reg_rdata_next[15:12] = default_region_scramble_en_qs;
Tests: T1 T2 T3
13206 1/1 reg_rdata_next[19:16] = default_region_ecc_en_qs;
Tests: T1 T2 T3
13207 1/1 reg_rdata_next[23:20] = default_region_he_en_qs;
Tests: T1 T2 T3
13208 end
13209
13210 addr_hit[37]: begin
13211 1/1 reg_rdata_next[0] = bank0_info0_regwen_0_qs;
Tests: T1 T2 T3
13212 end
13213
13214 addr_hit[38]: begin
13215 1/1 reg_rdata_next[0] = bank0_info0_regwen_1_qs;
Tests: T1 T2 T3
13216 end
13217
13218 addr_hit[39]: begin
13219 1/1 reg_rdata_next[0] = bank0_info0_regwen_2_qs;
Tests: T1 T2 T3
13220 end
13221
13222 addr_hit[40]: begin
13223 1/1 reg_rdata_next[0] = bank0_info0_regwen_3_qs;
Tests: T1 T2 T3
13224 end
13225
13226 addr_hit[41]: begin
13227 1/1 reg_rdata_next[0] = bank0_info0_regwen_4_qs;
Tests: T1 T2 T3
13228 end
13229
13230 addr_hit[42]: begin
13231 1/1 reg_rdata_next[0] = bank0_info0_regwen_5_qs;
Tests: T1 T2 T3
13232 end
13233
13234 addr_hit[43]: begin
13235 1/1 reg_rdata_next[0] = bank0_info0_regwen_6_qs;
Tests: T1 T2 T3
13236 end
13237
13238 addr_hit[44]: begin
13239 1/1 reg_rdata_next[0] = bank0_info0_regwen_7_qs;
Tests: T1 T2 T3
13240 end
13241
13242 addr_hit[45]: begin
13243 1/1 reg_rdata_next[0] = bank0_info0_regwen_8_qs;
Tests: T1 T2 T3
13244 end
13245
13246 addr_hit[46]: begin
13247 1/1 reg_rdata_next[0] = bank0_info0_regwen_9_qs;
Tests: T1 T2 T3
13248 end
13249
13250 addr_hit[47]: begin
13251 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_0_en_0_qs;
Tests: T1 T2 T3
13252 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_0_rd_en_0_qs;
Tests: T1 T2 T3
13253 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_0_prog_en_0_qs;
Tests: T1 T2 T3
13254 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_0_erase_en_0_qs;
Tests: T1 T2 T3
13255 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_0_scramble_en_0_qs;
Tests: T1 T2 T3
13256 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_0_ecc_en_0_qs;
Tests: T1 T2 T3
13257 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_0_he_en_0_qs;
Tests: T1 T2 T3
13258 end
13259
13260 addr_hit[48]: begin
13261 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_1_en_1_qs;
Tests: T1 T2 T3
13262 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_1_rd_en_1_qs;
Tests: T1 T2 T3
13263 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_1_prog_en_1_qs;
Tests: T1 T2 T3
13264 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_1_erase_en_1_qs;
Tests: T1 T2 T3
13265 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_1_scramble_en_1_qs;
Tests: T1 T2 T3
13266 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_1_ecc_en_1_qs;
Tests: T1 T2 T3
13267 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_1_he_en_1_qs;
Tests: T1 T2 T3
13268 end
13269
13270 addr_hit[49]: begin
13271 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_2_en_2_qs;
Tests: T1 T2 T3
13272 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_2_rd_en_2_qs;
Tests: T1 T2 T3
13273 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_2_prog_en_2_qs;
Tests: T1 T2 T3
13274 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_2_erase_en_2_qs;
Tests: T1 T2 T3
13275 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_2_scramble_en_2_qs;
Tests: T1 T2 T3
13276 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_2_ecc_en_2_qs;
Tests: T1 T2 T3
13277 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_2_he_en_2_qs;
Tests: T1 T2 T3
13278 end
13279
13280 addr_hit[50]: begin
13281 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_3_en_3_qs;
Tests: T1 T2 T3
13282 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_3_rd_en_3_qs;
Tests: T1 T2 T3
13283 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_3_prog_en_3_qs;
Tests: T1 T2 T3
13284 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_3_erase_en_3_qs;
Tests: T1 T2 T3
13285 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_3_scramble_en_3_qs;
Tests: T1 T2 T3
13286 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_3_ecc_en_3_qs;
Tests: T1 T2 T3
13287 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_3_he_en_3_qs;
Tests: T1 T2 T3
13288 end
13289
13290 addr_hit[51]: begin
13291 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_4_en_4_qs;
Tests: T1 T2 T3
13292 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_4_rd_en_4_qs;
Tests: T1 T2 T3
13293 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_4_prog_en_4_qs;
Tests: T1 T2 T3
13294 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_4_erase_en_4_qs;
Tests: T1 T2 T3
13295 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_4_scramble_en_4_qs;
Tests: T1 T2 T3
13296 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_4_ecc_en_4_qs;
Tests: T1 T2 T3
13297 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_4_he_en_4_qs;
Tests: T1 T2 T3
13298 end
13299
13300 addr_hit[52]: begin
13301 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_5_en_5_qs;
Tests: T1 T2 T3
13302 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_5_rd_en_5_qs;
Tests: T1 T2 T3
13303 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_5_prog_en_5_qs;
Tests: T1 T2 T3
13304 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_5_erase_en_5_qs;
Tests: T1 T2 T3
13305 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_5_scramble_en_5_qs;
Tests: T1 T2 T3
13306 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_5_ecc_en_5_qs;
Tests: T1 T2 T3
13307 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_5_he_en_5_qs;
Tests: T1 T2 T3
13308 end
13309
13310 addr_hit[53]: begin
13311 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_6_en_6_qs;
Tests: T1 T2 T3
13312 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_6_rd_en_6_qs;
Tests: T1 T2 T3
13313 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_6_prog_en_6_qs;
Tests: T1 T2 T3
13314 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_6_erase_en_6_qs;
Tests: T1 T2 T3
13315 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_6_scramble_en_6_qs;
Tests: T1 T2 T3
13316 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_6_ecc_en_6_qs;
Tests: T1 T2 T3
13317 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_6_he_en_6_qs;
Tests: T1 T2 T3
13318 end
13319
13320 addr_hit[54]: begin
13321 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_7_en_7_qs;
Tests: T1 T2 T3
13322 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_7_rd_en_7_qs;
Tests: T1 T2 T3
13323 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_7_prog_en_7_qs;
Tests: T1 T2 T3
13324 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_7_erase_en_7_qs;
Tests: T1 T2 T3
13325 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_7_scramble_en_7_qs;
Tests: T1 T2 T3
13326 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_7_ecc_en_7_qs;
Tests: T1 T2 T3
13327 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_7_he_en_7_qs;
Tests: T1 T2 T3
13328 end
13329
13330 addr_hit[55]: begin
13331 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_8_en_8_qs;
Tests: T1 T2 T3
13332 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_8_rd_en_8_qs;
Tests: T1 T2 T3
13333 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_8_prog_en_8_qs;
Tests: T1 T2 T3
13334 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_8_erase_en_8_qs;
Tests: T1 T2 T3
13335 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_8_scramble_en_8_qs;
Tests: T1 T2 T3
13336 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_8_ecc_en_8_qs;
Tests: T1 T2 T3
13337 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_8_he_en_8_qs;
Tests: T1 T2 T3
13338 end
13339
13340 addr_hit[56]: begin
13341 1/1 reg_rdata_next[3:0] = bank0_info0_page_cfg_9_en_9_qs;
Tests: T1 T2 T3
13342 1/1 reg_rdata_next[7:4] = bank0_info0_page_cfg_9_rd_en_9_qs;
Tests: T1 T2 T3
13343 1/1 reg_rdata_next[11:8] = bank0_info0_page_cfg_9_prog_en_9_qs;
Tests: T1 T2 T3
13344 1/1 reg_rdata_next[15:12] = bank0_info0_page_cfg_9_erase_en_9_qs;
Tests: T1 T2 T3
13345 1/1 reg_rdata_next[19:16] = bank0_info0_page_cfg_9_scramble_en_9_qs;
Tests: T1 T2 T3
13346 1/1 reg_rdata_next[23:20] = bank0_info0_page_cfg_9_ecc_en_9_qs;
Tests: T1 T2 T3
13347 1/1 reg_rdata_next[27:24] = bank0_info0_page_cfg_9_he_en_9_qs;
Tests: T1 T2 T3
13348 end
13349
13350 addr_hit[57]: begin
13351 1/1 reg_rdata_next[0] = bank0_info1_regwen_qs;
Tests: T1 T2 T3
13352 end
13353
13354 addr_hit[58]: begin
13355 1/1 reg_rdata_next[3:0] = bank0_info1_page_cfg_en_0_qs;
Tests: T1 T2 T3
13356 1/1 reg_rdata_next[7:4] = bank0_info1_page_cfg_rd_en_0_qs;
Tests: T1 T2 T3
13357 1/1 reg_rdata_next[11:8] = bank0_info1_page_cfg_prog_en_0_qs;
Tests: T1 T2 T3
13358 1/1 reg_rdata_next[15:12] = bank0_info1_page_cfg_erase_en_0_qs;
Tests: T1 T2 T3
13359 1/1 reg_rdata_next[19:16] = bank0_info1_page_cfg_scramble_en_0_qs;
Tests: T1 T2 T3
13360 1/1 reg_rdata_next[23:20] = bank0_info1_page_cfg_ecc_en_0_qs;
Tests: T1 T2 T3
13361 1/1 reg_rdata_next[27:24] = bank0_info1_page_cfg_he_en_0_qs;
Tests: T1 T2 T3
13362 end
13363
13364 addr_hit[59]: begin
13365 1/1 reg_rdata_next[0] = bank0_info2_regwen_0_qs;
Tests: T1 T2 T3
13366 end
13367
13368 addr_hit[60]: begin
13369 1/1 reg_rdata_next[0] = bank0_info2_regwen_1_qs;
Tests: T1 T2 T3
13370 end
13371
13372 addr_hit[61]: begin
13373 1/1 reg_rdata_next[3:0] = bank0_info2_page_cfg_0_en_0_qs;
Tests: T1 T2 T3
13374 1/1 reg_rdata_next[7:4] = bank0_info2_page_cfg_0_rd_en_0_qs;
Tests: T1 T2 T3
13375 1/1 reg_rdata_next[11:8] = bank0_info2_page_cfg_0_prog_en_0_qs;
Tests: T1 T2 T3
13376 1/1 reg_rdata_next[15:12] = bank0_info2_page_cfg_0_erase_en_0_qs;
Tests: T1 T2 T3
13377 1/1 reg_rdata_next[19:16] = bank0_info2_page_cfg_0_scramble_en_0_qs;
Tests: T1 T2 T3
13378 1/1 reg_rdata_next[23:20] = bank0_info2_page_cfg_0_ecc_en_0_qs;
Tests: T1 T2 T3
13379 1/1 reg_rdata_next[27:24] = bank0_info2_page_cfg_0_he_en_0_qs;
Tests: T1 T2 T3
13380 end
13381
13382 addr_hit[62]: begin
13383 1/1 reg_rdata_next[3:0] = bank0_info2_page_cfg_1_en_1_qs;
Tests: T1 T2 T3
13384 1/1 reg_rdata_next[7:4] = bank0_info2_page_cfg_1_rd_en_1_qs;
Tests: T1 T2 T3
13385 1/1 reg_rdata_next[11:8] = bank0_info2_page_cfg_1_prog_en_1_qs;
Tests: T1 T2 T3
13386 1/1 reg_rdata_next[15:12] = bank0_info2_page_cfg_1_erase_en_1_qs;
Tests: T1 T2 T3
13387 1/1 reg_rdata_next[19:16] = bank0_info2_page_cfg_1_scramble_en_1_qs;
Tests: T1 T2 T3
13388 1/1 reg_rdata_next[23:20] = bank0_info2_page_cfg_1_ecc_en_1_qs;
Tests: T1 T2 T3
13389 1/1 reg_rdata_next[27:24] = bank0_info2_page_cfg_1_he_en_1_qs;
Tests: T1 T2 T3
13390 end
13391
13392 addr_hit[63]: begin
13393 1/1 reg_rdata_next[0] = bank1_info0_regwen_0_qs;
Tests: T1 T2 T3
13394 end
13395
13396 addr_hit[64]: begin
13397 1/1 reg_rdata_next[0] = bank1_info0_regwen_1_qs;
Tests: T1 T2 T3
13398 end
13399
13400 addr_hit[65]: begin
13401 1/1 reg_rdata_next[0] = bank1_info0_regwen_2_qs;
Tests: T1 T2 T3
13402 end
13403
13404 addr_hit[66]: begin
13405 1/1 reg_rdata_next[0] = bank1_info0_regwen_3_qs;
Tests: T1 T2 T3
13406 end
13407
13408 addr_hit[67]: begin
13409 1/1 reg_rdata_next[0] = bank1_info0_regwen_4_qs;
Tests: T1 T2 T3
13410 end
13411
13412 addr_hit[68]: begin
13413 1/1 reg_rdata_next[0] = bank1_info0_regwen_5_qs;
Tests: T1 T2 T3
13414 end
13415
13416 addr_hit[69]: begin
13417 1/1 reg_rdata_next[0] = bank1_info0_regwen_6_qs;
Tests: T1 T2 T3
13418 end
13419
13420 addr_hit[70]: begin
13421 1/1 reg_rdata_next[0] = bank1_info0_regwen_7_qs;
Tests: T1 T2 T3
13422 end
13423
13424 addr_hit[71]: begin
13425 1/1 reg_rdata_next[0] = bank1_info0_regwen_8_qs;
Tests: T1 T2 T3
13426 end
13427
13428 addr_hit[72]: begin
13429 1/1 reg_rdata_next[0] = bank1_info0_regwen_9_qs;
Tests: T1 T2 T3
13430 end
13431
13432 addr_hit[73]: begin
13433 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_0_en_0_qs;
Tests: T1 T2 T3
13434 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_0_rd_en_0_qs;
Tests: T1 T2 T3
13435 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_0_prog_en_0_qs;
Tests: T1 T2 T3
13436 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_0_erase_en_0_qs;
Tests: T1 T2 T3
13437 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_0_scramble_en_0_qs;
Tests: T1 T2 T3
13438 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_0_ecc_en_0_qs;
Tests: T1 T2 T3
13439 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_0_he_en_0_qs;
Tests: T1 T2 T3
13440 end
13441
13442 addr_hit[74]: begin
13443 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_1_en_1_qs;
Tests: T1 T2 T3
13444 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_1_rd_en_1_qs;
Tests: T1 T2 T3
13445 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_1_prog_en_1_qs;
Tests: T1 T2 T3
13446 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_1_erase_en_1_qs;
Tests: T1 T2 T3
13447 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_1_scramble_en_1_qs;
Tests: T1 T2 T3
13448 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_1_ecc_en_1_qs;
Tests: T1 T2 T3
13449 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_1_he_en_1_qs;
Tests: T1 T2 T3
13450 end
13451
13452 addr_hit[75]: begin
13453 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_2_en_2_qs;
Tests: T1 T2 T3
13454 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_2_rd_en_2_qs;
Tests: T1 T2 T3
13455 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_2_prog_en_2_qs;
Tests: T1 T2 T3
13456 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_2_erase_en_2_qs;
Tests: T1 T2 T3
13457 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_2_scramble_en_2_qs;
Tests: T1 T2 T3
13458 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_2_ecc_en_2_qs;
Tests: T1 T2 T3
13459 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_2_he_en_2_qs;
Tests: T1 T2 T3
13460 end
13461
13462 addr_hit[76]: begin
13463 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_3_en_3_qs;
Tests: T1 T2 T3
13464 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_3_rd_en_3_qs;
Tests: T1 T2 T3
13465 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_3_prog_en_3_qs;
Tests: T1 T2 T3
13466 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_3_erase_en_3_qs;
Tests: T1 T2 T3
13467 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_3_scramble_en_3_qs;
Tests: T1 T2 T3
13468 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_3_ecc_en_3_qs;
Tests: T1 T2 T3
13469 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_3_he_en_3_qs;
Tests: T1 T2 T3
13470 end
13471
13472 addr_hit[77]: begin
13473 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_4_en_4_qs;
Tests: T1 T2 T3
13474 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_4_rd_en_4_qs;
Tests: T1 T2 T3
13475 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_4_prog_en_4_qs;
Tests: T1 T2 T3
13476 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_4_erase_en_4_qs;
Tests: T1 T2 T3
13477 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_4_scramble_en_4_qs;
Tests: T1 T2 T3
13478 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_4_ecc_en_4_qs;
Tests: T1 T2 T3
13479 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_4_he_en_4_qs;
Tests: T1 T2 T3
13480 end
13481
13482 addr_hit[78]: begin
13483 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_5_en_5_qs;
Tests: T1 T2 T3
13484 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_5_rd_en_5_qs;
Tests: T1 T2 T3
13485 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_5_prog_en_5_qs;
Tests: T1 T2 T3
13486 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_5_erase_en_5_qs;
Tests: T1 T2 T3
13487 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_5_scramble_en_5_qs;
Tests: T1 T2 T3
13488 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_5_ecc_en_5_qs;
Tests: T1 T2 T3
13489 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_5_he_en_5_qs;
Tests: T1 T2 T3
13490 end
13491
13492 addr_hit[79]: begin
13493 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_6_en_6_qs;
Tests: T1 T2 T3
13494 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_6_rd_en_6_qs;
Tests: T1 T2 T3
13495 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_6_prog_en_6_qs;
Tests: T1 T2 T3
13496 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_6_erase_en_6_qs;
Tests: T1 T2 T3
13497 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_6_scramble_en_6_qs;
Tests: T1 T2 T3
13498 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_6_ecc_en_6_qs;
Tests: T1 T2 T3
13499 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_6_he_en_6_qs;
Tests: T1 T2 T3
13500 end
13501
13502 addr_hit[80]: begin
13503 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_7_en_7_qs;
Tests: T1 T2 T3
13504 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_7_rd_en_7_qs;
Tests: T1 T2 T3
13505 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_7_prog_en_7_qs;
Tests: T1 T2 T3
13506 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_7_erase_en_7_qs;
Tests: T1 T2 T3
13507 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_7_scramble_en_7_qs;
Tests: T1 T2 T3
13508 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_7_ecc_en_7_qs;
Tests: T1 T2 T3
13509 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_7_he_en_7_qs;
Tests: T1 T2 T3
13510 end
13511
13512 addr_hit[81]: begin
13513 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_8_en_8_qs;
Tests: T1 T2 T3
13514 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_8_rd_en_8_qs;
Tests: T1 T2 T3
13515 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_8_prog_en_8_qs;
Tests: T1 T2 T3
13516 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_8_erase_en_8_qs;
Tests: T1 T2 T3
13517 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_8_scramble_en_8_qs;
Tests: T1 T2 T3
13518 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_8_ecc_en_8_qs;
Tests: T1 T2 T3
13519 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_8_he_en_8_qs;
Tests: T1 T2 T3
13520 end
13521
13522 addr_hit[82]: begin
13523 1/1 reg_rdata_next[3:0] = bank1_info0_page_cfg_9_en_9_qs;
Tests: T1 T2 T3
13524 1/1 reg_rdata_next[7:4] = bank1_info0_page_cfg_9_rd_en_9_qs;
Tests: T1 T2 T3
13525 1/1 reg_rdata_next[11:8] = bank1_info0_page_cfg_9_prog_en_9_qs;
Tests: T1 T2 T3
13526 1/1 reg_rdata_next[15:12] = bank1_info0_page_cfg_9_erase_en_9_qs;
Tests: T1 T2 T3
13527 1/1 reg_rdata_next[19:16] = bank1_info0_page_cfg_9_scramble_en_9_qs;
Tests: T1 T2 T3
13528 1/1 reg_rdata_next[23:20] = bank1_info0_page_cfg_9_ecc_en_9_qs;
Tests: T1 T2 T3
13529 1/1 reg_rdata_next[27:24] = bank1_info0_page_cfg_9_he_en_9_qs;
Tests: T1 T2 T3
13530 end
13531
13532 addr_hit[83]: begin
13533 1/1 reg_rdata_next[0] = bank1_info1_regwen_qs;
Tests: T1 T2 T3
13534 end
13535
13536 addr_hit[84]: begin
13537 1/1 reg_rdata_next[3:0] = bank1_info1_page_cfg_en_0_qs;
Tests: T1 T2 T3
13538 1/1 reg_rdata_next[7:4] = bank1_info1_page_cfg_rd_en_0_qs;
Tests: T1 T2 T3
13539 1/1 reg_rdata_next[11:8] = bank1_info1_page_cfg_prog_en_0_qs;
Tests: T1 T2 T3
13540 1/1 reg_rdata_next[15:12] = bank1_info1_page_cfg_erase_en_0_qs;
Tests: T1 T2 T3
13541 1/1 reg_rdata_next[19:16] = bank1_info1_page_cfg_scramble_en_0_qs;
Tests: T1 T2 T3
13542 1/1 reg_rdata_next[23:20] = bank1_info1_page_cfg_ecc_en_0_qs;
Tests: T1 T2 T3
13543 1/1 reg_rdata_next[27:24] = bank1_info1_page_cfg_he_en_0_qs;
Tests: T1 T2 T3
13544 end
13545
13546 addr_hit[85]: begin
13547 1/1 reg_rdata_next[0] = bank1_info2_regwen_0_qs;
Tests: T1 T2 T3
13548 end
13549
13550 addr_hit[86]: begin
13551 1/1 reg_rdata_next[0] = bank1_info2_regwen_1_qs;
Tests: T1 T2 T3
13552 end
13553
13554 addr_hit[87]: begin
13555 1/1 reg_rdata_next[3:0] = bank1_info2_page_cfg_0_en_0_qs;
Tests: T1 T2 T3
13556 1/1 reg_rdata_next[7:4] = bank1_info2_page_cfg_0_rd_en_0_qs;
Tests: T1 T2 T3
13557 1/1 reg_rdata_next[11:8] = bank1_info2_page_cfg_0_prog_en_0_qs;
Tests: T1 T2 T3
13558 1/1 reg_rdata_next[15:12] = bank1_info2_page_cfg_0_erase_en_0_qs;
Tests: T1 T2 T3
13559 1/1 reg_rdata_next[19:16] = bank1_info2_page_cfg_0_scramble_en_0_qs;
Tests: T1 T2 T3
13560 1/1 reg_rdata_next[23:20] = bank1_info2_page_cfg_0_ecc_en_0_qs;
Tests: T1 T2 T3
13561 1/1 reg_rdata_next[27:24] = bank1_info2_page_cfg_0_he_en_0_qs;
Tests: T1 T2 T3
13562 end
13563
13564 addr_hit[88]: begin
13565 1/1 reg_rdata_next[3:0] = bank1_info2_page_cfg_1_en_1_qs;
Tests: T1 T2 T3
13566 1/1 reg_rdata_next[7:4] = bank1_info2_page_cfg_1_rd_en_1_qs;
Tests: T1 T2 T3
13567 1/1 reg_rdata_next[11:8] = bank1_info2_page_cfg_1_prog_en_1_qs;
Tests: T1 T2 T3
13568 1/1 reg_rdata_next[15:12] = bank1_info2_page_cfg_1_erase_en_1_qs;
Tests: T1 T2 T3
13569 1/1 reg_rdata_next[19:16] = bank1_info2_page_cfg_1_scramble_en_1_qs;
Tests: T1 T2 T3
13570 1/1 reg_rdata_next[23:20] = bank1_info2_page_cfg_1_ecc_en_1_qs;
Tests: T1 T2 T3
13571 1/1 reg_rdata_next[27:24] = bank1_info2_page_cfg_1_he_en_1_qs;
Tests: T1 T2 T3
13572 end
13573
13574 addr_hit[89]: begin
13575 1/1 reg_rdata_next[3:0] = hw_info_cfg_override_scramble_dis_qs;
Tests: T1 T2 T3
13576 1/1 reg_rdata_next[7:4] = hw_info_cfg_override_ecc_dis_qs;
Tests: T1 T2 T3
13577 end
13578
13579 addr_hit[90]: begin
13580 1/1 reg_rdata_next[0] = bank_cfg_regwen_qs;
Tests: T1 T2 T3
13581 end
13582
13583 addr_hit[91]: begin
13584 1/1 reg_rdata_next[0] = mp_bank_cfg_shadowed_erase_en_0_qs;
Tests: T1 T2 T3
13585 1/1 reg_rdata_next[1] = mp_bank_cfg_shadowed_erase_en_1_qs;
Tests: T1 T2 T3
13586 end
13587
13588 addr_hit[92]: begin
13589 1/1 reg_rdata_next[0] = op_status_done_qs;
Tests: T1 T2 T3
13590 1/1 reg_rdata_next[1] = op_status_err_qs;
Tests: T1 T2 T3
13591 end
13592
13593 addr_hit[93]: begin
13594 1/1 reg_rdata_next[0] = status_rd_full_qs;
Tests: T1 T2 T3
13595 1/1 reg_rdata_next[1] = status_rd_empty_qs;
Tests: T1 T2 T3
13596 1/1 reg_rdata_next[2] = status_prog_full_qs;
Tests: T1 T2 T3
13597 1/1 reg_rdata_next[3] = status_prog_empty_qs;
Tests: T1 T2 T3
13598 1/1 reg_rdata_next[4] = status_init_wip_qs;
Tests: T1 T2 T3
13599 1/1 reg_rdata_next[5] = status_initialized_qs;
Tests: T1 T2 T3
13600 end
13601
13602 addr_hit[94]: begin
13603 1/1 reg_rdata_next[10:0] = debug_state_qs;
Tests: T1 T2 T3
13604 end
13605
13606 addr_hit[95]: begin
13607 1/1 reg_rdata_next[0] = err_code_op_err_qs;
Tests: T1 T2 T3
13608 1/1 reg_rdata_next[1] = err_code_mp_err_qs;
Tests: T1 T2 T3
13609 1/1 reg_rdata_next[2] = err_code_rd_err_qs;
Tests: T1 T2 T3
13610 1/1 reg_rdata_next[3] = err_code_prog_err_qs;
Tests: T1 T2 T3
13611 1/1 reg_rdata_next[4] = err_code_prog_win_err_qs;
Tests: T1 T2 T3
13612 1/1 reg_rdata_next[5] = err_code_prog_type_err_qs;
Tests: T1 T2 T3
13613 1/1 reg_rdata_next[6] = err_code_update_err_qs;
Tests: T1 T2 T3
13614 1/1 reg_rdata_next[7] = err_code_macro_err_qs;
Tests: T1 T2 T3
13615 end
13616
13617 addr_hit[96]: begin
13618 1/1 reg_rdata_next[0] = std_fault_status_reg_intg_err_qs;
Tests: T1 T2 T3
13619 1/1 reg_rdata_next[1] = std_fault_status_prog_intg_err_qs;
Tests: T1 T2 T3
13620 1/1 reg_rdata_next[2] = std_fault_status_lcmgr_err_qs;
Tests: T1 T2 T3
13621 1/1 reg_rdata_next[3] = std_fault_status_lcmgr_intg_err_qs;
Tests: T1 T2 T3
13622 1/1 reg_rdata_next[4] = std_fault_status_arb_fsm_err_qs;
Tests: T1 T2 T3
13623 1/1 reg_rdata_next[5] = std_fault_status_storage_err_qs;
Tests: T1 T2 T3
13624 1/1 reg_rdata_next[6] = std_fault_status_phy_fsm_err_qs;
Tests: T1 T2 T3
13625 1/1 reg_rdata_next[7] = std_fault_status_ctrl_cnt_err_qs;
Tests: T1 T2 T3
13626 1/1 reg_rdata_next[8] = std_fault_status_fifo_err_qs;
Tests: T1 T2 T3
13627 end
13628
13629 addr_hit[97]: begin
13630 1/1 reg_rdata_next[0] = fault_status_op_err_qs;
Tests: T1 T2 T3
13631 1/1 reg_rdata_next[1] = fault_status_mp_err_qs;
Tests: T1 T2 T3
13632 1/1 reg_rdata_next[2] = fault_status_rd_err_qs;
Tests: T1 T2 T3
13633 1/1 reg_rdata_next[3] = fault_status_prog_err_qs;
Tests: T1 T2 T3
13634 1/1 reg_rdata_next[4] = fault_status_prog_win_err_qs;
Tests: T1 T2 T3
13635 1/1 reg_rdata_next[5] = fault_status_prog_type_err_qs;
Tests: T1 T2 T3
13636 1/1 reg_rdata_next[6] = fault_status_seed_err_qs;
Tests: T1 T2 T3
13637 1/1 reg_rdata_next[7] = fault_status_phy_relbl_err_qs;
Tests: T1 T2 T3
13638 1/1 reg_rdata_next[8] = fault_status_phy_storage_err_qs;
Tests: T1 T2 T3
13639 1/1 reg_rdata_next[9] = fault_status_spurious_ack_qs;
Tests: T1 T2 T3
13640 1/1 reg_rdata_next[10] = fault_status_arb_err_qs;
Tests: T1 T2 T3
13641 1/1 reg_rdata_next[11] = fault_status_host_gnt_err_qs;
Tests: T1 T2 T3
13642 end
13643
13644 addr_hit[98]: begin
13645 1/1 reg_rdata_next[19:0] = err_addr_qs;
Tests: T1 T2 T3
13646 end
13647
13648 addr_hit[99]: begin
13649 1/1 reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
Tests: T1 T2 T3
13650 1/1 reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
Tests: T1 T2 T3
13651 end
13652
13653 addr_hit[100]: begin
13654 1/1 reg_rdata_next[19:0] = ecc_single_err_addr_0_qs;
Tests: T1 T2 T3
13655 end
13656
13657 addr_hit[101]: begin
13658 1/1 reg_rdata_next[19:0] = ecc_single_err_addr_1_qs;
Tests: T1 T2 T3
13659 end
13660
13661 addr_hit[102]: begin
13662 1/1 reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
Tests: T1 T2 T3
13663 1/1 reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
Tests: T1 T2 T3
13664 end
13665
13666 addr_hit[103]: begin
13667 1/1 reg_rdata_next[0] = phy_status_init_wip_qs;
Tests: T1 T2 T3
13668 1/1 reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
Tests: T1 T2 T3
13669 1/1 reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
Tests: T1 T2 T3
13670 end
13671
13672 addr_hit[104]: begin
13673 1/1 reg_rdata_next[31:0] = scratch_qs;
Tests: T1 T2 T3
13674 end
13675
13676 addr_hit[105]: begin
13677 1/1 reg_rdata_next[4:0] = fifo_lvl_prog_qs;
Tests: T1 T2 T3
13678 1/1 reg_rdata_next[12:8] = fifo_lvl_rd_qs;
Tests: T1 T2 T3
13679 end
13680
13681 addr_hit[106]: begin
13682 1/1 reg_rdata_next[0] = fifo_rst_qs;
Tests: T1 T2 T3
13683 end
13684
13685 addr_hit[107]: begin
13686 1/1 reg_rdata_next[4:0] = curr_fifo_lvl_prog_qs;
Tests: T1 T2 T3
13687 1/1 reg_rdata_next[12:8] = curr_fifo_lvl_rd_qs;
Tests: T1 T2 T3
13688 end
13689
13690 default: begin
13691 reg_rdata_next = '1;
13692 end
13693 endcase
13694 end
13695
13696 // shadow busy
13697 logic shadow_busy;
13698 logic rst_done;
13699 logic shadow_rst_done;
13700 always_ff @(posedge clk_i or negedge rst_ni) begin
13701 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
13702 1/1 rst_done <= '0;
Tests: T1 T2 T3
13703 end else begin
13704 1/1 rst_done <= 1'b1;
Tests: T1 T2 T3
13705 end
13706 end
13707
13708 always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
13709 1/1 if (!rst_shadowed_ni) begin
Tests: T1 T2 T3
13710 1/1 shadow_rst_done <= '0;
Tests: T1 T2 T3
13711 end else begin
13712 1/1 shadow_rst_done <= 1'b1;
Tests: T1 T2 T3
13713 end
13714 end
13715
13716 // both shadow and normal resets have been released
13717 1/1 assign shadow_busy = ~(rst_done & shadow_rst_done);
Tests: T1 T2 T3
13718
13719 // Collect up storage and update errors
13720 1/1 assign shadowed_storage_err_o = |{
Tests: T1 T2 T3
13721 mp_bank_cfg_shadowed_erase_en_0_storage_err,
13722 mp_bank_cfg_shadowed_erase_en_1_storage_err
13723 };
13724 1/1 assign shadowed_update_err_o = |{
Tests: T1 T2 T3
13725 mp_bank_cfg_shadowed_erase_en_0_update_err,
13726 mp_bank_cfg_shadowed_erase_en_1_update_err
13727 };
13728
13729 // register busy
13730 1/1 assign reg_busy = shadow_busy;
Tests: T1 T2 T3
13731
13732 // Unused signal tieoff
13733
13734 // wdata / byte enable are not always fully used
13735 // add a blanket unused statement to handle lint waivers
13736 logic unused_wdata;
13737 logic unused_be;
13738 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
13739 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3