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 LINE       140
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT62,T95,T208
10CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT62,T95,T208

 LINE       146
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT35,T62,T95
10CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT95
111CoveredT35,T62,T95

 LINE       146
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT62,T81,T95
10CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT62,T81,T95

 LINE       146
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT62,T95,T208
10CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       146
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT62,T95,T208

 LINE       146
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       154
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       167
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       167
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       167
 EXPRESSION (req_o & ack_i & no_match)
             --1--   --2--   ----3---
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT51,T74,T81
110Not Covered
111CoveredT1,T2,T3

 LINE       186
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       193
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       194
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T3
1011111Not Covered
1101111CoveredT1,T2,T58
1110111CoveredT1,T2,T3
1111011CoveredT95
1111101Not Covered
1111110CoveredT157,T208,T154
1111111CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T3,T8
1011111CoveredT214
1101111CoveredT1,T2,T17
1110111CoveredT1,T2,T3
1111011CoveredT95
1111101Not Covered
1111110CoveredT157,T213,T153
1111111CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T3,T8
1011111Not Covered
1101111CoveredT1,T2,T8
1110111CoveredT1,T2,T3
1111011Not Covered
1111101CoveredT215
1111110CoveredT213,T152,T153
1111111CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT2,T3,T8
1011111Not Covered
1101111CoveredT1,T2,T8
1110111CoveredT1,T2,T3
1111011Not Covered
1111101Not Covered
1111110CoveredT22,T157,T213
1111111CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       196
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT157,T158,T208
111CoveredT1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT157,T213,T153
111CoveredT1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT213,T158,T152
111CoveredT1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       212
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT22,T37,T157
111CoveredT1,T2,T3

 LINE       212
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT3,T8,T13
101CoveredT1,T2,T3
110CoveredT17,T9,T22
111CoveredT1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT3,T8,T13
101CoveredT1,T2,T3
110CoveredT17,T9,T35
111CoveredT1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT3,T8,T13
101CoveredT1,T2,T3
110CoveredT17,T9,T35
111CoveredT1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       218
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT3,T8,T13
101CoveredT1,T2,T3
110CoveredT17,T9,T22
111CoveredT1,T2,T3

 LINE       218
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       222
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T8,T17
10CoveredT1,T2,T3
11CoveredT2,T8,T17

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T17,T58
010CoveredT2,T8,T58
100CoveredT27,T30,T31

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T13
11CoveredT2,T8,T58

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T58,T4
11CoveredT2,T17,T58

 LINE       222
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T8,T17
10CoveredT1,T2,T3
11CoveredT2,T8,T17

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T17,T58
010CoveredT2,T8,T58
100CoveredT27,T30,T31

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T13
11CoveredT2,T8,T58

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T58,T4
11CoveredT2,T17,T58

 LINE       222
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T8,T17
10CoveredT1,T2,T3
11CoveredT2,T8,T17

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T17,T58
010CoveredT2,T8,T58
100CoveredT27,T30,T31

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T13
11CoveredT2,T8,T58

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T58,T4
11CoveredT2,T17,T58

 LINE       222
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT2,T8,T17
10CoveredT1,T2,T3
11CoveredT2,T8,T17

 LINE       222
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT2,T17,T58
010CoveredT2,T8,T58
100CoveredT27,T30,T31

 LINE       222
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T8,T13
11CoveredT2,T8,T58

 LINE       222
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT29,T58,T4
11CoveredT2,T17,T58

 LINE       232
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT62,T95,T216
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT50,T62,T46
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT22,T62,T83
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       239
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT62,T74,T83
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       291
 EXPRESSION (req_o & ack_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT51,T74,T81
11CoveredT1,T2,T3

 LINE       292
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT2,T8,T13
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       302
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       305
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T9,T22
11CoveredT1,T2,T3

 LINE       308
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       377
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       382
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT10,T12,T69
10CoveredT10,T12,T69
11CoveredT1,T2,T3

 LINE       393
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       399
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change & (calc_req_o ? calc_req_done : 1'b1))
             --------------------------------1-------------------------------   -----------2-----------   --------3-------   -----------------4-----------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Not Covered
1101CoveredT1,T2,T3
1110CoveredT9,T22,T50
1111CoveredT1,T2,T3

 LINE       399
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       399
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT3,T8,T9
111CoveredT1,T2,T3

 LINE       399
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match & (calc_req_o ? calc_req_done : 1'b1))
             --1--   --------2-------   ----3----   ------4------   ----5---   -----------------6-----------------
-1--2--3--4--5--6-StatusTests
011111CoveredT1,T2,T3
101111CoveredT217
110111CoveredT3,T51,T83
111011Not Covered
111101CoveredT1,T2,T3
111110CoveredT22,T50,T62
111111CoveredT1,T2,T3

 LINE       407
 SUB-EXPRESSION (calc_req_o ? calc_req_done : 1'b1)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       428
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       432
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT2,T13,T17
10CoveredT1,T2,T3
11CoveredT17,T65,T22

 LINE       432
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T13,T17

 LINE       442
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT2,T8,T14
10CoveredT1,T2,T3
11CoveredT35,T62,T81

 LINE       451
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT50,T35,T62

 LINE       451
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT50,T51,T52
10CoveredT35,T62,T81

 LINE       456
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT8,T14,T17
10CoveredT1,T2,T3
11CoveredT50,T51,T52

 LINE       491
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy & addr_xor_fifo_rdy)
             ------1------   ------2------   --------3--------
-1--2--3-StatusTests
011CoveredT10,T12,T69
101Not Covered
110CoveredT3,T8,T9
111CoveredT1,T2,T3

 LINE       494
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT17,T22,T37
111CoveredT1,T2,T3

 LINE       497
 EXPRESSION (rd_done & rd_attrs.descramble & data_erased)
             ---1---   ---------2---------   -----3-----
-1--2--3-StatusTests
011Not Covered
101CoveredT17,T65,T83
110CoveredT1,T2,T3
111CoveredT17,T22,T37

 LINE       501
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT81,T157,T213
111CoveredT1,T2,T3

 LINE       503
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       504
 EXPRESSION (fifo_data_valid & dropmsk_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT17,T22,T37

 LINE       505
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3