Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	97.89	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2100995085	20353582	0	0
check_regwen_rd_A	2100995085	3142	0	0
check_timeout_rd_A	2100995085	2913	0	0
check_trigger_regwen_rd_A	2100995085	3285	0	0
consistency_check_period_rd_A	2100995085	3362	0	0
creator_sw_cfg_read_lock_rd_A	2100995085	2801	0	0
direct_access_address_rd_A	2100995085	2688	0	0
direct_access_wdata_0_rd_A	2100995085	1994	0	0
direct_access_wdata_1_rd_A	2100995085	2121	0	0
integrity_check_period_rd_A	2100995085	3042	0	0
intr_enable_rd_A	2100995085	4373	0	0
owner_sw_cfg_read_lock_rd_A	2100995085	2634	0	0
vendor_test_read_lock_rd_A	2100995085	2544	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	20353582	0	0
T13	86025	1	0	0
T107	59376	4	0	0
T108	6910	0	0	0
T183	7737	0	0	0
T184	11895	0	0	0
T185	9824	279	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	0	39	0	0
T192	0	262	0	0
T193	0	68	0	0
T200	0	6	0	0
T201	0	1	0	0
T243	0	2	0	0
T249	0	2	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	3142	0	0
T184	11895	41	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	9	0	0
T198	0	13	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T243	0	14	0	0
T249	0	54	0	0
T257	0	13	0	0
T270	0	8	0	0
T272	0	2	0	0
T287	0	43	0	0
T288	0	1	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	2913	0	0
T1	0	185	0	0
T4	0	303	0	0
T12	0	42	0	0
T184	11895	94	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	14	0	0
T198	0	9	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T257	0	57	0	0
T270	0	1	0	0
T289	0	47	0	0
T290	0	170	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	3285	0	0
T184	11895	82	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	17	0	0
T198	0	18	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T243	0	14	0	0
T249	0	34	0	0
T257	0	46	0	0
T270	0	7	0	0
T272	0	5	0	0
T287	0	25	0	0
T288	0	10	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	3362	0	0
T184	11895	27	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	7	0	0
T198	0	9	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T243	0	29	0	0
T249	0	34	0	0
T257	0	58	0	0
T270	0	7	0	0
T287	0	29	0	0
T288	0	5	0	0
T291	0	137	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	2801	0	0
T1	0	242	0	0
T4	0	363	0	0
T12	0	51	0	0
T184	11895	36	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	7	0	0
T198	0	11	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T257	0	39	0	0
T289	0	12	0	0
T290	0	164	0	0
T292	0	87	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	2688	0	0
T1	0	178	0	0
T4	0	354	0	0
T12	0	26	0	0
T194	9787	3	0	0
T195	16483	0	0	0
T198	0	2	0	0
T216	3505	0	0	0
T217	3430	0	0	0
T218	3815	0	0	0
T255	5846	0	0	0
T256	3956	0	0	0
T270	0	2	0	0
T290	0	97	0	0
T292	0	90	0	0
T293	0	19	0	0
T294	0	132	0	0
T295	3587	0	0	0
T296	3803	0	0	0
T297	3059	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	1994	0	0
T1	219091	143	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	305	0	0
T5	19562	0	0	0
T6	27806	0	0	0
T7	13630	0	0	0
T8	10804	0	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T12	0	20	0	0
T283	0	96	0	0
T290	0	115	0	0
T292	0	59	0	0
T293	0	18	0	0
T294	0	96	0	0
T298	0	7	0	0
T299	0	210	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	2121	0	0
T1	219091	170	0	0
T2	13075	0	0	0
T4	0	339	0	0
T12	0	7	0	0
T268	12103	0	0	0
T283	0	157	0	0
T289	8617	0	0	0
T290	0	110	0	0
T292	0	72	0	0
T293	0	33	0	0
T294	0	127	0	0
T298	0	13	0	0
T300	16692	5	0	0
T301	3311	0	0	0
T302	3511	0	0	0
T303	3345	0	0	0
T304	3899	0	0	0
T305	115931	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	3042	0	0
T184	11895	16	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	15	0	0
T198	0	7	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T243	0	12	0	0
T249	0	29	0	0
T257	0	29	0	0
T270	0	6	0	0
T272	0	5	0	0
T287	0	47	0	0
T288	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	4373	0	0
T109	0	11	0	0
T111	0	28	0	0
T184	11895	82	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	23	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T216	0	23	0	0
T217	0	16	0	0
T218	0	13	0	0
T243	0	28	0	0
T249	0	52	0	0
T296	0	1	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	2634	0	0
T1	0	152	0	0
T4	0	393	0	0
T12	0	19	0	0
T184	11895	34	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	6	0	0
T198	0	8	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T257	0	44	0	0
T270	0	7	0	0
T289	0	24	0	0
T290	0	94	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2100995085	2544	0	0
T1	0	130	0	0
T4	0	297	0	0
T12	0	17	0	0
T184	11895	34	0	0
T185	9824	0	0	0
T186	5081	0	0	0
T187	3657	0	0	0
T188	41397	0	0	0
T189	4009	0	0	0
T190	7115	0	0	0
T191	4608	0	0	0
T194	0	10	0	0
T198	0	7	0	0
T200	113360	0	0	0
T201	58551	0	0	0
T257	0	25	0	0
T270	0	1	0	0
T289	0	62	0	0
T290	0	141	0	0