Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.06	98.11	97.78		66.67	97.73	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	93.17	97.62	95.56		83.33	93.18	96.15
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.17	97.62	95.56		83.33	93.18	96.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.53	98.44	95.74	97.87	83.33	94.64	97.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	97.89	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	97.89	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	100.00		91.67	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.26	100.00	100.00	97.87	91.67	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.04	97.89	88.57	96.78		96.97	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_digest_write_lock.u_prim_mubi8_sender_write_lock	100.00	100.00				100.00	100.00
u_otp_ctrl_ecc_reg	99.57	100.00	100.00	97.87		100.00	100.00
u_prim_mubi8_sender_read_lock_pre	100.00	100.00				100.00	100.00
u_prim_mubi8_sender_write_lock_pre	100.00	100.00				100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
93.17	97.62

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	83	94.32
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	62	92.54
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	0	1
271	0	1
273	0	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		88	88	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	67	67	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
93.17	95.56

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T121,T62,T38

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T121,T62,T38

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T62,T38

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T121

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T117,T114,T115

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T117,T114,T115

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T117,T114,T115

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T29,T117,T114

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T16,T17,T18

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T122,T123,T124
1	Covered	T122,T123,T124

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T125,T105

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T125,T105

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 + Info=226594821,DigestOffset=1656,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T95,T121,T126
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T61,T62

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T127,T128,T129
0	1	Covered	T1,T2,T4
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T29,T114,T42

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T16,T17,T18

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T130,T122,T131
1	Covered	T130,T122,T131

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T53,T95

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T53,T95

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T13
IdleSt	199	Covered	T13
InitSt	175	Covered	T13
InitWaitSt	185	Covered	T13
ReadSt	221	Covered	T13
ReadWaitSt	239	Covered	T13
ResetSt	173	Covered	T13

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T13
IdleSt->ReadSt	221	Covered	T13
InitSt->ErrorSt	309	Covered	T13
InitSt->InitWaitSt	185	Covered	T13
InitWaitSt->ErrorSt	209	Covered	T13
InitWaitSt->IdleSt	199	Covered	T13
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T13
ReadSt->ReadWaitSt	239	Covered	T13
ReadWaitSt->ErrorSt	270	Covered	T13
ReadWaitSt->IdleSt	260	Covered	T13
ResetSt->ErrorSt	309	Covered	T13
ResetSt->InitSt	175	Covered	T13

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T13
CheckFailError	311	Covered	T13
FsmStateError	283	Covered	T13
MacroEccCorrError	206	Covered	T13
NoError	220	Covered	T13

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	311	Not Covered
AccessError->FsmStateError	319	Covered	T13
AccessError->MacroEccCorrError	206	Not Covered
AccessError->NoError	220	Covered	T13
CheckFailError->AccessError	243	Not Covered
CheckFailError->FsmStateError	319	Not Covered
CheckFailError->MacroEccCorrError	206	Not Covered
CheckFailError->NoError	220	Covered	T13
FsmStateError->AccessError	243	Not Covered
FsmStateError->CheckFailError	311	Not Covered
FsmStateError->MacroEccCorrError	206	Not Covered
FsmStateError->NoError	220	Covered	T13
MacroEccCorrError->AccessError	243	Not Covered
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T13
MacroEccCorrError->NoError	220	Covered	T13
NoError->AccessError	243	Covered	T13
NoError->CheckFailError	311	Covered	T13
NoError->FsmStateError	283	Covered	T13
NoError->MacroEccCorrError	206	Covered	T13

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=16879621,DigestOffset=856,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T53,T95
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T103,T61,T62
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T95,T121,T126
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T86,T100
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T114,T42,T90
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T127,T128,T132
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T130,T122,T131
1	0	Covered	T130,T122,T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=226594821,DigestOffset=1656,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T53,T96
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T61,T19,T77
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T103,T133,T134
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T118,T119
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T42,T26
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T135,T136
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T94
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T94
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T131,T123,T137
1	0	Covered	T131,T123,T137
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=8196,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.17	93.18

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T121,T125,T105
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T121
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T54,T86
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T117,T114
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T122,T123,T124
1	0	Covered	T122,T123,T124
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	3480	3480	0	0
EccErrorState_A	2147483647	48405	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	1223615031	0	0
InitWriteLocksPartition_A	2147483647	1223615031	0	0
OffsetMustBeBlockAligned_A	3480	3480	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	131	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	2147483647	0	0
SizeMustBeBlockAligned_A	3480	3480	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	30492	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	3045245	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	44989996	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3480	3480	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48405	0	0
T12	265502	0	0	0
T30	39808	0	0	0
T41	79809	0	0	0
T44	102683	0	0	0
T54	33657	0	0	0
T104	24535	0	0	0
T105	9964	0	0	0
T106	24973	0	0	0
T122	15249	5720	0	0
T123	0	9591	0	0
T124	0	10752	0	0
T125	27566	0	0	0
T126	13513	0	0	0
T130	11875	2836	0	0
T131	13887	4194	0	0
T137	0	3840	0	0
T138	0	3685	0	0
T139	0	2057	0	0
T140	0	5730	0	0
T141	10775	0	0	0
T142	9744	0	0	0
T143	18662	0	0	0
T144	337270	0	0	0
T145	8462	0	0	0
T146	31520	0	0	0
T147	12476	0	0	0
T148	11529	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223615031	0	0
T1	657273	2998524	0	0
T2	39225	14739	0	0
T3	15129	243	0	0
T4	1514292	2313	0	0
T5	58686	1662	0	0
T6	83418	7731	0	0
T7	40890	18528	0	0
T8	32412	7587	0	0
T9	46920	13803	0	0
T10	30630	8823	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1223615031	0	0
T1	657273	2998524	0	0
T2	39225	14739	0	0
T3	15129	243	0	0
T4	1514292	2313	0	0
T5	58686	1662	0	0
T6	83418	7731	0	0
T7	40890	18528	0	0
T8	32412	7587	0	0
T9	46920	13803	0	0
T10	30630	8823	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3480	3480	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	131	0	0
T11	197565	0	0	0
T16	923218	0	0	0
T29	64199	0	0	0
T34	24085	0	0	0
T61	15846	0	0	0
T63	13730	0	0	0
T84	91204	0	0	0
T85	64346	0	0	0
T95	11920	1	0	0
T96	19420	0	0	0
T97	21537	0	0	0
T98	12824	0	0	0
T103	11528	1	0	0
T121	11369	1	0	0
T125	27566	0	0	0
T126	13513	1	0	0
T127	0	2	0	0
T129	0	1	0	0
T130	11875	0	0	0
T133	13913	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T141	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	15442	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	22796	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	339779	0	0
T2	39225	0	0	0
T3	15129	0	0	0
T4	1514292	1139402	0	0
T5	58686	0	0	0
T6	83418	6912	0	0
T7	40890	20111	0	0
T8	32412	0	0	0
T9	46920	0	0	0
T10	30630	0	0	0
T11	0	436936	0	0
T29	0	9716	0	0
T53	0	9932	0	0
T54	0	832	0	0
T94	0	20626	0	0
T96	0	5796	0	0
T125	0	22025	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3480	3480	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30492	0	0
T1	657273	101	0	0
T2	39225	0	0	0
T3	15129	0	0	0
T4	1514292	46	0	0
T5	58686	0	0	0
T6	83418	6	0	0
T7	40890	66	0	0
T8	32412	2	0	0
T9	46920	0	0	0
T10	30630	0	0	0
T11	0	208	0	0
T29	0	25	0	0
T53	0	12	0	0
T94	0	80	0	0
T96	0	9	0	0
T97	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3045245	0	0
T6	27806	2830	0	0
T11	395130	0	0	0
T20	12413	0	0	0
T29	128398	1146	0	0
T34	48170	0	0	0
T42	0	4587	0	0
T43	0	6071	0	0
T53	98070	3297	0	0
T54	0	318	0	0
T57	25406	0	0	0
T61	15846	0	0	0
T83	0	4079	0	0
T84	0	9364	0	0
T85	64346	14719	0	0
T86	0	1047	0	0
T87	0	3205	0	0
T91	59089	1262	0	0
T92	36473	0	0	0
T93	0	2052	0	0
T94	37128	0	0	0
T95	23840	0	0	0
T96	38840	0	0	0
T97	21537	0	0	0
T98	12824	0	0	0
T125	27566	15152	0	0
T160	0	12058	0	0
T161	0	4339	0	0
T162	0	834	0	0
T163	0	18230	0	0
T164	0	2823	0	0
T165	0	4111	0	0
T166	0	2020	0	0
T167	12066	0	0	0
T168	16792	0	0	0
T169	14574	0	0	0
T170	35042	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	44989996	0	0
T6	55612	40421	0	0
T11	395130	0	0	0
T12	265502	0	0	0
T29	128398	41352	0	0
T30	0	34583	0	0
T34	48170	0	0	0
T38	0	3591	0	0
T42	0	35268	0	0
T53	98070	75704	0	0
T54	33657	53598	0	0
T57	25406	0	0	0
T60	26716	0	0	0
T62	0	3713	0	0
T83	0	56035	0	0
T84	0	83772	0	0
T85	0	57191	0	0
T86	0	17782	0	0
T94	37128	0	0	0
T95	23840	2623	0	0
T96	38840	20531	0	0
T103	0	3391	0	0
T104	24535	0	0	0
T105	9964	4948	0	0
T106	24973	0	0	0
T121	11369	5061	0	0
T125	27566	12739	0	0
T126	13513	3261	0	0
T130	11875	0	0	0
T141	10775	3922	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	657273	657270	0	0
T2	39225	38490	0	0
T3	15129	14952	0	0
T4	1514292	1514286	0	0
T5	58686	57114	0	0
T6	83418	81966	0	0
T7	40890	40566	0	0
T8	32412	31470	0	0
T9	46920	46086	0	0
T10	30630	29814	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		84	82	97.62
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	63	61	96.83
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			==> MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	0	1
210	0	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270		excluded
			Exclude Annotation: VC_COV_UNR
271		excluded
			Exclude Annotation: VC_COV_UNR
273		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T3
1	0	Covered	T121,T62,T38

 LINE       197
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T121,T62,T38

 LINE       197
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T62,T38

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T10,T121

 LINE       258
 EXPRESSION ((((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T1,T2,T4
1	0	Covered	T117,T114,T115

 LINE       258
 SUB-EXPRESSION (((!1'b0)) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))
                 ----1----    -----------------------2----------------------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T4
-	1	Covered	T117,T114,T115

 LINE       258
 SUB-EXPRESSION (otp_err_e'(otp_err_i) == MacroEccUncorrError)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T117,T114,T115

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T29,T117,T114

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T16,T17,T18

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T122,T123,T124
1	Covered	T122,T123,T124

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T125,T105

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T121,T125,T105

---

FSM Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	10	76.92
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T13
IdleSt	199	Covered	T13
InitSt	175	Covered	T13
InitWaitSt	185	Covered	T13
ReadSt	221	Covered	T13
ReadWaitSt	239	Covered	T13
ResetSt	173	Covered	T13

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T13
IdleSt->ReadSt	221	Covered	T13
InitSt->ErrorSt	309	Not Covered
InitSt->InitWaitSt	185	Covered	T13
InitWaitSt->ErrorSt	209	Covered	T13
InitWaitSt->IdleSt	199	Covered	T13
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T13
ReadSt->ReadWaitSt	239	Covered	T13
ReadWaitSt->ErrorSt	270	Not Covered
ReadWaitSt->IdleSt	260	Covered	T13
ResetSt->ErrorSt	309	Covered	T13
ResetSt->InitSt	175	Covered	T13

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T13
CheckFailError	311	Covered	T13
FsmStateError	283	Covered	T13
MacroEccCorrError	206	Covered	T13
NoError	220	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T13
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T13
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T13
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T13
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T13
MacroEccCorrError->NoError	220	Covered	T13
NoError->AccessError	243	Covered	T13
NoError->CheckFailError	311	Covered	T13
NoError->FsmStateError	283	Covered	T13
NoError->MacroEccCorrError	206	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	41	93.18
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	20	86.96
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T121,T125,T105
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b0) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b0) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T2,T10,T121
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T54,T86
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T117,T114
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T122,T123,T124
1	0	Covered	T122,T123,T124
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	25	96.15
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	25	96.15

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2098301949	2097475901	0	0
DigestKnown_A	2098301949	2097475901	0	0
DigestOffsetMustBeRepresentable_A	1160	1160	0	0
EccErrorState_A	2098301949	9641	0	0
ErrorKnown_A	2098301949	2097475901	0	0
FsmStateKnown_A	2098301949	2097475901	0	0
InitDoneKnown_A	2098301949	2097475901	0	0
InitReadLocksPartition_A	2098301949	407696484	0	0
InitWriteLocksPartition_A	2098301949	407696484	0	0
OffsetMustBeBlockAligned_A	1160	1160	0	0
OtpAddrKnown_A	2098301949	2097475901	0	0
OtpCmdKnown_A	2098301949	2097475901	0	0
OtpErrorState_A	2098301949	0	0	0
OtpReqKnown_A	2098301949	2097475901	0	0
OtpSizeKnown_A	2098301949	2097475901	0	0
OtpWdataKnown_A	2098301949	2097475901	0	0
ReadLockPropagation_A	2098301949	1003435661	0	0
SizeMustBeBlockAligned_A	1160	1160	0	0
TlulGntKnown_A	2098301949	2097475901	0	0
TlulRdataKnown_A	2098301949	2097475901	0	0
TlulReadOnReadLock_A	2098301949	9919	0	0
TlulRerrorKnown_A	2098301949	2097475901	0	0
TlulRvalidKnown_A	2098301949	2097475901	0	0
WriteLockPropagation_A	2098301949	338626	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2098301949	6127968	0	0
u_state_regs_A	2098301949	2097475901	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	9641	0	0
T41	79809	0	0	0
T44	102683	0	0	0
T122	15249	2860	0	0
T123	0	3197	0	0
T124	0	3584	0	0
T142	9744	0	0	0
T143	18662	0	0	0
T144	337270	0	0	0
T145	8462	0	0	0
T146	31520	0	0	0
T147	12476	0	0	0
T148	11529	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	407696484	0	0
T1	219091	999489	0	0
T2	13075	4879	0	0
T3	5043	64	0	0
T4	504764	584	0	0
T5	19562	435	0	0
T6	27806	2475	0	0
T7	13630	6142	0	0
T8	10804	2461	0	0
T9	15640	4550	0	0
T10	10210	2890	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	407696484	0	0
T1	219091	999489	0	0
T2	13075	4879	0	0
T3	5043	64	0	0
T4	504764	584	0	0
T5	19562	435	0	0
T6	27806	2475	0	0
T7	13630	6142	0	0
T8	10804	2461	0	0
T9	15640	4550	0	0
T10	10210	2890	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	1003435661	0	0
T1	219091	113348	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	379832	0	0
T5	19562	0	0	0
T6	27806	2308	0	0
T7	13630	6894	0	0
T8	10804	0	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T11	0	145996	0	0
T29	0	1701	0	0
T53	0	4202	0	0
T54	0	832	0	0
T96	0	1874	0	0
T125	0	3208	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	9919	0	0
T1	219091	30	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	14	0	0
T5	19562	0	0	0
T6	27806	1	0	0
T7	13630	25	0	0
T8	10804	1	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T11	0	58	0	0
T29	0	9	0	0
T53	0	6	0	0
T94	0	29	0	0
T96	0	3	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	338626	0	0
T20	12413	0	0	0
T43	0	6071	0	0
T61	15846	0	0	0
T85	64346	2625	0	0
T91	59089	1262	0	0
T92	36473	0	0	0
T98	12824	0	0	0
T160	0	4782	0	0
T161	0	4339	0	0
T162	0	834	0	0
T163	0	18230	0	0
T164	0	2823	0	0
T165	0	4111	0	0
T166	0	2020	0	0
T167	12066	0	0	0
T168	16792	0	0	0
T169	14574	0	0	0
T170	35042	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	6127968	0	0
T12	265502	0	0	0
T38	0	3591	0	0
T42	0	35268	0	0
T54	33657	0	0	0
T62	0	3713	0	0
T83	0	22704	0	0
T84	0	3520	0	0
T85	0	57191	0	0
T86	0	17782	0	0
T104	24535	0	0	0
T105	9964	2491	0	0
T106	24973	0	0	0
T121	11369	2533	0	0
T125	27566	2399	0	0
T126	13513	0	0	0
T130	11875	0	0	0
T141	10775	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T95,T121,T126
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T61,T62

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T127,T128,T132
0	1	Covered	T1,T2,T4
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T114,T42,T90

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T16,T17,T18

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T130,T122,T131
1	Covered	T130,T122,T131

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T53,T95

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T53,T95

---

FSM Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T13
IdleSt	199	Covered	T13
InitSt	175	Covered	T13
InitWaitSt	185	Covered	T13
ReadSt	221	Covered	T13
ReadWaitSt	239	Covered	T13
ResetSt	173	Covered	T13

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T13
IdleSt->ReadSt	221	Covered	T13
InitSt->ErrorSt	309	Covered	T13
InitSt->InitWaitSt	185	Covered	T13
InitWaitSt->ErrorSt	209	Covered	T13
InitWaitSt->IdleSt	199	Covered	T13
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T13
ReadSt->ReadWaitSt	239	Covered	T13
ReadWaitSt->ErrorSt	270	Covered	T13
ReadWaitSt->IdleSt	260	Covered	T13
ResetSt->ErrorSt	309	Covered	T13
ResetSt->InitSt	175	Covered	T13

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T13
CheckFailError	311	Covered	T13
FsmStateError	283	Covered	T13
MacroEccCorrError	206	Covered	T13
NoError	220	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T13
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T13
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T13
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T13
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T13
MacroEccCorrError->NoError	220	Covered	T13
NoError->AccessError	243	Covered	T13
NoError->CheckFailError	311	Covered	T13
NoError->FsmStateError	283	Covered	T13
NoError->MacroEccCorrError	206	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T53,T95
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T103,T61,T62
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T95,T121,T126
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T96,T86,T100
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T114,T42,T90
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T127,T128,T132
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T8
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T130,T122,T131
1	0	Covered	T130,T122,T131
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2098301949	2097475901	0	0
DigestKnown_A	2098301949	2097475901	0	0
DigestOffsetMustBeRepresentable_A	1160	1160	0	0
EccErrorState_A	2098301949	23181	0	0
ErrorKnown_A	2098301949	2097475901	0	0
FsmStateKnown_A	2098301949	2097475901	0	0
InitDoneKnown_A	2098301949	2097475901	0	0
InitReadLocksPartition_A	2098301949	407872051	0	0
InitWriteLocksPartition_A	2098301949	407872051	0	0
OffsetMustBeBlockAligned_A	1160	1160	0	0
OtpAddrKnown_A	2098301949	2097475901	0	0
OtpCmdKnown_A	2098301949	2097475901	0	0
OtpErrorState_A	2098301949	84	0	0
OtpReqKnown_A	2098301949	2097475901	0	0
OtpSizeKnown_A	2098301949	2097475901	0	0
OtpWdataKnown_A	2098301949	2097475901	0	0
ReadLockPropagation_A	2098301949	1016155497	0	0
SizeMustBeBlockAligned_A	1160	1160	0	0
TlulGntKnown_A	2098301949	2097475901	0	0
TlulRdataKnown_A	2098301949	2097475901	0	0
TlulReadOnReadLock_A	2098301949	10189	0	0
TlulRerrorKnown_A	2098301949	2097475901	0	0
TlulRvalidKnown_A	2098301949	2097475901	0	0
WriteLockPropagation_A	2098301949	1392401	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2098301949	20028745	0	0
u_state_regs_A	2098301949	2097475901	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	23181	0	0
T12	265502	0	0	0
T30	39808	0	0	0
T54	33657	0	0	0
T104	24535	0	0	0
T105	9964	0	0	0
T106	24973	0	0	0
T122	0	2860	0	0
T123	0	3197	0	0
T124	0	3584	0	0
T125	27566	0	0	0
T126	13513	0	0	0
T130	11875	2836	0	0
T131	0	2097	0	0
T138	0	3685	0	0
T139	0	2057	0	0
T140	0	2865	0	0
T141	10775	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	407872051	0	0
T1	219091	999508	0	0
T2	13075	4913	0	0
T3	5043	81	0	0
T4	504764	771	0	0
T5	19562	554	0	0
T6	27806	2577	0	0
T7	13630	6176	0	0
T8	10804	2529	0	0
T9	15640	4601	0	0
T10	10210	2941	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	407872051	0	0
T1	219091	999508	0	0
T2	13075	4913	0	0
T3	5043	81	0	0
T4	504764	771	0	0
T5	19562	554	0	0
T6	27806	2577	0	0
T7	13630	6176	0	0
T8	10804	2529	0	0
T9	15640	4601	0	0
T10	10210	2941	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	84	0	0
T11	197565	0	0	0
T29	64199	0	0	0
T34	24085	0	0	0
T95	11920	1	0	0
T96	19420	0	0	0
T97	21537	0	0	0
T121	11369	1	0	0
T125	27566	0	0	0
T126	13513	1	0	0
T127	0	2	0	0
T130	11875	0	0	0
T141	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T156	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	1016155497	0	0
T1	219091	113291	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	379797	0	0
T5	19562	0	0	0
T6	27806	2304	0	0
T7	13630	6325	0	0
T8	10804	0	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T11	0	145999	0	0
T29	0	4611	0	0
T53	0	3243	0	0
T94	0	10314	0	0
T96	0	2056	0	0
T125	0	15637	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	10189	0	0
T1	219091	38	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	19	0	0
T5	19562	0	0	0
T6	27806	4	0	0
T7	13630	20	0	0
T8	10804	1	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T11	0	81	0	0
T29	0	10	0	0
T53	0	1	0	0
T94	0	24	0	0
T96	0	4	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	1392401	0	0
T11	197565	0	0	0
T29	64199	1146	0	0
T34	24085	0	0	0
T42	0	4587	0	0
T53	49035	3297	0	0
T57	12703	0	0	0
T83	0	1487	0	0
T84	0	7950	0	0
T85	0	5733	0	0
T86	0	1047	0	0
T87	0	2270	0	0
T93	0	2052	0	0
T94	18564	0	0	0
T95	11920	0	0	0
T96	19420	0	0	0
T97	21537	0	0	0
T125	27566	15152	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	20028745	0	0
T6	27806	20253	0	0
T11	197565	0	0	0
T29	64199	41352	0	0
T34	24085	0	0	0
T53	49035	37937	0	0
T54	0	26867	0	0
T57	12703	0	0	0
T60	13358	0	0	0
T94	18564	0	0	0
T95	11920	2623	0	0
T96	19420	13548	0	0
T121	0	2528	0	0
T125	0	7975	0	0
T126	0	3261	0	0
T141	0	3922	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		87	87	100.00
CONT_ASSIGN	137	1	1	100.00
ALWAYS	147	66	66	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	330	1	1	100.00
CONT_ASSIGN	335	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	340	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
ALWAYS	437	3	3	100.00
ALWAYS	440	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
137	1	1
147	1	1
150	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
162	1	1
165	1	1
166	1	1
167	1	1
169	1	1
174	1	1
175	1	1
			MISSING_ELSE
183	1	1
184	1	1
185	1	1
			MISSING_ELSE
193	1	1
194	1	1
197	1	1
199	1	1
205	1	1
206	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
			MISSING_ELSE
231	1	1
233	1	1
236	1	1
237	1	1
238	1	1
239	1	1
			MISSING_ELSE
242	1	1
243	1	1
244	1	1
245	1	1
253	1	1
254	1	1
255	1	1
258	1	1
260	1	1
266	1	1
267	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
			MISSING_ELSE
282	1	1
283		excluded
			Exclude Annotation: VC_COV_UNR
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
308	1	1
309	1	1
310	1	1
311	1	1
			MISSING_ELSE
			MISSING_ELSE
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
			MISSING_ELSE
			MISSING_ELSE
328	1	1
330	1	1
335	1	1
336	1	1
340	1	1
344	1	1
371	1	1
396	1	1
430	1	1
437	3	3
440	1	1
441	1	1
442	1	1
443	1	1
445	1	1
446	1	1
447	1	1
448	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	35	35	100.00
Logical	35	35	100.00
Non-Logical	0	0
Event	0	0

 LINE       197
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T103,T133,T134
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       205
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T61,T19,T77

 LINE       258
 EXPRESSION ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError))) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
             ------------------------------1------------------------------    -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	0	Covered	T129,T135,T136
0	1	Covered	T1,T2,T4
1	0	Unreachable

 LINE       266
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T29,T42,T26

 LINE       282
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T16,T17,T18

 LINE       310
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T131,T123,T137
1	Covered	T131,T123,T137

 LINE       318
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       330
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T7
1	1	Covered	T1,T2,T4

 LINE       330
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       335
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       335
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       396
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T53,T96

 LINE       396
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T53,T96

---

FSM Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	209	Covered	T13
IdleSt	199	Covered	T13
InitSt	175	Covered	T13
InitWaitSt	185	Covered	T13
ReadSt	221	Covered	T13
ReadWaitSt	239	Covered	T13
ResetSt	173	Covered	T13

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	309	Covered	T13
IdleSt->ReadSt	221	Covered	T13
InitSt->ErrorSt	309	Covered	T13
InitSt->InitWaitSt	185	Covered	T13
InitWaitSt->ErrorSt	209	Covered	T13
InitWaitSt->IdleSt	199	Covered	T13
ReadSt->ErrorSt	309	Not Covered
ReadSt->IdleSt	242	Covered	T13
ReadSt->ReadWaitSt	239	Covered	T13
ReadWaitSt->ErrorSt	270	Covered	T13
ReadWaitSt->IdleSt	260	Covered	T13
ResetSt->ErrorSt	309	Covered	T13
ResetSt->InitSt	175	Covered	T13

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	11	10	90.91
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	243	Covered	T13
CheckFailError	311	Covered	T13
FsmStateError	283	Covered	T13
MacroEccCorrError	206	Covered	T13
NoError	220	Covered	T13

transitions	Line No.	Covered	Tests	Exclude Annotation
AccessError->CheckFailError	311	Excluded		VC_COV_UNR
AccessError->FsmStateError	319	Covered	T13
AccessError->MacroEccCorrError	206	Excluded		VC_COV_UNR
AccessError->NoError	220	Covered	T13
CheckFailError->AccessError	243	Excluded		VC_COV_UNR
CheckFailError->FsmStateError	319	Excluded		VC_COV_UNR
CheckFailError->MacroEccCorrError	206	Excluded		VC_COV_UNR
CheckFailError->NoError	220	Covered	T13
FsmStateError->AccessError	243	Excluded		VC_COV_UNR
FsmStateError->CheckFailError	311	Excluded		VC_COV_UNR
FsmStateError->MacroEccCorrError	206	Excluded		VC_COV_UNR
FsmStateError->NoError	220	Covered	T13
MacroEccCorrError->AccessError	243	Excluded		VC_COV_UNR
MacroEccCorrError->CheckFailError	311	Not Covered
MacroEccCorrError->FsmStateError	319	Covered	T13
MacroEccCorrError->NoError	220	Covered	T13
NoError->AccessError	243	Covered	T13
NoError->CheckFailError	311	Covered	T13
NoError->FsmStateError	283	Covered	T13
NoError->MacroEccCorrError	206	Covered	T13

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	330	2	2	100.00
TERNARY	335	2	2	100.00
TERNARY	344	2	2	100.00
TERNARY	371	2	2	100.00
TERNARY	396	2	2	100.00
CASE	169	23	23	100.00
IF	308	3	3	100.00
IF	315	3	3	100.00
IF	437	2	2	100.00
IF	440	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	330	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	335	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	344	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	371	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	396	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T53,T96
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	169	case (state_q)
-2-:	174	if (init_req_i)
-3-:	184	if (otp_gnt_i)
-4-:	193	if (otp_rvalid_i)
-5-:	197	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-6-:	205	if ((otp_err_e'(otp_err_i) != NoError))
-7-:	219	if (tlul_req_i)
-8-:	233	if (((({tlul_addr_q, 2'b0} >= 11'b01101100000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd)) && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-9-:	238	if (otp_gnt_i)
-10-:	254	if (otp_rvalid_i)
-11-:	258	if ((((!1'b1) && (otp_err_e'(otp_err_i) == MacroEccUncorrError)) || (otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError})))
-12-:	266	if ((otp_err_e'(otp_err_i) != NoError))
-13-:	282	if ((error_q == NoError))
-14-:	287	if (pending_tlul_error_q)
-15-:	290	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T61,T19,T77
InitWaitSt	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T103,T133,T134
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T2,T4
ReadSt	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T118,T119
ReadSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T4,T6
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T29,T42,T26
ReadWaitSt	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T2,T4
ReadWaitSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T135,T136
ReadWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T4
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T17,T18
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T2,T7
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T7,T94
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T1,T7,T94
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T1,T2,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	308	if (ecc_err)
-2-:	310	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T131,T123,T137
1	0	Covered	T131,T123,T137
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	315	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	318	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T7
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	437	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	if ((!rst_ni))
-2-:	447	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2098301949	2097475901	0	0
DigestKnown_A	2098301949	2097475901	0	0
DigestOffsetMustBeRepresentable_A	1160	1160	0	0
EccErrorState_A	2098301949	15583	0	0
ErrorKnown_A	2098301949	2097475901	0	0
FsmStateKnown_A	2098301949	2097475901	0	0
InitDoneKnown_A	2098301949	2097475901	0	0
InitReadLocksPartition_A	2098301949	408046496	0	0
InitWriteLocksPartition_A	2098301949	408046496	0	0
OffsetMustBeBlockAligned_A	1160	1160	0	0
OtpAddrKnown_A	2098301949	2097475901	0	0
OtpCmdKnown_A	2098301949	2097475901	0	0
OtpErrorState_A	2098301949	47	0	0
OtpReqKnown_A	2098301949	2097475901	0	0
OtpSizeKnown_A	2098301949	2097475901	0	0
OtpWdataKnown_A	2098301949	2097475901	0	0
ReadLockPropagation_A	2098301949	1006035935	0	0
SizeMustBeBlockAligned_A	1160	1160	0	0
TlulGntKnown_A	2098301949	2097475901	0	0
TlulRdataKnown_A	2098301949	2097475901	0	0
TlulReadOnReadLock_A	2098301949	10384	0	0
TlulRerrorKnown_A	2098301949	2097475901	0	0
TlulRvalidKnown_A	2098301949	2097475901	0	0
WriteLockPropagation_A	2098301949	1314218	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2098301949	18833283	0	0
u_state_regs_A	2098301949	2097475901	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	15583	0	0
T123	0	3197	0	0
T124	0	3584	0	0
T131	13887	2097	0	0
T137	0	3840	0	0
T140	0	2865	0	0
T171	23115	0	0	0
T172	15381	0	0	0
T173	12460	0	0	0
T174	11324	0	0	0
T175	16717	0	0	0
T176	18795	0	0	0
T177	100127	0	0	0
T178	5352	0	0	0
T179	22389	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	408046496	0	0
T1	219091	999527	0	0
T2	13075	4947	0	0
T3	5043	98	0	0
T4	504764	958	0	0
T5	19562	673	0	0
T6	27806	2679	0	0
T7	13630	6210	0	0
T8	10804	2597	0	0
T9	15640	4652	0	0
T10	10210	2992	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	408046496	0	0
T1	219091	999527	0	0
T2	13075	4947	0	0
T3	5043	98	0	0
T4	504764	958	0	0
T5	19562	673	0	0
T6	27806	2679	0	0
T7	13630	6210	0	0
T8	10804	2597	0	0
T9	15640	4652	0	0
T10	10210	2992	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	47	0	0
T16	923218	0	0	0
T61	15846	0	0	0
T63	13730	0	0	0
T84	91204	0	0	0
T85	64346	0	0	0
T98	12824	0	0	0
T103	11528	1	0	0
T129	0	1	0	0
T133	13913	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T151	15442	0	0	0
T152	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	22796	0	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	1006035935	0	0
T1	219091	113140	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	379773	0	0
T5	19562	0	0	0
T6	27806	2300	0	0
T7	13630	6892	0	0
T8	10804	0	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T11	0	144941	0	0
T29	0	3404	0	0
T53	0	2487	0	0
T94	0	10312	0	0
T96	0	1866	0	0
T125	0	3180	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160	1160	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	10384	0	0
T1	219091	33	0	0
T2	13075	0	0	0
T3	5043	0	0	0
T4	504764	13	0	0
T5	19562	0	0	0
T6	27806	1	0	0
T7	13630	21	0	0
T8	10804	0	0	0
T9	15640	0	0	0
T10	10210	0	0	0
T11	0	69	0	0
T29	0	6	0	0
T53	0	5	0	0
T94	0	27	0	0
T96	0	2	0	0
T97	0	11	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	1314218	0	0
T6	27806	2830	0	0
T11	197565	0	0	0
T29	64199	0	0	0
T34	24085	0	0	0
T53	49035	0	0	0
T54	0	318	0	0
T57	12703	0	0	0
T60	13358	0	0	0
T83	0	2592	0	0
T84	0	1414	0	0
T85	0	6361	0	0
T87	0	935	0	0
T94	18564	0	0	0
T95	11920	0	0	0
T96	19420	0	0	0
T160	0	7276	0	0
T180	0	1459	0	0
T181	0	4870	0	0
T182	0	1994	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	18833283	0	0
T6	27806	20168	0	0
T11	197565	0	0	0
T29	64199	0	0	0
T30	0	34583	0	0
T34	24085	0	0	0
T53	49035	37767	0	0
T54	0	26731	0	0
T57	12703	0	0	0
T60	13358	0	0	0
T83	0	33331	0	0
T84	0	80252	0	0
T94	18564	0	0	0
T95	11920	0	0	0
T96	19420	6983	0	0
T103	0	3391	0	0
T105	0	2457	0	0
T125	0	2365	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2098301949	2097475901	0	0
T1	219091	219090	0	0
T2	13075	12830	0	0
T3	5043	4984	0	0
T4	504764	504762	0	0
T5	19562	19038	0	0
T6	27806	27322	0	0
T7	13630	13522	0	0
T8	10804	10490	0	0
T9	15640	15362	0	0
T10	10210	9938	0	0