Unified Coverage Report :: Module :: otp_ctrl_part_buf

Module : otp_ctrl_part_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.27	82.87	74.90		87.23	74.18	97.14

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf	76.97	68.46	70.83		95.24	68.52	81.82
tb.dut.gen_partitions[3].gen_buffered.u_part_buf	77.42	77.99	76.09		79.31	74.29	79.41
tb.dut.gen_partitions[4].gen_buffered.u_part_buf	84.62	89.31	76.92		86.11	82.19	88.57
tb.dut.gen_partitions[5].gen_buffered.u_part_buf	84.62	89.31	76.92		86.11	82.19	88.57
tb.dut.gen_partitions[6].gen_buffered.u_part_buf	85.76	89.31	76.92		86.11	82.19	94.29

Line Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1736,StateWidth=12 )
Line Coverage for Module self-instances :

SCORE	LINE
77.42	77.99

tb.dut.gen_partitions[3].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		159	124	77.99
CONT_ASSIGN	182	1	1	100.00
ALWAYS	195	140	105	75.00
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
ALWAYS	738	3	3	100.00
ALWAYS	741	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
195	1	1
198	1	1
201	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
218	1	1
219	1	1
222	1	1
223	1	1
226	1	1
227	1	1
229	1	1
234	1	1
235	1	1
			MISSING_ELSE
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
260	1	1
261	1	1
264	1	1
265		unreachable
267	1	1
268	1	1
271	1	1
272	1	1
			MISSING_ELSE
275	1	1
276	1	1
			MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292	0	1
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305	0	1
306	0	1
			==> MISSING_ELSE
313	1	1
314	1	1
315	1	1
320		unreachable
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
332	1	1
337	1	1
338	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
			MISSING_ELSE
351	1	1
352	1	1
355	1	1
357	1	1
358	1	1
359	1	1
362	0	1
363	0	1
365	0	1
370		unreachable
374		unreachable
375		unreachable
376		unreachable
379		unreachable
380		unreachable
383		unreachable
384		unreachable
386		unreachable
390	1	1
391	0	1
			MISSING_ELSE
394	0	1
395	0	1
397	0	1
			MISSING_ELSE
406	1	1
407	1	1
408	1	1
409	1	1
412	1	1
413	1	1
414		unreachable
415		unreachable
416		unreachable
			==> MISSING_ELSE
421	1	1
422	1	1
423	1	1
			MISSING_ELSE
432		unreachable
433		unreachable
434		unreachable
			==> MISSING_ELSE
444	0	1
445	0	1
446	0	1
447	0	1
448	0	1
449	0	1
			==> MISSING_ELSE
456	0	1
457	0	1
458	0	1
459	0	1
			==> MISSING_ELSE
469	1	1
470	1	1
471	1	1
472	1	1
474	1	1
478	1	1
479	0	1
480	0	1
482	1	1
483	1	1
487	1	1
488	1	1
			MISSING_ELSE
492	1	1
493		unreachable
			MISSING_ELSE
			MISSING_ELSE
505	1	1
506	1	1
507	1	1
508	1	1
509	1	1
			==> MISSING_ELSE
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
531	1	1
532	1	1
533	1	1
536	1	1
537	1	1
540	1	1
541	1	1
545	1	1
549	1	1
550	1	1
552	1	1
			MISSING_ELSE
561	1	1
562	1	1
563	1	1
			MISSING_ELSE
567	1	1
568	1	1
584	1	1
585	0	1
586	0	1
587	0	1
			==> MISSING_ELSE
			MISSING_ELSE
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
			MISSING_ELSE
			MISSING_ELSE
624	1	1
629	1	1
630	1	1
634	1	1
640	1	1
663	1	1
666	1	1
668	1	1
697	1	1
731	1	1
738	3	3
741	1	1
742	1	1
744	1	1
746	1	1
747	1	1

---

Line Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=3,DigestOffset=1776,StateWidth=12 )
Line Coverage for Module self-instances :

SCORE	LINE
84.62	89.31

tb.dut.gen_partitions[4].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		159	142	89.31
CONT_ASSIGN	182	1	1	100.00
ALWAYS	195	140	123	87.86
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
ALWAYS	738	3	3	100.00
ALWAYS	741	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
195	1	1
198	1	1
201	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
218	1	1
219	1	1
222	1	1
223	1	1
226	1	1
227	1	1
229	1	1
234	1	1
235	1	1
			MISSING_ELSE
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
260	1	1
261	1	1
264	1	1
265	1	1
267		unreachable
268		unreachable
271	1	1
272	1	1
			MISSING_ELSE
275	1	1
276	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
313	1	1
314	1	1
315	1	1
320		unreachable
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
332	1	1
337	1	1
338	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
			MISSING_ELSE
351	1	1
352	1	1
355	1	1
357	1	1
358	1	1
359	1	1
362	0	1
363	0	1
365	0	1
370		unreachable
374		unreachable
375		unreachable
376		unreachable
379		unreachable
380		unreachable
383		unreachable
384		unreachable
386		unreachable
390	1	1
391	0	1
			MISSING_ELSE
394	0	1
395	0	1
397	0	1
			MISSING_ELSE
406	1	1
407	1	1
408	1	1
409	1	1
412	1	1
413	1	1
414	1	1
415	1	1
416	1	1
			MISSING_ELSE
421		unreachable
422		unreachable
423		unreachable
			==> MISSING_ELSE
432		unreachable
433		unreachable
434		unreachable
			==> MISSING_ELSE
444	1	1
445	1	1
446	1	1
447	1	1
448	1	1
449	1	1
			MISSING_ELSE
456	1	1
457	1	1
458	1	1
459	1	1
			MISSING_ELSE
469	1	1
470	1	1
471	1	1
472	1	1
474	1	1
478	1	1
479	1	1
480	1	1
482	0	1
483	0	1
487	1	1
488	1	1
			MISSING_ELSE
492	1	1
493	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
505	0	1
506	0	1
507	0	1
508	0	1
509	0	1
			==> MISSING_ELSE
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
531	1	1
532	1	1
533	1	1
536	1	1
537	1	1
540	1	1
541	1	1
545	1	1
549	1	1
550	1	1
552	1	1
			MISSING_ELSE
561	1	1
562	1	1
563	1	1
			MISSING_ELSE
567	1	1
568	1	1
584	1	1
585	0	1
586	0	1
587	0	1
			==> MISSING_ELSE
			MISSING_ELSE
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
			MISSING_ELSE
			MISSING_ELSE
624	1	1
629	1	1
630	1	1
634	1	1
640	1	1
663	1	1
666	1	1
668	1	1
697	1	1
717	1	1
738	3	3
741	1	1
742	1	1
744	1	1
746	1	1
747	1	1

---

Line Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1864,StateWidth=12 )
Line Coverage for Module self-instances :

SCORE	LINE
84.62	89.31

tb.dut.gen_partitions[5].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		159	142	89.31
CONT_ASSIGN	182	1	1	100.00
ALWAYS	195	140	123	87.86
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
ALWAYS	738	3	3	100.00
ALWAYS	741	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
195	1	1
198	1	1
201	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
218	1	1
219	1	1
222	1	1
223	1	1
226	1	1
227	1	1
229	1	1
234	1	1
235	1	1
			MISSING_ELSE
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
260	1	1
261	1	1
264	1	1
265	1	1
267		unreachable
268		unreachable
271	1	1
272	1	1
			MISSING_ELSE
275	1	1
276	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
313	1	1
314	1	1
315	1	1
320		unreachable
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
332	1	1
337	1	1
338	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
			MISSING_ELSE
351	1	1
352	1	1
355	1	1
357	1	1
358	1	1
359	1	1
362	0	1
363	0	1
365	0	1
370		unreachable
374		unreachable
375		unreachable
376		unreachable
379		unreachable
380		unreachable
383		unreachable
384		unreachable
386		unreachable
390	1	1
391	0	1
			MISSING_ELSE
394	0	1
395	0	1
397	0	1
			MISSING_ELSE
406	1	1
407	1	1
408	1	1
409	1	1
412	1	1
413	1	1
414	1	1
415	1	1
416	1	1
			MISSING_ELSE
421		unreachable
422		unreachable
423		unreachable
			==> MISSING_ELSE
432		unreachable
433		unreachable
434		unreachable
			==> MISSING_ELSE
444	1	1
445	1	1
446	1	1
447	1	1
448	1	1
449	1	1
			MISSING_ELSE
456	1	1
457	1	1
458	1	1
459	1	1
			MISSING_ELSE
469	1	1
470	1	1
471	1	1
472	1	1
474	1	1
478	1	1
479	1	1
480	1	1
482	0	1
483	0	1
487	1	1
488	1	1
			MISSING_ELSE
492	1	1
493	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
505	0	1
506	0	1
507	0	1
508	0	1
509	0	1
			==> MISSING_ELSE
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
531	1	1
532	1	1
533	1	1
536	1	1
537	1	1
540	1	1
541	1	1
545	1	1
549	1	1
550	1	1
552	1	1
			MISSING_ELSE
561	1	1
562	1	1
563	1	1
			MISSING_ELSE
567	1	1
568	1	1
584	1	1
585	0	1
586	0	1
587	0	1
			==> MISSING_ELSE
			MISSING_ELSE
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
			MISSING_ELSE
			MISSING_ELSE
624	1	1
629	1	1
630	1	1
634	1	1
640	1	1
663	1	1
666	1	1
668	1	1
697	1	1
717	1	1
738	3	3
741	1	1
742	1	1
744	1	1
746	1	1
747	1	1

---

Line Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1952,StateWidth=12 )
Line Coverage for Module self-instances :

SCORE	LINE
85.76	89.31

tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		159	142	89.31
CONT_ASSIGN	182	1	1	100.00
ALWAYS	195	140	123	87.86
CONT_ASSIGN	624	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
ALWAYS	738	3	3	100.00
ALWAYS	741	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
195	1	1
198	1	1
201	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
218	1	1
219	1	1
222	1	1
223	1	1
226	1	1
227	1	1
229	1	1
234	1	1
235	1	1
			MISSING_ELSE
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
260	1	1
261	1	1
264	1	1
265	1	1
267		unreachable
268		unreachable
271	1	1
272	1	1
			MISSING_ELSE
275	1	1
276	1	1
			MISSING_ELSE
287	1	1
288	1	1
289	1	1
290	1	1
291	1	1
292	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
			MISSING_ELSE
313	1	1
314	1	1
315	1	1
320		unreachable
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
332	1	1
337	1	1
338	1	1
			==> MISSING_ELSE
340	1	1
341	1	1
			MISSING_ELSE
351	1	1
352	1	1
355	1	1
357	1	1
358	1	1
359	1	1
362	0	1
363	0	1
365	0	1
370		unreachable
374		unreachable
375		unreachable
376		unreachable
379		unreachable
380		unreachable
383		unreachable
384		unreachable
386		unreachable
390	1	1
391	0	1
			MISSING_ELSE
394	0	1
395	0	1
397	0	1
			MISSING_ELSE
406	1	1
407	1	1
408	1	1
409	1	1
412	1	1
413	1	1
414	1	1
415	1	1
416	1	1
			MISSING_ELSE
421		unreachable
422		unreachable
423		unreachable
			==> MISSING_ELSE
432		unreachable
433		unreachable
434		unreachable
			==> MISSING_ELSE
444	1	1
445	1	1
446	1	1
447	1	1
448	1	1
449	1	1
			MISSING_ELSE
456	1	1
457	1	1
458	1	1
459	1	1
			MISSING_ELSE
469	1	1
470	1	1
471	1	1
472	1	1
474	1	1
478	1	1
479	1	1
480	1	1
482	0	1
483	0	1
487	1	1
488	1	1
			MISSING_ELSE
492	1	1
493	1	1
			==> MISSING_ELSE
			==> MISSING_ELSE
505	0	1
506	0	1
507	0	1
508	0	1
509	0	1
			==> MISSING_ELSE
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
531	1	1
532	1	1
533	1	1
536	1	1
537	1	1
540	1	1
541	1	1
545	1	1
549	1	1
550	1	1
552	1	1
			MISSING_ELSE
561	1	1
562	1	1
563	1	1
			MISSING_ELSE
567	1	1
568	1	1
584	1	1
585	0	1
586	0	1
587	0	1
			==> MISSING_ELSE
			MISSING_ELSE
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
			MISSING_ELSE
			MISSING_ELSE
624	1	1
629	1	1
630	1	1
634	1	1
640	1	1
663	1	1
666	1	1
668	1	1
697	1	1
717	1	1
738	3	3
741	1	1
742	1	1
744	1	1
746	1	1
747	1	1

---

Line Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=2040,StateWidth=12 )
Line Coverage for Module self-instances :

SCORE	LINE
76.97	68.46

tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Line No.	Total	Covered	Percent
TOTAL		130	89	68.46
CONT_ASSIGN	182	1	1	100.00
ALWAYS	195	111	73	65.77
CONT_ASSIGN	624	1	0	0.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	640	1	1	100.00
CONT_ASSIGN	663	1	1	100.00
CONT_ASSIGN	666	1	1	100.00
CONT_ASSIGN	668	1	1	100.00
CONT_ASSIGN	711	1	0	0.00
CONT_ASSIGN	731	1	0	0.00
ALWAYS	738	3	3	100.00
ALWAYS	741	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
182	1	1
195	1	1
198	1	1
201	1	1
204	1	1
207	1	1
208	1	1
209	1	1
210	1	1
213	1	1
214	1	1
215	1	1
218	1	1
219	1	1
222	1	1
223	1	1
226	1	1
227	1	1
229	1	1
234	1	1
235	1	1
			MISSING_ELSE
243	1	1
244	1	1
245	1	1
			MISSING_ELSE
254	1	1
255	1	1
256	1	1
260	1	1
261	1	1
264	1	1
265		unreachable
267	1	1
268	1	1
271	1	1
272	1	1
			MISSING_ELSE
275	1	1
276	1	1
			MISSING_ELSE
287	0	1
288	0	1
289	0	1
290	0	1
291	0	1
292		unreachable
			==> MISSING_ELSE
300	0	1
301	0	1
302	0	1
303	0	1
304		unreachable
305		unreachable
306		unreachable
			==> MISSING_ELSE
313	1	1
314	1	1
315		unreachable
320	1	1
322	1	1
323	1	1
324	1	1
			MISSING_ELSE
332	1	1
337	1	1
338		unreachable
			MISSING_ELSE
340	1	1
341	1	1
			MISSING_ELSE
351	1	1
352	1	1
355	1	1
357		unreachable
358		unreachable
359		unreachable
362		unreachable
363		unreachable
365		unreachable
370	1	1
374	1	1
375	1	1
376	1	1
379	1	1
380	1	1
383	1	1
384	1	1
386	1	1
390	1	1
391	0	1
			MISSING_ELSE
394	0	1
395	0	1
397	0	1
			MISSING_ELSE
406	1	1
407		unreachable
408		unreachable
409		unreachable
412		unreachable
413		unreachable
414		unreachable
415		unreachable
416		unreachable
			==> MISSING_ELSE
421		unreachable
422		unreachable
423		unreachable
			==> MISSING_ELSE
432	1	1
433	1	1
434	1	1
			==> MISSING_ELSE
444	0	1
445	0	1
446	0	1
447	0	1
448	0	1
449		unreachable
			==> MISSING_ELSE
456	0	1
457	0	1
458	0	1
459		unreachable
			==> MISSING_ELSE
469	0	1
470	0	1
471	0	1
472		unreachable
474		unreachable
478		unreachable
479		unreachable
480		unreachable
482		unreachable
483		unreachable
487		unreachable
488		unreachable
			==> MISSING_ELSE
492		unreachable
493		unreachable
			==> MISSING_ELSE
			==> MISSING_ELSE
505	0	1
506	0	1
507	0	1
508	0	1
509		unreachable
			==> MISSING_ELSE
517	0	1
518	0	1
519	0	1
520	0	1
521		unreachable
			==> MISSING_ELSE
531	0	1
532	0	1
533	0	1
536		unreachable
537		unreachable
540		unreachable
541		unreachable
545		unreachable
549		unreachable
550		unreachable
552		unreachable
			==> MISSING_ELSE
561	1	1
562	1	1
563	1	1
			MISSING_ELSE
567	1	1
568	1	1
584	1	1
585	0	1
586	0	1
587	0	1
			==> MISSING_ELSE
			MISSING_ELSE
591	1	1
592	1	1
593	1	1
594	1	1
595	1	1
			MISSING_ELSE
			MISSING_ELSE
624	0	1
629	1	1
630	1	1
634	1	1
640	1	1
663	1	1
666	1	1
668	1	1
711	0	1
731	0	1
738	3	3
741	1	1
742	1	1
744	1	1
746	1	1
747	1	1

---

Cond Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1952,StateWidth=12 )
Cond Coverage for Module self-instances :

SCORE	COND
85.76	76.92

tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	52	40	76.92
Logical	52	40	76.92
Non-Logical	0	0
Event	0	0

 LINE       260
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T24,T25,T26

 LINE       291
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       357
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       357
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       374
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       390
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Not Covered

 LINE       415
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       422
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       474
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T27,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T29

 LINE       536
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       536
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T4,T7,T29
1	Covered	T1,T2,T3

 LINE       562
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       586
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       594
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11101010000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       624
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       640
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       666
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       697
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       697
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       717
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

 LINE       717
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T29

---

Cond Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=3,DigestOffset=1776,StateWidth=12 )
Cond Coverage for Module self-instances :

SCORE	COND
84.62	76.92

tb.dut.gen_partitions[4].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	52	40	76.92
Logical	52	40	76.92
Non-Logical	0	0
Event	0	0

 LINE       260
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T30,T31,T32

 LINE       291
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       357
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       357
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       374
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       390
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Not Covered

 LINE       415
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       422
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       474
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T33
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T5,T6

 LINE       536
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T5,T6

 LINE       536
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T2,T17,T18
1	Covered	T1,T2,T3

 LINE       562
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       586
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       594
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T18

 LINE       624
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011010000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       624
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       640
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       666
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       697
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       697
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       717
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       717
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

---

Cond Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=2040,StateWidth=12 )
Cond Coverage for Module self-instances :

SCORE	COND
76.97	70.83

tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Total	Covered	Percent
Conditions	24	17	70.83
Logical	24	17	70.83
Non-Logical	0	0
Event	0	0

 LINE       260
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T34,T32

 LINE       291
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       357
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       357
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       357
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       374
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Covered	T4,T6,T21

 LINE       390
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Not Covered

 LINE       415
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       422
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       474
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       536
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       536
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       536
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       562
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       586
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       594
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11110101000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       624
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       640
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       640
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       666
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1736,StateWidth=12 )
Cond Coverage for Module self-instances :

SCORE	COND
77.42	76.09

tb.dut.gen_partitions[3].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	48	35	72.92
Logical	48	35	72.92
Non-Logical	0	0
Event	0	0

 LINE       260
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T35,T36

 LINE       291
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       357
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       357
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       357
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       374
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       390
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Not Covered

 LINE       415
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       422
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       474
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T18,T37,T38
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7

 LINE       536
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T7

 LINE       536
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T18,T4,T5
1	Covered	T1,T2,T3

 LINE       562
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       586
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       594
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11010000000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       624
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       640
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       666
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       697
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

 LINE       697
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T18

---

Cond Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1864,StateWidth=12 )
Cond Coverage for Module self-instances :

SCORE	COND
84.62	76.92

tb.dut.gen_partitions[5].gen_buffered.u_part_buf

	Total	Covered	Percent
Conditions	52	40	76.92
Logical	52	40	76.92
Non-Logical	0	0
Event	0	0

 LINE       260
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T32,T39

 LINE       291
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       357
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       357
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       357
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Not Covered
1	Covered	T4,T6,T21

 LINE       374
 EXPRESSION (cnt == LastScrmblBlock)
            ------------1-----------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       390
 EXPRESSION (otp_err_e'(otp_err_i) != NoError)
            -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T6,T21
1	Not Covered

 LINE       415
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       422
 EXPRESSION (scrmbl_mtx_gnt_i && scrmbl_ready_i)
             --------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       474
 EXPRESSION (cnt == PenultimateScrmblBlock)
            ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       536
 EXPRESSION ((digest_o == data_mux) || (digest_o == '0))
             -----------1----------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T40,T41,T42
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T7,T29

 LINE       536
 SUB-EXPRESSION (digest_o == data_mux)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

 LINE       536
 SUB-EXPRESSION (digest_o == '0)
                --------1-------

-1-	Status	Tests
0	Covered	T5,T7,T29
1	Covered	T1,T2,T3

 LINE       562
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T14,T15,T16

 LINE       586
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       594
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       624
 EXPRESSION ((base_sel == DigOffset) ? DigestOffset : 11'b11011111000)
             -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       624
 SUB-EXPRESSION (base_sel == DigOffset)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T21

 LINE       640
 EXPRESSION ((data_sel == ScrmblData) ? scrmbl_data_i : otp_rdata_i)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       640
 SUB-EXPRESSION (data_sel == ScrmblData)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       666
 EXPRESSION (init_done_o ? data : DataDefault)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       697
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

 LINE       697
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

 LINE       717
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

 LINE       717
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T7,T29

---

FSM Coverage for Module : otp_ctrl_part_buf

Summary for FSM :: state_q

	Total	Covered	Percent
States	16	16	100.00	(Not included in score)
Transitions	38	36	94.74
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
CnstyReadSt	323	Covered	T4,T6,T21
CnstyReadWaitSt	341	Covered	T4,T6,T21
ErrorSt	275	Covered	T1,T2,T3
IdleSt	358	Covered	T1,T2,T3
InitDescrSt	265	Covered	T1,T2,T3
InitDescrWaitSt	292	Covered	T1,T2,T3
InitSt	235	Covered	T1,T2,T3
InitWaitSt	245	Covered	T1,T2,T3
IntegDigClrSt	261	Covered	T1,T2,T3
IntegDigFinSt	480	Covered	T1,T2,T3
IntegDigPadSt	482	Covered	T1,T2,T3
IntegDigSt	423	Covered	T1,T2,T3
IntegDigWaitSt	521	Covered	T1,T2,T3
IntegScrSt	416	Covered	T1,T2,T3
IntegScrWaitSt	449	Covered	T1,T2,T3
ResetSt	233	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CnstyReadSt->CnstyReadWaitSt	341	Covered	T4,T6,T21
CnstyReadSt->ErrorSt	585	Covered	T43
CnstyReadWaitSt->CnstyReadSt	379	Covered	T4,T6,T21
CnstyReadWaitSt->ErrorSt	362	Covered	T32,T44,T45
CnstyReadWaitSt->IdleSt	358	Covered	T4,T6,T21
IdleSt->CnstyReadSt	323	Covered	T4,T6,T21
IdleSt->ErrorSt	585	Covered	T1,T2,T9
IdleSt->IntegDigClrSt	315	Covered	T9,T4,T8
InitDescrSt->ErrorSt	585	Covered	T2,T17,T18
InitDescrSt->InitDescrWaitSt	292	Covered	T1,T2,T3
InitDescrWaitSt->ErrorSt	585	Covered	T2,T3,T17
InitDescrWaitSt->InitSt	304	Covered	T1,T2,T3
InitSt->ErrorSt	585	Covered	T3,T19,T46
InitSt->InitWaitSt	245	Covered	T1,T2,T3
InitWaitSt->ErrorSt	275	Covered	T3,T19,T20
InitWaitSt->InitDescrSt	265	Covered	T1,T2,T3
InitWaitSt->InitSt	267	Covered	T1,T2,T3
InitWaitSt->IntegDigClrSt	261	Covered	T1,T2,T3
IntegDigClrSt->ErrorSt	585	Covered	T2,T17,T33
IntegDigClrSt->IdleSt	432	Covered	T1,T2,T3
IntegDigClrSt->IntegDigSt	423	Covered	T1,T2,T3
IntegDigClrSt->IntegScrSt	416	Covered	T1,T2,T3
IntegDigFinSt->ErrorSt	585	Covered	T47
IntegDigFinSt->IntegDigWaitSt	521	Covered	T1,T2,T3
IntegDigPadSt->ErrorSt	585	Not Covered
IntegDigPadSt->IntegDigFinSt	509	Covered	T1,T2,T3
IntegDigSt->ErrorSt	585	Not Covered
IntegDigSt->IntegDigFinSt	480	Covered	T1,T2,T3
IntegDigSt->IntegDigPadSt	482	Covered	T1,T2,T3
IntegDigSt->IntegScrSt	493	Covered	T1,T2,T3
IntegDigWaitSt->ErrorSt	549	Covered	T2,T17,T18
IntegDigWaitSt->IdleSt	537	Covered	T1,T2,T3
IntegScrSt->ErrorSt	585	Covered	T48,T40,T41
IntegScrSt->IntegScrWaitSt	449	Covered	T1,T2,T3
IntegScrWaitSt->ErrorSt	585	Covered	T49,T50,T51
IntegScrWaitSt->IntegDigSt	459	Covered	T1,T2,T3
ResetSt->ErrorSt	585	Covered	T52,T53,T54
ResetSt->InitSt	235	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	9	5	55.56
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
CheckFailError	363	Covered	T2,T17,T18
FsmStateError	563	Covered	T1,T2,T3
MacroEccCorrError	272	Covered	T19,T20,T35
NoError	562	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
CheckFailError->FsmStateError	595	Not Covered
CheckFailError->MacroEccCorrError	272	Not Covered
FsmStateError->CheckFailError	363	Not Covered
FsmStateError->MacroEccCorrError	272	Not Covered
MacroEccCorrError->CheckFailError	363	Covered	T32,T44,T45
MacroEccCorrError->FsmStateError	595	Covered	T19,T20,T35
NoError->CheckFailError	363	Covered	T2,T17,T18
NoError->FsmStateError	563	Covered	T1,T2,T3
NoError->MacroEccCorrError	272	Covered	T19,T20,T35

---

Branch Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=2040,StateWidth=12 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
76.97	68.52

tb.dut.gen_partitions[7].gen_lifecycle.u_part_buf

	Line No.	Total	Covered	Percent
Branches		56	37	66.07
TERNARY	624	2	1	50.00
TERNARY	640	2	1	50.00
TERNARY	666	2	2	100.00
CASE	229	40	25	62.50
IF	584	3	1	33.33
IF	591	3	3	100.00
IF	738	2	2	100.00
IF	741	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	624	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	640	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	666	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	case (state_q)
-2-:	234	if (init_req_i)
-3-:	244	if (otp_gnt_i)
-4-:	254	if (otp_rvalid_i)
-5-:	256	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-6-:	260	if ((cnt == LastScrmblBlock))
-7-:	264	if (1'b0)
-8-:	271	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	291	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	303	if (scrmbl_valid_i)
-11-:	313	if (integ_chk_req_i)
-12-:	314	if (1'b0)
-13-:	322	if (cnsty_chk_req_i)
-14-:	337	if (1'b0)
-15-:	340	if (otp_gnt_i)
-16-:	351	if (otp_rvalid_i)
-17-:	352	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-18-:	355	if (1'b0)
-19-:	357	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	370	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	374	if ((cnt == LastScrmblBlock))
-22-:	390	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	406	if (1'b0)
-24-:	413	if (1'b0)
-25-:	415	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	422	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	433	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	448	if (scrmbl_ready_i)
-29-:	458	if (scrmbl_valid_i)
-30-:	471	if (scrmbl_ready_i)
-31-:	474	if ((cnt == PenultimateScrmblBlock))
-32-:	478	if (cnt[0])
-33-:	487	if (cnt[0])
-34-:	492	if (1'b0)
-35-:	508	if (scrmbl_ready_i)
-36-:	520	if (scrmbl_ready_i)
-37-:	533	if (scrmbl_valid_i)
-38-:	536	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	540	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	562	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T34,T32
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T47,T55
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T4,T8
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T44,T45
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Unreachable
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Unreachable
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	584	if (ecc_err)
-2-:	586	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	591	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	594	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	738	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	741	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=4,DigestOffset=1736,StateWidth=12 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
77.42	74.29

tb.dut.gen_partitions[3].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		70	52	74.29
TERNARY	624	2	2	100.00
TERNARY	640	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	697	2	2	100.00
CASE	229	52	36	69.23
IF	584	3	1	33.33
IF	591	3	3	100.00
IF	738	2	2	100.00
IF	741	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	624	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	640	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	666	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	697	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	case (state_q)
-2-:	234	if (init_req_i)
-3-:	244	if (otp_gnt_i)
-4-:	254	if (otp_rvalid_i)
-5-:	256	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-6-:	260	if ((cnt == LastScrmblBlock))
-7-:	264	if (1'b0)
-8-:	271	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	291	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	303	if (scrmbl_valid_i)
-11-:	313	if (integ_chk_req_i)
-12-:	314	if (1'b1)
-13-:	322	if (cnsty_chk_req_i)
-14-:	337	if (1'b1)
-15-:	340	if (otp_gnt_i)
-16-:	351	if (otp_rvalid_i)
-17-:	352	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-18-:	355	if (1'b1)
-19-:	357	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	370	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	374	if ((cnt == LastScrmblBlock))
-22-:	390	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	406	if (1'b1)
-24-:	413	if (1'b0)
-25-:	415	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	422	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	433	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	448	if (scrmbl_ready_i)
-29-:	458	if (scrmbl_valid_i)
-30-:	471	if (scrmbl_ready_i)
-31-:	474	if ((cnt == PenultimateScrmblBlock))
-32-:	478	if (cnt[0])
-33-:	487	if (cnt[0])
-34-:	492	if (1'b0)
-35-:	508	if (scrmbl_ready_i)
-36-:	520	if (scrmbl_ready_i)
-37-:	533	if (scrmbl_valid_i)
-38-:	536	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	540	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	562	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T35,T36
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T56,T57,T58
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T4,T8
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Unreachable
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T9,T4,T8
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T18,T37,T38
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	584	if (ecc_err)
-2-:	586	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	591	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	594	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	738	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	741	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_buf ( parameter Info=-1,CntWidth=3,DigestOffset=1776,StateWidth=12 + Info=-1,CntWidth=4,DigestOffset=1864,StateWidth=12 + Info=-1,CntWidth=4,DigestOffset=1952,StateWidth=12 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
84.62	82.19

tb.dut.gen_partitions[4].gen_buffered.u_part_buf

SCORE	BRANCH
84.62	82.19

tb.dut.gen_partitions[5].gen_buffered.u_part_buf

SCORE	BRANCH
85.76	82.19

tb.dut.gen_partitions[6].gen_buffered.u_part_buf

	Line No.	Total	Covered	Percent
Branches		73	60	82.19
TERNARY	624	2	2	100.00
TERNARY	640	2	2	100.00
TERNARY	666	2	2	100.00
TERNARY	697	2	2	100.00
TERNARY	717	2	2	100.00
CASE	229	53	42	79.25
IF	584	3	1	33.33
IF	591	3	3	100.00
IF	738	2	2	100.00
IF	741	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_buf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	624	((base_sel == DigOffset)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T21
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	640	((data_sel == ScrmblData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	666	(init_done_o) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	697	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	717	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	229	case (state_q)
-2-:	234	if (init_req_i)
-3-:	244	if (otp_gnt_i)
-4-:	254	if (otp_rvalid_i)
-5-:	256	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-6-:	260	if ((cnt == LastScrmblBlock))
-7-:	264	if (1'b1)
-8-:	271	if ((otp_err_e'(otp_err_i) != NoError))
-9-:	291	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-10-:	303	if (scrmbl_valid_i)
-11-:	313	if (integ_chk_req_i)
-12-:	314	if (1'b1)
-13-:	322	if (cnsty_chk_req_i)
-14-:	337	if (1'b1)
-15-:	340	if (otp_gnt_i)
-16-:	351	if (otp_rvalid_i)
-17-:	352	if ((otp_err_e'(otp_err_i) inside {NoError, MacroEccCorrError}))
-18-:	355	if (1'b1)
-19-:	357	if (((digest_o == data_mux) || (digest_o == '0)))
-20-:	370	if (((scrmbl_data_o == data_mux) || lc_ctrl_pkg::lc_tx_test_true_strict(check_byp_en_i)))
-21-:	374	if ((cnt == LastScrmblBlock))
-22-:	390	if ((otp_err_e'(otp_err_i) != NoError))
-23-:	406	if (1'b1)
-24-:	413	if (1'b1)
-25-:	415	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-26-:	422	if ((scrmbl_mtx_gnt_i && scrmbl_ready_i))
-27-:	433	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-28-:	448	if (scrmbl_ready_i)
-29-:	458	if (scrmbl_valid_i)
-30-:	471	if (scrmbl_ready_i)
-31-:	474	if ((cnt == PenultimateScrmblBlock))
-32-:	478	if (cnt[0])
-33-:	487	if (cnt[0])
-34-:	492	if (1'b1)
-35-:	508	if (scrmbl_ready_i)
-36-:	520	if (scrmbl_ready_i)
-37-:	533	if (scrmbl_valid_i)
-38-:	536	if (((digest_o == data_mux) || (digest_o == '0)))
-39-:	540	if (prim_mubi_pkg::mubi8_test_true_strict(dout_locked_q))
-40-:	562	if ((error_q == NoError))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	-31-	-32-	-33-	-34-	-35-	-36-	-37-	-38-	-39-	-40-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	1	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
InitWaitSt	-	-	1	1	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T30,T31
InitWaitSt	-	-	1	1	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T20,T35
InitWaitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrWaitSt	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitDescrWaitSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T4,T8
IdleSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IdleSt	-	-	-	-	-	-	-	-	-	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
IdleSt	-	-	-	-	-	-	-	-	-	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CnstyReadWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T21
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
IntegDigClrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegScrWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	0	-	-	-	-	-	-	Not Covered
IntegDigSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
IntegDigPadSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
IntegDigFinSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	Covered	T1,T2,T3
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	0	-	Covered	T9,T4,T8
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T17,T33
IntegDigWaitSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T15,T16
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15,T16

	LineNo.	Expression
-1-:	584	if (ecc_err)
-2-:	586	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	591	if ((lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i) || cnt_err))
-2-:	594	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	738	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	741	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_buf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	34	97.14
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	34	97.14

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	130250080	129033470	0	0
BypassEnable0_A	130250080	77420082	0	0
BypassEnable1_A	130250080	103226776	0	0
CnstyChkAckKnown_A	130250080	129033470	0	0
DataKnown_A	130250080	129033470	0	0
DigestKnown_A	130250080	129033470	0	0
DigestOffsetMustBeRepresentable_A	2760	2760	0	0
EccErrorState_A	130250080	0	0	0
ErrorKnown_A	130250080	129033470	0	0
InitDoneKnown_A	130250080	129033470	0	0
InitReadLocksPartition_A	130250080	35997073	0	0
InitWriteLocksPartition_A	130250080	35997073	0	0
IntegChkAckKnown_A	130250080	129033470	0	0
OffsetMustBeBlockAligned_A	2760	2760	0	0
OtpAddrKnown_A	130250080	129033470	0	0
OtpCmdKnown_A	130250080	129033470	0	0
OtpErrorState_A	26050016	22	0	0
OtpReqKnown_A	130250080	129033470	0	0
OtpSizeKnown_A	130250080	129033470	0	0
OtpWdataKnown_A	130250080	129033470	0	0
ReadLockImpliesDigest_A	130250080	103226776	0	0
ReadLockPropagation_A	130250080	26552278	0	0
ScrambledImpliesDigest_A	130250080	77420082	0	0
ScrmblCmdKnown_A	130250080	129033470	0	0
ScrmblDataKnown_A	129146250	127929640	0	0
ScrmblModeKnown_A	130250080	129033470	0	0
ScrmblMtxReqKnown_A	130250080	129033470	0	0
ScrmblSelKnown_A	130250080	129033470	0	0
ScrmblValidKnown_A	130250080	129033470	0	0
SizeMustBeBlockAligned_A	2760	2760	0	0
WriteLockImpliesDigest_A	130250080	77420082	0	0
WriteLockPropagation_A	130250080	26552278	0	0
gen_digest_read_lock.DigestReadLocksPartition_A	78150048	1109640	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	104200064	1675755	0	0
u_state_regs_A	130250080	129033470	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

BypassEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

BypassEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	103226776	0	0
T1	58688	57936	0	0
T2	58616	57512	0	0
T3	46412	45380	0	0
T4	99820	97692	0	0
T5	80564	78260	0	0
T9	97176	96100	0	0
T17	75508	74428	0	0
T18	62428	61348	0	0
T19	56204	55124	0	0
T20	49148	48376	0	0

CnstyChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2760	2760	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T9	5	5	0	0
T17	5	5	0	0
T18	5	5	0	0
T19	5	5	0	0
T20	5	5	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	35997073	0	0
T1	73360	60344	0	0
T2	73270	29294	0	0
T3	58015	28974	0	0
T4	124775	36718	0	0
T5	100705	28068	0	0
T9	121470	100249	0	0
T17	94385	40629	0	0
T18	78035	33811	0	0
T19	70255	31882	0	0
T20	61435	36127	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	35997073	0	0
T1	73360	60344	0	0
T2	73270	29294	0	0
T3	58015	28974	0	0
T4	124775	36718	0	0
T5	100705	28068	0	0
T9	121470	100249	0	0
T17	94385	40629	0	0
T18	78035	33811	0	0
T19	70255	31882	0	0
T20	61435	36127	0	0

IntegChkAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2760	2760	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T9	5	5	0	0
T17	5	5	0	0
T18	5	5	0	0
T19	5	5	0	0
T20	5	5	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26050016	22	0	0
T5	20141	0	0	0
T6	23159	0	0	0
T7	14644	0	0	0
T8	37926	0	0	0
T11	14160	0	0	0
T19	14051	1	0	0
T20	12287	0	0	0
T24	0	1	0	0
T29	29315	0	0	0
T33	11519	0	0	0
T46	12885	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T55	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

ReadLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	103226776	0	0
T1	58688	57936	0	0
T2	58616	57512	0	0
T3	46412	45380	0	0
T4	99820	97692	0	0
T5	80564	78260	0	0
T9	97176	96100	0	0
T17	75508	74428	0	0
T18	62428	61348	0	0
T19	56204	55124	0	0
T20	49148	48376	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	26552278	0	0
T1	29344	24056	0	0
T2	29308	14386	0	0
T3	23206	11353	0	0
T4	49910	24439	0	0
T5	40282	19581	0	0
T9	48588	24033	0	0
T17	37754	18615	0	0
T18	31214	15345	0	0
T19	28102	13789	0	0
T20	24574	12100	0	0

ScrambledImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

ScrmblCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

ScrmblDataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129146250	127929640	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

ScrmblModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

ScrmblMtxReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

ScrmblSelKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

ScrmblValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2760	2760	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T4	5	5	0	0
T5	5	5	0	0
T9	5	5	0	0
T17	5	5	0	0
T18	5	5	0	0
T19	5	5	0	0
T20	5	5	0	0

WriteLockImpliesDigest_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	77420082	0	0
T1	44016	43452	0	0
T2	43962	43134	0	0
T3	34809	34035	0	0
T4	74865	73269	0	0
T5	60423	58695	0	0
T9	72882	72075	0	0
T17	56631	55821	0	0
T18	46821	46011	0	0
T19	42153	41343	0	0
T20	36861	36282	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	26552278	0	0
T1	29344	24056	0	0
T2	29308	14386	0	0
T3	23206	11353	0	0
T4	49910	24439	0	0
T5	40282	19581	0	0
T9	48588	24033	0	0
T17	37754	18615	0	0
T18	31214	15345	0	0
T19	28102	13789	0	0
T20	24574	12100	0	0

gen_digest_read_lock.DigestReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78150048	1109640	0	0
T2	14654	3042	0	0
T3	11603	0	0	0
T4	49910	1471	0	0
T5	60423	11420	0	0
T6	46318	3676	0	0
T7	29288	4307	0	0
T8	75852	0	0	0
T9	24294	0	0	0
T11	42480	0	0	0
T12	5513	0	0	0
T13	0	7100	0	0
T17	18877	3187	0	0
T18	15607	4404	0	0
T19	28102	0	0	0
T20	24574	0	0	0
T21	52684	0	0	0
T29	29315	16568	0	0
T33	23038	3735	0	0
T40	0	4066	0	0
T46	25770	0	0	0
T63	0	5941	0	0
T64	0	1576	0	0
T65	0	4246	0	0
T66	0	2651	0	0
T67	0	4020	0	0
T68	0	1423	0	0
T69	0	4516	0	0
T70	0	3596	0	0
T71	0	5996	0	0
T72	0	4187	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104200064	1675755	0	0
T2	29308	5948	0	0
T3	23206	0	0	0
T4	74865	3651	0	0
T5	80564	17670	0	0
T6	46318	6455	0	0
T7	29288	7153	0	0
T8	75852	0	0	0
T9	48588	0	0	0
T11	56640	0	0	0
T12	5513	0	0	0
T13	0	7100	0	0
T17	37754	6238	0	0
T18	31214	8672	0	0
T19	42153	0	0	0
T20	36861	0	0	0
T21	52684	0	0	0
T29	29315	27162	0	0
T33	23038	7334	0	0
T40	0	4066	0	0
T46	25770	0	0	0
T63	0	12558	0	0
T64	0	1576	0	0
T65	0	4246	0	0
T66	0	2651	0	0
T67	0	4020	0	0
T68	0	1423	0	0
T69	0	4516	0	0
T70	0	3596	0	0
T71	0	5996	0	0
T72	0	4187	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130250080	129033470	0	0
T1	73360	72420	0	0
T2	73270	71890	0	0
T3	58015	56725	0	0
T4	124775	122115	0	0
T5	100705	97825	0	0
T9	121470	120125	0	0
T17	94385	93035	0	0
T18	78035	76685	0	0
T19	70255	68905	0	0
T20	61435	60470	0	0