Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	84.62						84.62

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.62						84.62

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	11	84.62
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	11	84.62

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2757561	8700	0	0
check_regwen_rd_A	2757561	1143	0	0
check_timeout_rd_A	2757561	162	0	0
check_trigger_regwen_rd_A	2757561	902	0	0
consistency_check_period_rd_A	2757561	1022	0	0
creator_sw_cfg_read_lock_rd_A	2757561	242	0	0
direct_access_address_rd_A	2757561	55	0	0
direct_access_wdata_0_rd_A	2757561	0	0	0
direct_access_wdata_1_rd_A	2757561	0	0	0
integrity_check_period_rd_A	2757561	1024	0	0
intr_enable_rd_A	2757561	1348	0	0
owner_sw_cfg_read_lock_rd_A	2757561	156	0	0
vendor_test_read_lock_rd_A	2757561	190	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	8700	0	0
T1	60665	1	0	0
T2	9387	267	0	0
T3	64800	4	0	0
T4	8872	5	0	0
T5	65099	4	0	0
T6	3807	0	0	0
T11	72412	1	0	0
T12	5617	0	0	0
T13	3738	0	0	0
T14	6733	0	0	0
T15	0	545	0	0
T16	0	279	0	0
T17	0	148	0	0
T24	0	5	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	1143	0	0
T6	3807	0	0	0
T14	6733	18	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	22	0	0
T20	0	4	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T26	0	52	0	0
T27	39845	324	0	0
T31	0	6	0	0
T34	59508	0	0	0
T37	0	71	0	0
T40	0	55	0	0
T42	0	7	0	0
T61	0	17	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	162	0	0
T6	3807	0	0	0
T14	6733	32	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	13	0	0
T20	0	6	0	0
T22	0	10	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T27	39845	0	0	0
T34	59508	0	0	0
T40	0	11	0	0
T51	0	5	0	0
T61	0	14	0	0
T62	0	7	0	0
T63	0	5	0	0
T64	0	12	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	902	0	0
T6	3807	0	0	0
T14	6733	2	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	10	0	0
T20	0	5	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T26	0	42	0	0
T27	39845	296	0	0
T31	0	1	0	0
T34	59508	0	0	0
T37	0	71	0	0
T40	0	26	0	0
T42	0	14	0	0
T62	0	3	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	1022	0	0
T6	3807	0	0	0
T14	6733	24	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	3	0	0
T20	0	11	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T26	0	28	0	0
T27	39845	247	0	0
T31	0	3	0	0
T34	59508	0	0	0
T37	0	70	0	0
T40	0	57	0	0
T42	0	5	0	0
T61	0	22	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	242	0	0
T6	3807	0	0	0
T14	6733	13	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	9	0	0
T20	0	7	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T27	39845	0	0	0
T34	59508	0	0	0
T40	0	68	0	0
T51	0	13	0	0
T57	0	11	0	0
T61	0	17	0	0
T64	0	24	0	0
T65	0	28	0	0
T66	0	52	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	55	0	0
T10	3600	0	0	0
T19	9813	11	0	0
T20	7027	2	0	0
T21	7056	0	0	0
T30	5642	0	0	0
T31	3434	0	0	0
T32	7706	0	0	0
T51	0	15	0	0
T61	0	13	0	0
T62	0	1	0	0
T63	0	9	0	0
T67	0	4	0	0
T68	4010	0	0	0
T69	3478	0	0	0
T70	4027	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	1024	0	0
T6	3807	0	0	0
T14	6733	17	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	11	0	0
T20	0	5	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T26	0	38	0	0
T27	39845	297	0	0
T31	0	9	0	0
T34	59508	0	0	0
T37	0	70	0	0
T40	0	29	0	0
T42	0	5	0	0
T62	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	1348	0	0
T6	3807	0	0	0
T8	0	25	0	0
T14	6733	11	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	8	0	0
T20	0	4	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T26	0	69	0	0
T27	39845	249	0	0
T31	0	8	0	0
T34	59508	0	0	0
T45	0	22	0	0
T47	0	6	0	0
T69	0	7	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	156	0	0
T6	3807	0	0	0
T14	6733	6	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	6	0	0
T20	0	7	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T27	39845	0	0	0
T34	59508	0	0	0
T40	0	1	0	0
T51	0	10	0	0
T57	0	4	0	0
T61	0	9	0	0
T63	0	6	0	0
T64	0	41	0	0
T65	0	34	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	190	0	0
T6	3807	0	0	0
T14	6733	20	0	0
T15	15008	0	0	0
T16	4831	0	0	0
T17	6848	0	0	0
T19	0	8	0	0
T20	0	7	0	0
T23	4018	0	0	0
T24	111255	0	0	0
T25	56453	0	0	0
T27	39845	0	0	0
T34	59508	0	0	0
T40	0	38	0	0
T51	0	9	0	0
T61	0	11	0	0
T62	0	8	0	0
T63	0	8	0	0
T64	0	22	0	0
T65	0	13	0	0