Unified Coverage Report :: Module :: otp_ctrl_core_reg_top

Module : otp_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.87			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	97.22	100.00	88.87			100.00	100.00

---

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.87			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.54	97.49	91.87	89.91		98.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
6.75	0.00	0.00	27.01		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_bus_integ_error	100.00	100.00
u_alert_test_fatal_check_error	100.00	100.00
u_alert_test_fatal_macro_error	100.00	100.00
u_alert_test_fatal_prim_otp_alert	100.00	100.00
u_alert_test_recov_prim_otp_alert	100.00	100.00
u_check_regwen	100.00	100.00	100.00			100.00
u_check_timeout	65.34	88.89	50.00			57.14
u_check_trigger_consistency	100.00	100.00
u_check_trigger_integrity	100.00	100.00
u_check_trigger_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_consistency_check_period	100.00	100.00	100.00			100.00
u_creator_sw_cfg_digest_0	66.67	66.67
u_creator_sw_cfg_digest_1	66.67	66.67
u_creator_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_direct_access_address	100.00	100.00	100.00			100.00
u_direct_access_cmd_digest	100.00	100.00
u_direct_access_cmd_rd	100.00	100.00
u_direct_access_cmd_wr	100.00	100.00
u_direct_access_rdata_0	100.00	100.00
u_direct_access_rdata_1	100.00	100.00
u_direct_access_regwen	100.00	100.00
u_direct_access_wdata_0	100.00	100.00	100.00			100.00
u_direct_access_wdata_1	100.00	100.00	100.00			100.00
u_err_code_0	66.67	66.67
u_err_code_1	66.67	66.67
u_err_code_2	66.67	66.67
u_err_code_3	66.67	66.67
u_err_code_4	100.00	100.00
u_err_code_5	100.00	100.00
u_err_code_6	100.00	100.00
u_err_code_7	100.00	100.00
u_err_code_8	66.67	66.67
u_err_code_9	100.00	100.00
u_hw_cfg0_digest_0	66.67	66.67
u_hw_cfg0_digest_1	66.67	66.67
u_integrity_check_period	100.00	100.00	100.00			100.00
u_intr_enable_otp_error	100.00	100.00	100.00			100.00
u_intr_enable_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_state_otp_error	100.00	100.00	100.00			100.00
u_intr_state_otp_operation_done	100.00	100.00	100.00			100.00
u_intr_test_otp_error	100.00	100.00
u_intr_test_otp_operation_done	100.00	100.00
u_owner_sw_cfg_digest_0	66.67	66.67
u_owner_sw_cfg_digest_1	100.00	100.00
u_owner_sw_cfg_read_lock	100.00	100.00	100.00			100.00
u_prim_reg_we_check	50.00	100.00		0.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_secret0_digest_0	66.67	66.67
u_secret0_digest_1	66.67	66.67
u_secret1_digest_0	66.67	66.67
u_secret1_digest_1	100.00	100.00
u_secret2_digest_0	66.67	66.67
u_secret2_digest_1	66.67	66.67
u_socket	99.24	98.75	98.21			100.00	100.00
u_status_bus_integ_error	100.00	100.00
u_status_check_pending	100.00	100.00
u_status_creator_sw_cfg_error	100.00	100.00
u_status_dai_error	100.00	100.00
u_status_dai_idle	100.00	100.00
u_status_hw_cfg0_error	100.00	100.00
u_status_key_deriv_fsm_error	100.00	100.00
u_status_lci_error	100.00	100.00
u_status_lfsr_fsm_error	100.00	100.00
u_status_life_cycle_error	100.00	100.00
u_status_owner_sw_cfg_error	100.00	100.00
u_status_scrambling_fsm_error	100.00	100.00
u_status_secret0_error	100.00	100.00
u_status_secret1_error	100.00	100.00
u_status_secret2_error	100.00	100.00
u_status_timeout_error	100.00	100.00
u_status_vendor_test_error	100.00	100.00
u_vendor_test_digest_0	100.00	100.00
u_vendor_test_digest_1	100.00	100.00
u_vendor_test_read_lock	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		286	286	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	423	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	507	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	539	1	1	100.00
CONT_ASSIGN	972	1	1	100.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	992	1	1	100.00
CONT_ASSIGN	995	1	1	100.00
CONT_ASSIGN	1010	1	1	100.00
CONT_ASSIGN	1026	1	1	100.00
CONT_ASSIGN	1042	1	1	100.00
CONT_ASSIGN	1048	1	1	100.00
CONT_ASSIGN	1080	1	1	100.00
CONT_ASSIGN	1112	1	1	100.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1223	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1366	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1428	1	1	100.00
ALWAYS	1697	46	46	100.00
CONT_ASSIGN	1745	1	1	100.00
ALWAYS	1749	1	1	100.00
CONT_ASSIGN	1798	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1807	1	1	100.00
CONT_ASSIGN	1808	1	1	100.00
CONT_ASSIGN	1810	1	1	100.00
CONT_ASSIGN	1812	1	1	100.00
CONT_ASSIGN	1813	1	1	100.00
CONT_ASSIGN	1815	1	1	100.00
CONT_ASSIGN	1817	1	1	100.00
CONT_ASSIGN	1819	1	1	100.00
CONT_ASSIGN	1821	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1824	1	1	100.00
CONT_ASSIGN	1825	1	1	100.00
CONT_ASSIGN	1826	1	1	100.00
CONT_ASSIGN	1827	1	1	100.00
CONT_ASSIGN	1828	1	1	100.00
CONT_ASSIGN	1829	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1831	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1833	1	1	100.00
CONT_ASSIGN	1834	1	1	100.00
CONT_ASSIGN	1835	1	1	100.00
CONT_ASSIGN	1836	1	1	100.00
CONT_ASSIGN	1838	1	1	100.00
CONT_ASSIGN	1839	1	1	100.00
CONT_ASSIGN	1841	1	1	100.00
CONT_ASSIGN	1843	1	1	100.00
CONT_ASSIGN	1845	1	1	100.00
CONT_ASSIGN	1846	1	1	100.00
CONT_ASSIGN	1848	1	1	100.00
CONT_ASSIGN	1849	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1852	1	1	100.00
CONT_ASSIGN	1854	1	1	100.00
CONT_ASSIGN	1855	1	1	100.00
CONT_ASSIGN	1856	1	1	100.00
CONT_ASSIGN	1857	1	1	100.00
CONT_ASSIGN	1859	1	1	100.00
CONT_ASSIGN	1860	1	1	100.00
CONT_ASSIGN	1862	1	1	100.00
CONT_ASSIGN	1864	1	1	100.00
CONT_ASSIGN	1865	1	1	100.00
CONT_ASSIGN	1867	1	1	100.00
CONT_ASSIGN	1868	1	1	100.00
CONT_ASSIGN	1870	1	1	100.00
CONT_ASSIGN	1871	1	1	100.00
CONT_ASSIGN	1873	1	1	100.00
CONT_ASSIGN	1874	1	1	100.00
CONT_ASSIGN	1876	1	1	100.00
CONT_ASSIGN	1877	1	1	100.00
CONT_ASSIGN	1879	1	1	100.00
CONT_ASSIGN	1880	1	1	100.00
CONT_ASSIGN	1882	1	1	100.00
CONT_ASSIGN	1883	1	1	100.00
CONT_ASSIGN	1885	1	1	100.00
CONT_ASSIGN	1886	1	1	100.00
CONT_ASSIGN	1887	1	1	100.00
CONT_ASSIGN	1888	1	1	100.00
CONT_ASSIGN	1889	1	1	100.00
CONT_ASSIGN	1890	1	1	100.00
CONT_ASSIGN	1891	1	1	100.00
CONT_ASSIGN	1892	1	1	100.00
CONT_ASSIGN	1893	1	1	100.00
CONT_ASSIGN	1894	1	1	100.00
CONT_ASSIGN	1895	1	1	100.00
CONT_ASSIGN	1896	1	1	100.00
CONT_ASSIGN	1897	1	1	100.00
CONT_ASSIGN	1898	1	1	100.00
CONT_ASSIGN	1899	1	1	100.00
ALWAYS	1903	46	46	100.00
ALWAYS	1953	73	73	100.00
CONT_ASSIGN	2172	0	0
CONT_ASSIGN	2180	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
423	1	1
438	1	1
454	1	1
460	1	1
475	1	1
491	1	1
507	1	1
523	1	1
539	1	1
972	1	1
986	1	1
992	1	1
995	1	1
1010	1	1
1026	1	1
1042	1	1
1048	1	1
1080	1	1
1112	1	1
1205	1	1
1208	1	1
1223	1	1
1239	1	1
1273	1	1
1304	1	1
1335	1	1
1366	1	1
1397	1	1
1428	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1702	1	1
1703	1	1
1704	1	1
1705	1	1
1706	1	1
1707	1	1
1708	1	1
1709	1	1
1710	1	1
1711	1	1
1712	1	1
1713	1	1
1714	1	1
1715	1	1
1716	1	1
1717	1	1
1718	1	1
1719	1	1
1720	1	1
1721	1	1
1722	1	1
1723	1	1
1724	1	1
1725	1	1
1726	1	1
1727	1	1
1728	1	1
1729	1	1
1730	1	1
1731	1	1
1732	1	1
1733	1	1
1734	1	1
1735	1	1
1736	1	1
1737	1	1
1738	1	1
1739	1	1
1740	1	1
1741	1	1
1742	1	1
1745	1	1
1749	1	1
1798	1	1
1800	1	1
1802	1	1
1803	1	1
1805	1	1
1807	1	1
1808	1	1
1810	1	1
1812	1	1
1813	1	1
1815	1	1
1817	1	1
1819	1	1
1821	1	1
1823	1	1
1824	1	1
1825	1	1
1826	1	1
1827	1	1
1828	1	1
1829	1	1
1830	1	1
1831	1	1
1832	1	1
1833	1	1
1834	1	1
1835	1	1
1836	1	1
1838	1	1
1839	1	1
1841	1	1
1843	1	1
1845	1	1
1846	1	1
1848	1	1
1849	1	1
1851	1	1
1852	1	1
1854	1	1
1855	1	1
1856	1	1
1857	1	1
1859	1	1
1860	1	1
1862	1	1
1864	1	1
1865	1	1
1867	1	1
1868	1	1
1870	1	1
1871	1	1
1873	1	1
1874	1	1
1876	1	1
1877	1	1
1879	1	1
1880	1	1
1882	1	1
1883	1	1
1885	1	1
1886	1	1
1887	1	1
1888	1	1
1889	1	1
1890	1	1
1891	1	1
1892	1	1
1893	1	1
1894	1	1
1895	1	1
1896	1	1
1897	1	1
1898	1	1
1899	1	1
1903	1	1
1904	1	1
1905	1	1
1906	1	1
1907	1	1
1908	1	1
1909	1	1
1910	1	1
1911	1	1
1912	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1925	1	1
1926	1	1
1927	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1953	1	1
1954	1	1
1956	1	1
1957	1	1
1961	1	1
1962	1	1
1966	1	1
1967	1	1
1971	1	1
1972	1	1
1973	1	1
1974	1	1
1975	1	1
1979	1	1
1980	1	1
1981	1	1
1982	1	1
1983	1	1
1984	1	1
1985	1	1
1986	1	1
1987	1	1
1988	1	1
1989	1	1
1990	1	1
1991	1	1
1992	1	1
1993	1	1
1994	1	1
1995	1	1
1999	1	1
2003	1	1
2007	1	1
2011	1	1
2015	1	1
2019	1	1
2023	1	1
2027	1	1
2031	1	1
2035	1	1
2039	1	1
2043	1	1
2044	1	1
2045	1	1
2049	1	1
2053	1	1
2057	1	1
2061	1	1
2065	1	1
2069	1	1
2073	1	1
2074	1	1
2078	1	1
2082	1	1
2086	1	1
2090	1	1
2094	1	1
2098	1	1
2102	1	1
2106	1	1
2110	1	1
2114	1	1
2118	1	1
2122	1	1
2126	1	1
2130	1	1
2134	1	1
2138	1	1
2142	1	1
2146	1	1
2150	1	1
2154	1	1
2158	1	1
2172		unreachable
2180	1	1
2181	1	1

---

Cond Coverage for Module : otp_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	512	455	88.87
Logical	512	455	88.87
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-1855	93.27
1856-1899	69.79

---

Branch Coverage for Module : otp_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	1745	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	1954	46	46	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_core_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1745	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1954	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T2,T3,T4
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T3,T4
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T3,T4
addr_hit[7]	Covered	T1,T3,T5
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T3,T4
addr_hit[15]	Covered	T1,T3,T4
addr_hit[16]	Covered	T3,T4,T11
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T3,T4
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T2,T3,T4
addr_hit[26]	Covered	T1,T3,T4
addr_hit[27]	Covered	T1,T3,T4
addr_hit[28]	Covered	T2,T3,T4
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T3,T4,T5
addr_hit[31]	Covered	T1,T3,T4
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T3,T4
addr_hit[37]	Covered	T1,T3,T4
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	2757561	43355	0	0
reAfterRv	2757561	43354	0	0
rePulse	2757561	18007	0	0
wePulse	2757561	25347	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	43355	0	0
T1	60665	490	0	0
T2	9387	4	0	0
T3	64800	497	0	0
T4	8872	69	0	0
T5	65099	495	0	0
T6	3807	20	0	0
T11	72412	489	0	0
T12	5617	276	0	0
T13	3738	1	0	0
T14	6733	316	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	43354	0	0
T1	60665	490	0	0
T2	9387	4	0	0
T3	64800	497	0	0
T4	8872	69	0	0
T5	65099	495	0	0
T6	3807	20	0	0
T11	72412	489	0	0
T12	5617	276	0	0
T13	3738	1	0	0
T14	6733	316	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	18007	0	0
T1	60665	113	0	0
T2	9387	2	0	0
T3	64800	117	0	0
T4	8872	35	0	0
T5	65099	116	0	0
T6	3807	10	0	0
T11	72412	114	0	0
T12	5617	86	0	0
T13	3738	1	0	0
T14	6733	73	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	2757561	25347	0	0
T1	60665	377	0	0
T2	9387	2	0	0
T3	64800	380	0	0
T4	8872	34	0	0
T5	65099	379	0	0
T6	3807	10	0	0
T11	72412	375	0	0
T12	5617	190	0	0
T13	3738	0	0	0
T14	6733	243	0	0
T23	0	38	0	0