Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code

Group : otp_ctrl_env_pkg::otp_ctrl_buf_err_code_cg_wrap::buf_err_code_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
83.33	63.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
buf_err_code_cg_wrap[OtpSecret0ErrIdx]	0.00	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]	50.00	1	100	1	64	64
buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]	83.33	1	100	1	64	64
buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]	83.33	1	100	1	64	64

Group Instance : buf_err_code_cg_wrap[OtpSecret0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Summary for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	6	0	0.00

Variables for Group Instance buf_err_code_cg_wrap[OtpSecret0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	6	0	0.00	100	1	1	0

Group Instance : buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	3	3	50.00

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg1ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	3	3	50.00	100	1	1	0

Group Instance : buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Summary for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpHwCfg0ErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Group Instance : buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Summary for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpOwnerSwCfgErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthCodesignErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Group Instance : buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Summary for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance buf_err_code_cg_wrap[OtpRotCreatorAuthStateErrIdx]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	6	1	5	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	6	0	0.00

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
fsm_err	0	1	1
check_fail	0	1	1
ecc_uncorr_err	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1
no_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	3	3	50.00

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
check_fail	0	1	1
ecc_corr_err	0	1	1
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	105324	1		T4	77	T9	63	T13	1
ecc_uncorr_err	45	1		T71	1	T49	1	T133	1
no_err	149556	1		T1	70	T2	33	T3	5

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	105175	1		T4	77	T9	63	T64	1
check_fail	3	1		T61	1	T62	1	T63	1
ecc_uncorr_err	190	1		T13	1	T50	42	T81	39
ecc_corr_err	182	1		T40	50	T59	38	T60	3
no_err	149472	1		T1	70	T2	33	T3	5

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	105204	1		T4	77	T9	63	T17	7
check_fail	7	1		T33	1	T34	1	T35	1
ecc_uncorr_err	159	1		T82	1	T65	29	T113	1
ecc_corr_err	162	1		T17	9	T31	59	T32	24
no_err	149752	1		T1	71	T2	33	T3	5

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	105230	1		T4	77	T9	63	T64	1
check_fail	33	1		T45	1	T46	1	T47	1
ecc_uncorr_err	101	1		T83	1	T84	1	T118	1
ecc_corr_err	66	1		T44	66	-	-	-	-
no_err	149773	1		T1	71	T2	33	T3	5

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
fsm_err	105161	1		T4	77	T9	63	T13	1
check_fail	23	1		T51	1	T52	1	T53	1
ecc_uncorr_err	180	1		T80	1	T127	1	T128	1
ecc_corr_err	92	1		T31	48	T50	44	-	-
no_err	149655	1		T1	70	T2	33	T3	5