Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.24	96.15	86.96	87.79		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1382570805	15502106	0	0
check_regwen_rd_A	1382570805	3117	0	0
check_timeout_rd_A	1382570805	3581	0	0
check_trigger_regwen_rd_A	1382570805	3156	0	0
consistency_check_period_rd_A	1382570805	3506	0	0
creator_sw_cfg_read_lock_rd_A	1382570805	3384	0	0
direct_access_address_rd_A	1382570805	2877	0	0
direct_access_wdata_0_rd_A	1382570805	2234	0	0
direct_access_wdata_1_rd_A	1382570805	2758	0	0
integrity_check_period_rd_A	1382570805	2940	0	0
intr_enable_rd_A	1382570805	4083	0	0
owner_sw_cfg_read_lock_rd_A	1382570805	2827	0	0
rot_creator_auth_codesign_read_lock_rd_A	1382570805	3352	0	0
rot_creator_auth_state_read_lock_rd_A	1382570805	2853	0	0
vendor_test_read_lock_rd_A	1382570805	2835	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	15502106	0	0
T14	110854	82459	0	0
T15	216600	53353	0	0
T16	0	90204	0	0
T21	0	362722	0	0
T22	0	332830	0	0
T23	0	419035	0	0
T39	0	350044	0	0
T48	11511	0	0	0
T77	13009	0	0	0
T86	14357	0	0	0
T176	38132	0	0	0
T177	24368	0	0	0
T178	30390	0	0	0
T179	100823	0	0	0
T180	75808	0	0	0
T269	0	380992	0	0
T270	0	227226	0	0
T271	0	226753	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	3117	0	0
T89	9854	0	0	0
T240	0	362	0	0
T277	564088	472	0	0
T290	0	323	0	0
T296	0	328	0	0
T297	0	401	0	0
T322	0	161	0	0
T325	0	66	0	0
T326	0	116	0	0
T327	0	79	0	0
T328	0	151	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	3581	0	0
T89	9854	0	0	0
T240	0	393	0	0
T277	564088	650	0	0
T290	0	362	0	0
T296	0	486	0	0
T297	0	495	0	0
T322	0	246	0	0
T325	0	124	0	0
T326	0	181	0	0
T327	0	55	0	0
T328	0	203	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	3156	0	0
T89	9854	0	0	0
T240	0	313	0	0
T277	564088	496	0	0
T290	0	284	0	0
T296	0	405	0	0
T297	0	443	0	0
T322	0	160	0	0
T325	0	82	0	0
T326	0	100	0	0
T327	0	57	0	0
T328	0	148	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	3506	0	0
T89	9854	0	0	0
T240	0	373	0	0
T277	564088	558	0	0
T290	0	288	0	0
T296	0	471	0	0
T297	0	580	0	0
T322	0	169	0	0
T325	0	85	0	0
T326	0	95	0	0
T327	0	51	0	0
T328	0	190	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	3384	0	0
T89	9854	0	0	0
T240	0	462	0	0
T277	564088	503	0	0
T290	0	393	0	0
T296	0	502	0	0
T297	0	484	0	0
T322	0	125	0	0
T325	0	99	0	0
T326	0	100	0	0
T327	0	75	0	0
T328	0	201	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2877	0	0
T89	9854	0	0	0
T240	0	337	0	0
T277	564088	547	0	0
T290	0	318	0	0
T296	0	484	0	0
T297	0	560	0	0
T322	0	219	0	0
T325	0	55	0	0
T326	0	81	0	0
T327	0	53	0	0
T328	0	208	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2234	0	0
T89	9854	0	0	0
T240	0	340	0	0
T277	564088	380	0	0
T290	0	261	0	0
T296	0	391	0	0
T297	0	411	0	0
T322	0	120	0	0
T325	0	49	0	0
T326	0	114	0	0
T327	0	22	0	0
T328	0	146	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2758	0	0
T89	9854	0	0	0
T240	0	305	0	0
T277	564088	500	0	0
T290	0	329	0	0
T296	0	474	0	0
T297	0	548	0	0
T322	0	184	0	0
T325	0	65	0	0
T326	0	85	0	0
T327	0	60	0	0
T328	0	200	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2940	0	0
T89	9854	0	0	0
T240	0	264	0	0
T277	564088	431	0	0
T290	0	327	0	0
T296	0	423	0	0
T297	0	363	0	0
T322	0	185	0	0
T325	0	77	0	0
T326	0	70	0	0
T327	0	36	0	0
T328	0	128	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	4083	0	0
T5	102504	21	0	0
T20	76588	0	0	0
T31	68573	0	0	0
T80	14312	0	0	0
T95	6294	0	0	0
T96	118941	0	0	0
T97	19274	0	0	0
T98	12828	0	0	0
T99	101208	0	0	0
T100	85743	0	0	0
T126	0	38	0	0
T207	0	16	0	0
T277	0	522	0	0
T322	0	160	0	0
T325	0	105	0	0
T337	0	20	0	0
T338	0	11	0	0
T339	0	20	0	0
T340	0	30	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2827	0	0
T89	9854	0	0	0
T240	0	329	0	0
T277	564088	524	0	0
T290	0	262	0	0
T296	0	396	0	0
T297	0	410	0	0
T322	0	188	0	0
T325	0	76	0	0
T326	0	88	0	0
T327	0	71	0	0
T328	0	140	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	3352	0	0
T89	9854	0	0	0
T240	0	427	0	0
T277	564088	559	0	0
T290	0	339	0	0
T296	0	556	0	0
T297	0	473	0	0
T322	0	179	0	0
T325	0	99	0	0
T326	0	142	0	0
T327	0	63	0	0
T328	0	185	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2853	0	0
T89	9854	0	0	0
T240	0	376	0	0
T277	564088	565	0	0
T290	0	249	0	0
T296	0	394	0	0
T297	0	387	0	0
T322	0	173	0	0
T325	0	87	0	0
T326	0	86	0	0
T327	0	54	0	0
T328	0	130	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1382570805	2835	0	0
T89	9854	0	0	0
T240	0	377	0	0
T277	564088	408	0	0
T290	0	308	0	0
T296	0	405	0	0
T297	0	450	0	0
T322	0	109	0	0
T325	0	107	0	0
T326	0	84	0	0
T327	0	59	0	0
T328	0	135	0	0
T329	26704	0	0	0
T330	24263	0	0	0
T331	506794	0	0	0
T332	40410	0	0	0
T333	18422	0	0	0
T334	12327	0	0	0
T335	13739	0	0	0
T336	14084	0	0	0