Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.27	96.15	86.96	87.95		93.10	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1611330803	19176412	0	0
check_regwen_rd_A	1611330803	4509	0	0
check_timeout_rd_A	1611330803	4310	0	0
check_trigger_regwen_rd_A	1611330803	4527	0	0
consistency_check_period_rd_A	1611330803	5192	0	0
creator_sw_cfg_read_lock_rd_A	1611330803	4525	0	0
direct_access_address_rd_A	1611330803	3526	0	0
direct_access_wdata_0_rd_A	1611330803	2621	0	0
direct_access_wdata_1_rd_A	1611330803	3615	0	0
integrity_check_period_rd_A	1611330803	4763	0	0
intr_enable_rd_A	1611330803	5130	0	0
owner_sw_cfg_read_lock_rd_A	1611330803	3617	0	0
rot_creator_auth_codesign_read_lock_rd_A	1611330803	4007	0	0
rot_creator_auth_state_read_lock_rd_A	1611330803	3848	0	0
vendor_test_read_lock_rd_A	1611330803	4021	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	19176412	0	0
T5	271197	505178	0	0
T6	30988	0	0	0
T8	89789	0	0	0
T9	11588	0	0	0
T10	42821	0	0	0
T11	0	175846	0	0
T12	0	309529	0	0
T13	34894	0	0	0
T15	0	342525	0	0
T25	50598	0	0	0
T37	0	306626	0	0
T68	12348	0	0	0
T78	0	404612	0	0
T113	8171	0	0	0
T114	74200	0	0	0
T149	0	728467	0	0
T166	0	494470	0	0
T289	0	117199	0	0
T290	0	261842	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4509	0	0
T16	0	59	0	0
T18	0	186	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	39	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	370	0	0
T271	0	318	0	0
T289	210343	128	0	0
T291	0	132	0	0
T292	0	73	0	0
T338	0	26	0	0
T339	0	323	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4310	0	0
T16	0	133	0	0
T18	0	243	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	41	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	307	0	0
T271	0	302	0	0
T289	210343	185	0	0
T291	0	106	0	0
T292	0	93	0	0
T338	0	38	0	0
T339	0	334	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4527	0	0
T16	0	79	0	0
T18	0	165	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	70	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	281	0	0
T271	0	351	0	0
T289	210343	124	0	0
T291	0	113	0	0
T292	0	36	0	0
T338	0	27	0	0
T339	0	356	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	5192	0	0
T16	0	112	0	0
T18	0	159	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	43	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	263	0	0
T271	0	418	0	0
T289	210343	156	0	0
T291	0	106	0	0
T292	0	105	0	0
T338	0	38	0	0
T339	0	414	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4525	0	0
T16	0	86	0	0
T18	0	302	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	64	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	317	0	0
T271	0	391	0	0
T289	210343	118	0	0
T291	0	159	0	0
T292	0	104	0	0
T338	0	27	0	0
T339	0	394	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	3526	0	0
T16	0	79	0	0
T18	0	290	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	65	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	289	0	0
T271	0	297	0	0
T289	210343	124	0	0
T291	0	101	0	0
T292	0	119	0	0
T338	0	43	0	0
T339	0	369	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	2621	0	0
T16	0	93	0	0
T18	0	168	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	31	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	216	0	0
T271	0	298	0	0
T289	210343	118	0	0
T291	0	82	0	0
T292	0	59	0	0
T338	0	6	0	0
T339	0	314	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	3615	0	0
T16	0	79	0	0
T18	0	242	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	39	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	286	0	0
T271	0	393	0	0
T289	210343	99	0	0
T291	0	131	0	0
T292	0	133	0	0
T338	0	35	0	0
T339	0	397	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4763	0	0
T16	0	88	0	0
T18	0	265	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	65	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	349	0	0
T271	0	350	0	0
T289	210343	107	0	0
T291	0	124	0	0
T292	0	102	0	0
T338	0	23	0	0
T339	0	288	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	5130	0	0
T16	0	73	0	0
T18	0	222	0	0
T57	47130	0	0	0
T73	0	16	0	0
T130	0	15	0	0
T139	23281	0	0	0
T141	0	52	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	224	0	0
T271	0	343	0	0
T289	210343	69	0	0
T291	0	71	0	0
T292	0	117	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	3617	0	0
T16	0	59	0	0
T18	0	146	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	48	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	259	0	0
T271	0	322	0	0
T289	210343	109	0	0
T291	0	119	0	0
T292	0	68	0	0
T338	0	39	0	0
T339	0	336	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4007	0	0
T16	0	48	0	0
T18	0	247	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	60	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	257	0	0
T271	0	328	0	0
T289	210343	138	0	0
T291	0	86	0	0
T292	0	67	0	0
T338	0	38	0	0
T339	0	403	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	3848	0	0
T16	0	132	0	0
T18	0	211	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	58	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	208	0	0
T271	0	263	0	0
T289	210343	127	0	0
T291	0	79	0	0
T292	0	70	0	0
T338	0	35	0	0
T339	0	373	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1611330803	4021	0	0
T16	0	119	0	0
T18	0	203	0	0
T57	47130	0	0	0
T139	23281	0	0	0
T141	0	49	0	0
T199	17744	0	0	0
T221	12206	0	0	0
T242	23807	0	0	0
T265	0	294	0	0
T271	0	428	0	0
T289	210343	116	0	0
T291	0	150	0	0
T292	0	113	0	0
T338	0	48	0	0
T339	0	394	0	0
T340	15765	0	0	0
T341	14177	0	0	0
T342	4449	0	0	0
T343	199854	0	0	0