Unified Coverage Report :: Group :: push_pull_agent_pkg::req_ack_cg

Group : push_pull_agent_pkg::req_ack_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_push_pull_agent_0.1/push_pull_agent_cov.sv

9 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg	100.00	1	100	1	64	64

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	474694	1			T1	560		T3	3182		T4	98
auto[2]	475327	1			T1	560		T3	3182		T4	98
auto[3]	474733	1			T1	560		T3	3182		T4	98

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5438	1			T1	6		T3	33		T4	1
auto[2]	6045	1			T1	6		T3	33		T4	1
auto[3]	5438	1			T1	6		T3	33		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5431	1			T1	6		T3	33		T4	1
auto[2]	6183	1			T1	6		T3	35		T4	1
auto[3]	5431	1			T1	6		T3	33		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	11664	1			T1	23		T3	50		T4	1
auto[2]	12438	1			T1	31		T3	51		T4	1
auto[3]	11705	1			T1	23		T3	50		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5404	1			T1	6		T3	33		T4	1
auto[2]	6165	1			T1	6		T3	33		T4	1
auto[3]	5404	1			T1	6		T3	33		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5383	1			T1	6		T3	33		T4	1
auto[2]	6043	1			T1	6		T3	34		T4	1
auto[3]	5384	1			T1	6		T3	33		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5367	1			T1	6		T3	33		T4	1
auto[2]	5938	1			T1	6		T3	34		T4	1
auto[3]	5368	1			T1	6		T3	33		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5396	1			T1	6		T3	33		T4	1
auto[2]	5871	1			T1	6		T3	34		T4	1
auto[3]	5396	1			T1	6		T3	33		T4	1

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5296	1			T1	6		T3	32		T4	1
auto[2]	5908	1			T1	6		T3	34		T4	1
auto[3]	5397	1			T1	6		T3	33		T4	1