Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.67						86.67

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	86.67						86.67

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.67						86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.67						86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
7.56	0.00	0.00	30.25		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2943931	7671	0	0
check_regwen_rd_A	2943931	1631	0	0
check_timeout_rd_A	2943931	765	0	0
check_trigger_regwen_rd_A	2943931	1797	0	0
consistency_check_period_rd_A	2943931	1810	0	0
creator_sw_cfg_read_lock_rd_A	2943931	740	0	0
direct_access_address_rd_A	2943931	31	0	0
direct_access_wdata_0_rd_A	2943931	0	0	0
direct_access_wdata_1_rd_A	2943931	0	0	0
integrity_check_period_rd_A	2943931	1828	0	0
intr_enable_rd_A	2943931	2337	0	0
owner_sw_cfg_read_lock_rd_A	2943931	800	0	0
rot_creator_auth_codesign_read_lock_rd_A	2943931	855	0	0
rot_creator_auth_state_read_lock_rd_A	2943931	823	0	0
vendor_test_read_lock_rd_A	2943931	844	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	7671	0	0
T4	61983	1	0	0
T5	6380	33	0	0
T6	61632	1	0	0
T7	9565	92	0	0
T8	3431	0	0	0
T9	37973	0	0	0
T10	4086	0	0	0
T11	3409	0	0	0
T12	3444	0	0	0
T14	0	44	0	0
T16	8206	0	0	0
T19	0	192	0	0
T20	0	145	0	0
T21	0	279	0	0
T22	0	504	0	0
T23	0	51	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	1631	0	0
T4	61983	29	0	0
T5	6380	0	0	0
T6	61632	0	0	0
T7	9565	0	0	0
T8	3431	0	0	0
T9	37973	0	0	0
T10	4086	0	0	0
T11	3409	0	0	0
T12	3444	0	0	0
T16	8206	0	0	0
T17	0	94	0	0
T18	0	17	0	0
T27	0	339	0	0
T28	0	40	0	0
T29	0	9	0	0
T30	0	8	0	0
T34	0	1	0	0
T52	0	21	0	0
T54	0	37	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	765	0	0
T14	10559	0	0	0
T17	121611	0	0	0
T18	12840	49	0	0
T23	7926	0	0	0
T24	5590	0	0	0
T28	63599	0	0	0
T32	9470	0	0	0
T35	0	6	0	0
T52	7247	27	0	0
T53	0	5	0	0
T54	0	53	0	0
T57	0	1	0	0
T58	0	10	0	0
T59	0	3	0	0
T60	0	1	0	0
T61	0	208	0	0
T62	3695	0	0	0
T63	3601	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	1797	0	0
T2	3864	4	0	0
T3	3386	0	0	0
T4	61983	28	0	0
T5	6380	0	0	0
T6	61632	0	0	0
T8	3431	0	0	0
T9	37973	0	0	0
T10	4086	0	0	0
T12	3444	0	0	0
T15	3567	0	0	0
T17	0	73	0	0
T18	0	30	0	0
T27	0	434	0	0
T28	0	39	0	0
T29	0	2	0	0
T30	0	11	0	0
T52	0	18	0	0
T53	0	22	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	1810	0	0
T2	3864	9	0	0
T3	3386	0	0	0
T4	61983	39	0	0
T5	6380	0	0	0
T6	61632	0	0	0
T8	3431	0	0	0
T9	37973	0	0	0
T10	4086	0	0	0
T12	3444	0	0	0
T15	3567	0	0	0
T17	0	96	0	0
T18	0	28	0	0
T27	0	437	0	0
T28	0	39	0	0
T29	0	3	0	0
T30	0	1	0	0
T52	0	33	0	0
T53	0	16	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	740	0	0
T14	10559	0	0	0
T17	121611	0	0	0
T18	12840	46	0	0
T23	7926	0	0	0
T24	5590	0	0	0
T28	63599	0	0	0
T32	9470	0	0	0
T35	0	5	0	0
T52	7247	13	0	0
T53	0	17	0	0
T54	0	68	0	0
T57	0	1	0	0
T58	0	5	0	0
T59	0	4	0	0
T60	0	5	0	0
T61	0	197	0	0
T62	3695	0	0	0
T63	3601	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	31	0	0
T35	9856	2	0	0
T36	4201	0	0	0
T37	3949	0	0	0
T47	0	8	0	0
T55	3819	0	0	0
T57	10108	3	0	0
T58	10338	8	0	0
T59	0	3	0	0
T60	0	1	0	0
T64	0	6	0	0
T65	3411	0	0	0
T66	3229	0	0	0
T67	10002	0	0	0
T68	3410	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	1828	0	0
T2	3864	5	0	0
T3	3386	0	0	0
T4	61983	27	0	0
T5	6380	0	0	0
T6	61632	0	0	0
T8	3431	0	0	0
T9	37973	0	0	0
T10	4086	0	0	0
T12	3444	0	0	0
T15	3567	0	0	0
T17	0	84	0	0
T18	0	73	0	0
T27	0	401	0	0
T28	0	23	0	0
T29	0	7	0	0
T30	0	10	0	0
T52	0	40	0	0
T53	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	2337	0	0
T1	4300	23	0	0
T2	3864	4	0	0
T3	3386	0	0	0
T4	61983	55	0	0
T5	6380	0	0	0
T6	61632	0	0	0
T9	37973	0	0	0
T10	4086	0	0	0
T12	3444	0	0	0
T15	3567	0	0	0
T27	0	491	0	0
T29	0	5	0	0
T30	0	12	0	0
T40	0	20	0	0
T50	0	9	0	0
T69	0	9	0	0
T70	0	23	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	800	0	0
T14	10559	0	0	0
T17	121611	0	0	0
T18	12840	31	0	0
T23	7926	0	0	0
T24	5590	0	0	0
T28	63599	0	0	0
T32	9470	0	0	0
T35	0	8	0	0
T52	7247	7	0	0
T53	0	22	0	0
T54	0	52	0	0
T57	0	11	0	0
T58	0	6	0	0
T59	0	5	0	0
T60	0	2	0	0
T61	0	222	0	0
T62	3695	0	0	0
T63	3601	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	855	0	0
T14	10559	0	0	0
T17	121611	0	0	0
T18	12840	26	0	0
T23	7926	0	0	0
T24	5590	0	0	0
T28	63599	0	0	0
T32	9470	0	0	0
T35	0	7	0	0
T44	0	407	0	0
T52	7247	13	0	0
T53	0	2	0	0
T54	0	116	0	0
T57	0	7	0	0
T58	0	18	0	0
T60	0	3	0	0
T61	0	247	0	0
T62	3695	0	0	0
T63	3601	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	823	0	0
T14	10559	0	0	0
T17	121611	0	0	0
T18	12840	57	0	0
T23	7926	0	0	0
T24	5590	0	0	0
T28	63599	0	0	0
T32	9470	0	0	0
T35	0	6	0	0
T44	0	430	0	0
T52	7247	26	0	0
T53	0	15	0	0
T54	0	32	0	0
T57	0	3	0	0
T58	0	6	0	0
T59	0	3	0	0
T61	0	240	0	0
T62	3695	0	0	0
T63	3601	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2943931	844	0	0
T14	10559	0	0	0
T17	121611	0	0	0
T18	12840	40	0	0
T23	7926	0	0	0
T24	5590	0	0	0
T28	63599	0	0	0
T32	9470	0	0	0
T35	0	1	0	0
T52	7247	68	0	0
T53	0	12	0	0
T54	0	62	0	0
T57	0	17	0	0
T58	0	3	0	0
T59	0	5	0	0
T60	0	1	0	0
T61	0	243	0	0
T62	3695	0	0	0
T63	3601	0	0	0