Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	96.75	96.15	96.85		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	446824300	7572081	0	0
check_regwen_rd_A	446824300	3521	0	0
check_timeout_rd_A	446824300	2290	0	0
check_trigger_regwen_rd_A	446824300	3649	0	0
consistency_check_period_rd_A	446824300	3574	0	0
creator_sw_cfg_read_lock_rd_A	446824300	2423	0	0
direct_access_address_rd_A	446824300	1905	0	0
direct_access_wdata_0_rd_A	446824300	1071	0	0
direct_access_wdata_1_rd_A	446824300	1245	0	0
integrity_check_period_rd_A	446824300	3476	0	0
intr_enable_rd_A	446824300	4493	0	0
owner_sw_cfg_read_lock_rd_A	446824300	2148	0	0
rot_creator_auth_codesign_read_lock_rd_A	446824300	2181	0	0
rot_creator_auth_state_read_lock_rd_A	446824300	2195	0	0
vendor_test_read_lock_rd_A	446824300	1960	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	7572081	0	0
T6	675008	148363	0	0
T7	13558	0	0	0
T8	571747	152483	0	0
T14	0	252195	0	0
T17	0	133953	0	0
T27	67346	0	0	0
T28	53592	0	0	0
T42	21541	0	0	0
T65	0	79053	0	0
T66	0	207351	0	0
T92	37517	0	0	0
T93	32872	0	0	0
T99	16682	0	0	0
T108	52557	0	0	0
T215	0	58519	0	0
T270	0	40834	0	0
T271	0	69716	0	0
T272	0	85952	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	3521	0	0
T65	862257	98	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	147	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	99	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	46	0	0
T314	0	50	0	0
T315	0	94	0	0
T316	0	87	0	0
T317	0	3	0	0
T318	0	140	0	0
T319	0	32	0	0
T320	15249	0	0	0
T321	119283	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	2290	0	0
T65	862257	73	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	134	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	116	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	57	0	0
T314	0	55	0	0
T315	0	90	0	0
T316	0	103	0	0
T317	0	72	0	0
T318	0	140	0	0
T319	0	72	0	0
T320	15249	0	0	0
T321	119283	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	3649	0	0
T65	862257	72	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	173	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	61	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	56	0	0
T314	0	47	0	0
T315	0	71	0	0
T316	0	72	0	0
T317	0	44	0	0
T318	0	134	0	0
T319	0	52	0	0
T320	15249	0	0	0
T321	119283	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	3574	0	0
T65	862257	104	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	245	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	78	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	59	0	0
T314	0	61	0	0
T315	0	87	0	0
T316	0	83	0	0
T317	0	56	0	0
T318	0	122	0	0
T319	0	47	0	0
T320	15249	0	0	0
T321	119283	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	2423	0	0
T65	862257	78	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	142	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	150	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	52	0	0
T314	0	75	0	0
T315	0	77	0	0
T316	0	115	0	0
T317	0	48	0	0
T318	0	152	0	0
T319	0	42	0	0
T320	15249	0	0	0
T321	119283	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	1905	0	0
T65	862257	97	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	157	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	87	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	26	0	0
T314	0	56	0	0
T315	0	134	0	0
T316	0	78	0	0
T317	0	8	0	0
T318	0	152	0	0
T319	0	42	0	0
T320	15249	0	0	0
T321	119283	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	1071	0	0
T65	862257	47	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	134	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	76	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	25	0	0
T314	0	17	0	0
T315	0	37	0	0
T316	0	63	0	0
T317	0	15	0	0
T318	0	48	0	0
T319	0	30	0	0
T320	15249	0	0	0
T321	119283	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	1245	0	0
T65	862257	59	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	112	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	77	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	35	0	0
T314	0	10	0	0
T315	0	25	0	0
T316	0	55	0	0
T317	0	34	0	0
T318	0	65	0	0
T319	0	45	0	0
T320	15249	0	0	0
T321	119283	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	3476	0	0
T65	862257	103	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	170	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	55	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	42	0	0
T314	0	52	0	0
T315	0	67	0	0
T316	0	88	0	0
T317	0	11	0	0
T318	0	133	0	0
T319	0	51	0	0
T320	15249	0	0	0
T321	119283	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	4493	0	0
T65	862257	105	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T125	0	13	0	0
T127	0	2	0	0
T132	0	22	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	105	0	0
T219	13347	0	0	0
T223	0	23	0	0
T258	41056	0	0	0
T271	0	49	0	0
T314	0	92	0	0
T315	0	88	0	0
T320	15249	0	0	0
T321	119283	0	0	0
T322	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	2148	0	0
T65	862257	101	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	170	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	63	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	73	0	0
T314	0	53	0	0
T315	0	92	0	0
T316	0	41	0	0
T317	0	65	0	0
T318	0	125	0	0
T319	0	41	0	0
T320	15249	0	0	0
T321	119283	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	2181	0	0
T65	862257	103	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	138	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	81	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	74	0	0
T314	0	49	0	0
T315	0	96	0	0
T316	0	74	0	0
T317	0	42	0	0
T318	0	164	0	0
T319	0	69	0	0
T320	15249	0	0	0
T321	119283	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	2195	0	0
T65	862257	105	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	182	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	89	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	68	0	0
T314	0	42	0	0
T315	0	80	0	0
T316	0	90	0	0
T317	0	67	0	0
T318	0	134	0	0
T319	0	67	0	0
T320	15249	0	0	0
T321	119283	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	446824300	1960	0	0
T65	862257	95	0	0
T66	991409	0	0	0
T80	11221	0	0	0
T102	84770	0	0	0
T123	0	154	0	0
T145	72812	0	0	0
T161	15007	0	0	0
T215	0	59	0	0
T219	13347	0	0	0
T258	41056	0	0	0
T271	0	45	0	0
T314	0	66	0	0
T315	0	65	0	0
T316	0	99	0	0
T317	0	19	0	0
T318	0	131	0	0
T319	0	40	0	0
T320	15249	0	0	0
T321	119283	0	0	0