Unified Coverage Report :: Group :: push_pull_agent_pkg::req_ack_cg

Group : push_pull_agent_pkg::req_ack_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_push_pull_agent_0.1/push_pull_agent_cov.sv

9 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg	100.00	1	100	1	64	64
push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg	100.00	1	100	1	64	64

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_edn_pull_agent[0].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_addr_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_flash_data_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_lc_prog_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_otbn_pull_agent.cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[0].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[1].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[2].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

---

Group Instance : push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance push_pull_agent_pkg.uvm_test_top.env.m_sram_pull_agent[3].cov::m_req_ack_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_req_ack	3	0	3	100.00	100	1	1	4

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	514601	1			T1	811		T5	726		T6	190
auto[2]	515169	1			T1	813		T5	726		T6	190
auto[3]	514664	1			T1	812		T5	726		T6	190

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5901	1			T1	16		T5	8		T6	2
auto[2]	6417	1			T1	16		T5	8		T6	2
auto[3]	5901	1			T1	16		T5	8		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5855	1			T1	15		T5	8		T6	2
auto[2]	6798	1			T1	16		T5	8		T6	2
auto[3]	5855	1			T1	15		T5	8		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	16430	1			T1	5		T4	1		T5	64
auto[2]	17159	1			T1	5		T2	1		T4	1
auto[3]	16481	1			T1	5		T4	1		T5	64

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5863	1			T1	7		T5	8		T6	2
auto[2]	6517	1			T1	9		T5	8		T6	2
auto[3]	5863	1			T1	7		T5	8		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5797	1			T1	8		T5	8		T6	2
auto[2]	6542	1			T1	11		T5	8		T6	2
auto[3]	5797	1			T1	8		T5	8		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5791	1			T1	10		T5	8		T6	2
auto[2]	6259	1			T1	11		T5	8		T6	2
auto[3]	5791	1			T1	10		T5	8		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5811	1			T1	10		T5	8		T6	2
auto[2]	6732	1			T1	11		T5	8		T6	2
auto[3]	5811	1			T1	10		T5	8		T6	2

Summary for Variable cp_req_ack

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for cp_req_ack

Excluded/Illegal bins

NAME	COUNT	STATUS
ack_wo_req	0	Excluded
[auto[1]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5717	1			T1	9		T5	8		T6	2
auto[2]	6526	1			T1	10		T5	8		T6	2
auto[3]	5811	1			T1	9		T5	8		T6	2