Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.73	96.75	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	500756550	8125096	0	0
check_regwen_rd_A	500756550	3377	0	0
check_timeout_rd_A	500756550	3084	0	0
check_trigger_regwen_rd_A	500756550	3029	0	0
consistency_check_period_rd_A	500756550	3282	0	0
creator_sw_cfg_read_lock_rd_A	500756550	3015	0	0
direct_access_address_rd_A	500756550	2342	0	0
direct_access_wdata_0_rd_A	500756550	1403	0	0
direct_access_wdata_1_rd_A	500756550	1729	0	0
integrity_check_period_rd_A	500756550	3095	0	0
intr_enable_rd_A	500756550	4144	0	0
owner_sw_cfg_read_lock_rd_A	500756550	2772	0	0
rot_creator_auth_codesign_read_lock_rd_A	500756550	2967	0	0
rot_creator_auth_state_read_lock_rd_A	500756550	2811	0	0
vendor_test_read_lock_rd_A	500756550	2746	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	8125096	0	0
T3	487273	124970	0	0
T4	478159	104091	0	0
T5	70792	0	0	0
T6	17238	0	0	0
T7	11097	0	0	0
T8	23067	0	0	0
T9	301741	58308	0	0
T10	450663	0	0	0
T12	0	110466	0	0
T13	0	42339	0	0
T14	0	167770	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T147	0	45306	0	0
T148	0	54599	0	0
T188	0	171091	0	0
T249	0	58141	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	3377	0	0
T9	301741	102	0	0
T10	450663	0	0	0
T15	0	126	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	120	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	119	0	0
T249	0	33	0	0
T269	0	101	0	0
T305	0	133	0	0
T306	0	62	0	0
T307	0	60	0	0
T308	0	28	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	3084	0	0
T9	301741	69	0	0
T10	450663	0	0	0
T15	0	144	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	140	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	159	0	0
T249	0	81	0	0
T269	0	115	0	0
T305	0	177	0	0
T306	0	85	0	0
T307	0	76	0	0
T308	0	12	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	3029	0	0
T9	301741	45	0	0
T10	450663	0	0	0
T15	0	107	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	118	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	137	0	0
T249	0	56	0	0
T269	0	113	0	0
T305	0	145	0	0
T306	0	58	0	0
T307	0	78	0	0
T308	0	15	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	3282	0	0
T9	301741	75	0	0
T10	450663	0	0	0
T15	0	147	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	90	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	189	0	0
T249	0	94	0	0
T269	0	101	0	0
T305	0	174	0	0
T306	0	60	0	0
T307	0	68	0	0
T308	0	16	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	3015	0	0
T9	301741	77	0	0
T10	450663	0	0	0
T15	0	152	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	143	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	87	0	0
T249	0	63	0	0
T269	0	86	0	0
T305	0	179	0	0
T306	0	46	0	0
T307	0	63	0	0
T308	0	28	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	2342	0	0
T9	301741	72	0	0
T10	450663	0	0	0
T15	0	155	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	81	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	149	0	0
T249	0	56	0	0
T269	0	99	0	0
T305	0	127	0	0
T306	0	30	0	0
T307	0	69	0	0
T308	0	19	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	1403	0	0
T9	301741	36	0	0
T10	450663	0	0	0
T15	0	90	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	100	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	68	0	0
T249	0	51	0	0
T269	0	51	0	0
T305	0	68	0	0
T306	0	46	0	0
T307	0	72	0	0
T308	0	15	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	1729	0	0
T9	301741	28	0	0
T10	450663	0	0	0
T15	0	147	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	99	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	108	0	0
T249	0	55	0	0
T269	0	60	0	0
T305	0	152	0	0
T306	0	33	0	0
T307	0	52	0	0
T308	0	4	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	3095	0	0
T9	301741	119	0	0
T10	450663	0	0	0
T15	0	157	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	129	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	107	0	0
T249	0	88	0	0
T269	0	85	0	0
T305	0	91	0	0
T306	0	50	0	0
T307	0	74	0	0
T308	0	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	4144	0	0
T9	301741	140	0	0
T10	450663	0	0	0
T15	0	162	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	91	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	135	0	0
T249	0	61	0	0
T269	0	144	0	0
T305	0	161	0	0
T306	0	26	0	0
T307	0	56	0	0
T308	0	32	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	2772	0	0
T9	301741	64	0	0
T10	450663	0	0	0
T15	0	177	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	122	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	121	0	0
T249	0	113	0	0
T269	0	107	0	0
T305	0	118	0	0
T306	0	49	0	0
T307	0	69	0	0
T308	0	32	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	2967	0	0
T9	301741	111	0	0
T10	450663	0	0	0
T15	0	150	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	153	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	90	0	0
T249	0	79	0	0
T269	0	122	0	0
T305	0	126	0	0
T306	0	38	0	0
T307	0	86	0	0
T308	0	19	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	2811	0	0
T9	301741	94	0	0
T10	450663	0	0	0
T15	0	162	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	137	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	125	0	0
T249	0	74	0	0
T269	0	68	0	0
T305	0	126	0	0
T306	0	46	0	0
T307	0	64	0	0
T308	0	8	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	500756550	2746	0	0
T9	301741	104	0	0
T10	450663	0	0	0
T15	0	114	0	0
T17	103436	0	0	0
T24	60799	0	0	0
T34	0	89	0	0
T78	12422	0	0	0
T108	5222	0	0	0
T118	33254	0	0	0
T119	4223	0	0	0
T120	24511	0	0	0
T121	139758	0	0	0
T247	0	140	0	0
T249	0	43	0	0
T269	0	61	0	0
T305	0	128	0	0
T306	0	36	0	0
T307	0	81	0	0
T308	0	36	0	0