Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.97	100.00	71.88			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp_rsp_fifo	98.68	100.00	94.74			100.00	100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_tlul_adapter_sram.u_reqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_sramreqfifo	100.00	100.00	100.00			100.00	100.00
tb.dut.u_tlul_adapter_sram.u_rspfifo	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_otp_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.68	100.00	94.74			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.83	100.00	92.31			95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.40	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.85	100.00	95.41			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.36	95.00	87.10			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.85	100.00	95.41			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.37	95.00	89.47			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.85	100.00	95.41			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
98.68	100.00

tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T8,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
98.68	94.74

tb.dut.u_otp_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=4,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_rspfifo

SCORE	BRANCH
98.68	100.00

tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_reqfifo

SCORE	BRANCH
100.00	100.00

tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	265155921	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	1923021860	37937781	0	0
gen_passthru_fifo.paramCheckPass	7932	7932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	265155921	0	0
T1	102890	7979	0	0
T2	1792120	146100	0	0
T3	272210	39497	0	0
T4	844180	71316	0	0
T5	518210	47697	0	0
T8	316220	14177	0	0
T9	407730	41084	0	0
T10	133920	6843	0	0
T11	2132260	9585	0	0
T12	90070	3415	0	0
T69	0	723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	102890	100040	0	0
T2	1792120	1778820	0	0
T3	272210	270490	0	0
T4	844180	830980	0	0
T5	518210	517080	0	0
T8	316220	313100	0	0
T9	407730	406110	0	0
T10	133920	130240	0	0
T11	2132260	2126670	0	0
T12	90070	77180	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	102890	100040	0	0
T2	1792120	1778820	0	0
T3	272210	270490	0	0
T4	844180	830980	0	0
T5	518210	517080	0	0
T8	316220	313100	0	0
T9	407730	406110	0	0
T10	133920	130240	0	0
T11	2132260	2126670	0	0
T12	90070	77180	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	102890	100040	0	0
T2	1792120	1778820	0	0
T3	272210	270490	0	0
T4	844180	830980	0	0
T5	518210	517080	0	0
T8	316220	313100	0	0
T9	407730	406110	0	0
T10	133920	130240	0	0
T11	2132260	2126670	0	0
T12	90070	77180	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	1923021860	37937781	0	0
T1	41156	2807	0	0
T2	716848	20808	0	0
T3	108884	2773	0	0
T4	337672	18276	0	0
T5	207284	2927	0	0
T8	126488	5261	0	0
T9	163092	22220	0	0
T10	53568	2263	0	0
T11	852904	5737	0	0
T12	36028	2295	0	0
T69	0	601	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	7932	7932	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T8	6	6	0	0
T9	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0
T12	6	6	0	0

Line Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (4'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_otp_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480755465	17961608	0	0
DepthKnown_A	480755465	479856981	0	0
RvalidKnown_A	480755465	479856981	0	0
WreadyKnown_A	480755465	479856981	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480755465	17961608	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	17961608	0	0
T1	10289	2345	0	0
T2	179212	19635	0	0
T3	27221	2440	0	0
T4	84418	17664	0	0
T5	51821	2516	0	0
T8	31622	5186	0	0
T9	40773	11356	0	0
T10	13392	2260	0	0
T11	213226	5725	0	0
T12	9007	2295	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	17961608	0	0
T1	10289	2345	0	0
T2	179212	19635	0	0
T3	27221	2440	0	0
T4	84418	17664	0	0
T5	51821	2516	0	0
T8	31622	5186	0	0
T9	40773	11356	0	0
T10	13392	2260	0	0
T11	213226	5725	0	0
T12	9007	2295	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483604379	66157732	0	0
DepthKnown_A	483604379	482654758	0	0
RvalidKnown_A	483604379	482654758	0	0
WreadyKnown_A	483604379	482654758	0	0
gen_passthru_fifo.paramCheckPass	1322	1322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	66157732	0	0
T1	10289	1293	0	0
T2	179212	11497	0	0
T3	27221	9181	0	0
T4	84418	13260	0	0
T5	51821	4054	0	0
T8	31622	808	0	0
T9	40773	4121	0	0
T10	13392	1145	0	0
T11	213226	962	0	0
T12	9007	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322	1322	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483604379	52489101	0	0
DepthKnown_A	483604379	482654758	0	0
RvalidKnown_A	483604379	482654758	0	0
WreadyKnown_A	483604379	482654758	0	0
gen_passthru_fifo.paramCheckPass	1322	1322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	52489101	0	0
T1	10289	1293	0	0
T2	179212	51149	0	0
T3	27221	9181	0	0
T4	84418	13260	0	0
T5	51821	18331	0	0
T8	31622	3650	0	0
T9	40773	5311	0	0
T10	13392	1145	0	0
T11	213226	962	0	0
T12	9007	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322	1322	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483604379	28305942	0	0
DepthKnown_A	483604379	482654758	0	0
RvalidKnown_A	483604379	482654758	0	0
WreadyKnown_A	483604379	482654758	0	0
gen_passthru_fifo.paramCheckPass	1322	1322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	28305942	0	0
T1	10289	22	0	0
T2	179212	99	0	0
T3	27221	75	0	0
T4	84418	96	0	0
T5	51821	35	0	0
T8	31622	3	0	0
T9	40773	404	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322	1322	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483604379	18510743	0	0
DepthKnown_A	483604379	482654758	0	0
RvalidKnown_A	483604379	482654758	0	0
WreadyKnown_A	483604379	482654758	0	0
gen_passthru_fifo.paramCheckPass	1322	1322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	18510743	0	0
T1	10289	22	0	0
T2	179212	424	0	0
T3	27221	75	0	0
T4	84418	96	0	0
T5	51821	152	0	0
T8	31622	18	0	0
T9	40773	1594	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322	1322	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483604379	27776264	0	0
DepthKnown_A	483604379	482654758	0	0
RvalidKnown_A	483604379	482654758	0	0
WreadyKnown_A	483604379	482654758	0	0
gen_passthru_fifo.paramCheckPass	1322	1322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	27776264	0	0
T1	10289	1271	0	0
T2	179212	11398	0	0
T3	27221	9106	0	0
T4	84418	13164	0	0
T5	51821	4019	0	0
T8	31622	805	0	0
T9	40773	3717	0	0
T10	13392	1144	0	0
T11	213226	958	0	0
T12	9007	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322	1322	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	483604379	33978358	0	0
DepthKnown_A	483604379	482654758	0	0
RvalidKnown_A	483604379	482654758	0	0
WreadyKnown_A	483604379	482654758	0	0
gen_passthru_fifo.paramCheckPass	1322	1322	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	33978358	0	0
T1	10289	1271	0	0
T2	179212	50725	0	0
T3	27221	9106	0	0
T4	84418	13164	0	0
T5	51821	18179	0	0
T8	31622	3632	0	0
T9	40773	3717	0	0
T10	13392	1144	0	0
T11	213226	958	0	0
T12	9007	280	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	483604379	482654758	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1322	1322	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480755465	19053864	0	0
DepthKnown_A	480755465	479856981	0	0
RvalidKnown_A	480755465	479856981	0	0
WreadyKnown_A	480755465	479856981	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480755465	19053864	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	19053864	0	0
T1	10289	220	0	0
T2	179212	537	0	0
T3	27221	129	0	0
T4	84418	258	0	0
T5	51821	188	0	0
T8	31622	36	0	0
T9	40773	5230	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	19053864	0	0
T1	10289	220	0	0
T2	179212	537	0	0
T3	27221	129	0	0
T4	84418	258	0	0
T5	51821	188	0	0
T8	31622	36	0	0
T9	40773	5230	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	290	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T1,T2,T3
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480755465	678092	0	0
DepthKnown_A	480755465	479856981	0	0
RvalidKnown_A	480755465	479856981	0	0
WreadyKnown_A	480755465	479856981	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480755465	678092	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	678092	0	0
T1	10289	220	0	0
T2	179212	212	0	0
T3	27221	129	0	0
T4	84418	258	0	0
T5	51821	71	0	0
T8	31622	21	0	0
T9	40773	4040	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	678092	0	0
T1	10289	220	0	0
T2	179212	212	0	0
T3	27221	129	0	0
T4	84418	258	0	0
T5	51821	71	0	0
T8	31622	21	0	0
T9	40773	4040	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	210	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T8,T5
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	480755465	244217	0	0
DepthKnown_A	480755465	479856981	0	0
RvalidKnown_A	480755465	479856981	0	0
WreadyKnown_A	480755465	479856981	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	480755465	244217	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	244217	0	0
T1	10289	22	0	0
T2	179212	424	0	0
T3	27221	75	0	0
T4	84418	96	0	0
T5	51821	152	0	0
T8	31622	18	0	0
T9	40773	1594	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	479856981	0	0
T1	10289	10004	0	0
T2	179212	177882	0	0
T3	27221	27049	0	0
T4	84418	83098	0	0
T5	51821	51708	0	0
T8	31622	31310	0	0
T9	40773	40611	0	0
T10	13392	13024	0	0
T11	213226	212667	0	0
T12	9007	7718	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	480755465	244217	0	0
T1	10289	22	0	0
T2	179212	424	0	0
T3	27221	75	0	0
T4	84418	96	0	0
T5	51821	152	0	0
T8	31622	18	0	0
T9	40773	1594	0	0
T10	13392	1	0	0
T11	213226	4	0	0
T12	9007	0	0	0
T69	0	101	0	0