Module : prim_flop_2sync
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_flop_2sync_0/rtl/prim_flop_2sync.sv
Module self-instances :
Module Instance : tb.dut.u_prim_lc_sync_escalate_en.gen_flops.u_prim_flop_2sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_escalate_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_lc_sync_creator_seed_sw_rw_en.gen_flops.u_prim_flop_2sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_creator_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_lc_sync_owner_seed_sw_rw_en.gen_flops.u_prim_flop_2sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_owner_seed_sw_rw_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_lc_sync_seed_hw_rd_en.gen_flops.u_prim_flop_2sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_seed_hw_rd_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_flops.u_prim_flop_2sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_dft_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_lc_sync_check_byp_en.gen_flops.u_prim_flop_2sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 100.00 | 100.00 | 100.00 | u_prim_lc_sync_check_byp_en |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 95.83 | 100.00 | 83.33 | 100.00 | 100.00 | u_prim_sync_reqack |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_prim_edn_req.u_prim_sync_reqack_data.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 95.83 | 100.00 | 83.33 | 100.00 | 100.00 | u_prim_sync_reqack |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_otp_init_sync
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 96.82 | 97.40 | 96.15 | 96.96 | 96.43 | 97.18 | dut |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| u_sync_1 | 100.00 | 100.00 | 100.00 | ||||
| u_sync_2 | 100.00 | 100.00 | 100.00 |