Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.73	96.75	96.15	97.12		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	489160529	8121428	0	0
check_regwen_rd_A	489160529	2908	0	0
check_timeout_rd_A	489160529	2517	0	0
check_trigger_regwen_rd_A	489160529	2699	0	0
consistency_check_period_rd_A	489160529	2898	0	0
creator_sw_cfg_read_lock_rd_A	489160529	2903	0	0
direct_access_address_rd_A	489160529	2367	0	0
direct_access_wdata_0_rd_A	489160529	1580	0	0
direct_access_wdata_1_rd_A	489160529	1710	0	0
integrity_check_period_rd_A	489160529	2730	0	0
intr_enable_rd_A	489160529	3627	0	0
owner_sw_cfg_read_lock_rd_A	489160529	2346	0	0
rot_creator_auth_codesign_read_lock_rd_A	489160529	2898	0	0
rot_creator_auth_state_read_lock_rd_A	489160529	2618	0	0
vendor_test_read_lock_rd_A	489160529	2546	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	8121428	0	0
T7	418070	106172	0	0
T13	0	19070	0	0
T14	0	61420	0	0
T16	0	219793	0	0
T17	0	279909	0	0
T57	23481	0	0	0
T59	10087	0	0	0
T61	459420	0	0	0
T66	0	27747	0	0
T91	72893	0	0	0
T92	41556	0	0	0
T100	19144	0	0	0
T101	27923	0	0	0
T132	0	88069	0	0
T152	0	52805	0	0
T188	73315	0	0	0
T215	17534	0	0	0
T244	0	70527	0	0
T245	0	39074	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2908	0	0
T13	162118	44	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	131	0	0
T134	0	80	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	53	0	0
T322	0	58	0	0
T329	0	75	0	0
T330	0	108	0	0
T331	0	56	0	0
T332	0	37	0	0
T333	0	21	0	0
T334	31960	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2517	0	0
T13	162118	16	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	120	0	0
T134	0	144	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	39	0	0
T322	0	56	0	0
T329	0	56	0	0
T330	0	108	0	0
T331	0	92	0	0
T332	0	51	0	0
T333	0	37	0	0
T334	31960	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2699	0	0
T13	162118	46	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	129	0	0
T134	0	111	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	50	0	0
T322	0	47	0	0
T329	0	71	0	0
T330	0	171	0	0
T331	0	40	0	0
T332	0	25	0	0
T333	0	45	0	0
T334	31960	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2898	0	0
T13	162118	39	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	137	0	0
T134	0	139	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	66	0	0
T322	0	45	0	0
T329	0	63	0	0
T330	0	76	0	0
T331	0	28	0	0
T332	0	37	0	0
T333	0	41	0	0
T334	31960	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2903	0	0
T13	162118	46	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	91	0	0
T134	0	163	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	58	0	0
T322	0	51	0	0
T329	0	80	0	0
T330	0	141	0	0
T331	0	54	0	0
T332	0	53	0	0
T333	0	39	0	0
T334	31960	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2367	0	0
T13	162118	34	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	100	0	0
T134	0	122	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	42	0	0
T322	0	48	0	0
T329	0	55	0	0
T330	0	129	0	0
T331	0	32	0	0
T332	0	37	0	0
T333	0	103	0	0
T334	31960	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	1580	0	0
T13	162118	19	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	67	0	0
T134	0	79	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	28	0	0
T322	0	36	0	0
T329	0	14	0	0
T330	0	120	0	0
T331	0	26	0	0
T332	0	25	0	0
T333	0	68	0	0
T334	31960	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	1710	0	0
T13	162118	37	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	72	0	0
T134	0	131	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	51	0	0
T322	0	19	0	0
T329	0	46	0	0
T330	0	50	0	0
T331	0	58	0	0
T332	0	25	0	0
T333	0	37	0	0
T334	31960	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2730	0	0
T13	162118	41	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	75	0	0
T134	0	107	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	47	0	0
T322	0	50	0	0
T329	0	44	0	0
T330	0	103	0	0
T331	0	47	0	0
T332	0	35	0	0
T333	0	59	0	0
T334	31960	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	3627	0	0
T4	757637	10	0	0
T5	85111	0	0	0
T8	10355	0	0	0
T9	17198	0	0	0
T10	78507	0	0	0
T11	13499	0	0	0
T12	167019	0	0	0
T13	0	59	0	0
T15	223705	0	0	0
T58	9635	0	0	0
T97	27629	0	0	0
T121	0	38	0	0
T133	0	93	0	0
T134	0	146	0	0
T245	0	88	0	0
T261	0	22	0	0
T322	0	54	0	0
T329	0	57	0	0
T330	0	121	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2346	0	0
T13	162118	37	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	152	0	0
T134	0	128	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	45	0	0
T322	0	60	0	0
T329	0	43	0	0
T330	0	84	0	0
T331	0	50	0	0
T332	0	42	0	0
T333	0	36	0	0
T334	31960	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2898	0	0
T13	162118	74	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	136	0	0
T134	0	140	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	49	0	0
T322	0	63	0	0
T329	0	81	0	0
T330	0	116	0	0
T331	0	87	0	0
T332	0	41	0	0
T333	0	61	0	0
T334	31960	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2618	0	0
T13	162118	25	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	147	0	0
T134	0	130	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	63	0	0
T322	0	37	0	0
T329	0	45	0	0
T330	0	122	0	0
T331	0	56	0	0
T332	0	47	0	0
T333	0	51	0	0
T334	31960	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	489160529	2546	0	0
T13	162118	45	0	0
T14	246804	0	0	0
T45	108574	0	0	0
T47	16655	0	0	0
T50	16155	0	0	0
T94	57628	0	0	0
T133	0	133	0	0
T134	0	118	0	0
T158	16082	0	0	0
T179	15768	0	0	0
T189	31425	0	0	0
T245	0	51	0	0
T322	0	86	0	0
T329	0	20	0	0
T330	0	91	0	0
T331	0	60	0	0
T332	0	44	0	0
T333	0	37	0	0
T334	31960	0	0	0