Unified Coverage Report :: Module :: prim_ram_1p_adv

Module : prim_ram_1p_adv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_otp.gen_generic.u_impl_generic.u_prim_ram_1p_adv

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.53	98.59				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.45	97.27	100.00		100.00	100.00	100.00	gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_mem	98.85	96.55				100.00	100.00
u_req_d_buf	100.00	100.00
u_write_d_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
TOTAL		38	38	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
ALWAYS	126	3	3	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	136	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	248	0	0
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	255	1	1	100.00
ALWAYS	288	5	5	100.00
ALWAYS	299	7	7	100.00
ALWAYS	334	3	3	100.00
ALWAYS	343	5	5	100.00
CONT_ASSIGN	359	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
102	1	1
103	1	1
123	1	1
126	1	1
127	1	1
129	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
147	1	1
156	1	1
248		unreachable
249	1	1
251	1	1
255	1	1
288	1	1
289	1	1
290	1	1
292	1	1
293	1	1
299	1	1
300	1	1
301	1	1
302	1	1
304	1	1
305	1	1
306	1	1
334	1	1
335	1	1
337	1	1
343	1	1
344	1	1
345	1	1
347	1	1
349	1	1
359	1	1

---

Branch Coverage for Module : prim_ram_1p_adv

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	126	2	2	100.00
IF	299	2	2	100.00
IF	288	2	2	100.00
IF	343	2	2	100.00
IF	334	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	126	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	288	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	343	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_ram_1p_adv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CannotHaveEccAndParity_A	1151	1151	0	0

CannotHaveEccAndParity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1151	1151	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0