Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26400983

1

T1

1921

T2

5114

T3

919

full_word

8564631

1

T1

525

T2

4653

T3

592

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34965284	1			T1	2446		T2	9767		T3	1511
auto[TlIntgErrCmd]	99	1			T264	5		T265	2		T266	2
auto[TlIntgErrData]	105	1			T264	5		T265	3		T266	4
auto[TlIntgErrBoth]	126	1			T264	10		T265	5		T266	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9501870

1

T1

2253

T2

8305

T3

1335

auto[1]

25463744

1

T1

193

T2

1462

T3

176

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5945885	1			T1	1807		T2	4304		T3	823
auto[TlIntgErrNone]	partial	auto[1]	20454797	1			T1	114		T2	810		T3	96
auto[TlIntgErrNone]	full_word	auto[0]	3555833	1			T1	446		T2	4001		T3	512
auto[TlIntgErrNone]	full_word	auto[1]	5008769	1			T1	79		T2	652		T3	80
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T265	1		T266	1		T372	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T264	4		T265	1		T266	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T374	1		T272	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T264	1		T273	1		T376	1
auto[TlIntgErrData]	partial	auto[0]	57	1			T264	3		T265	1		T266	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T264	2		T265	2		T372	1
auto[TlIntgErrData]	full_word	auto[0]	5	1			T374	2		T378	3		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T377	1		T379	1		T378	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T264	4		T265	1		T266	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T264	6		T265	4		T266	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T370	2		T268	2		T376	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T376	1		T377	1		T272	2