Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26392364

1

T1

709

T2

1384

T3

3010

full_word

8487824

1

T1

107

T2

252

T3

2676

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34879878	1			T1	816		T2	1636		T3	5686
auto[TlIntgErrCmd]	100	1			T257	8		T258	7		T259	2
auto[TlIntgErrData]	104	1			T257	7		T258	8		T259	4
auto[TlIntgErrBoth]	106	1			T257	5		T258	5		T259	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9507292

1

T1

772

T2

1323

T3

5133

auto[1]

25372896

1

T1

44

T2

313

T3

553

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6006439	1			T1	680		T2	1187		T3	2688
auto[TlIntgErrNone]	partial	auto[1]	20385646	1			T1	29		T2	197		T3	322
auto[TlIntgErrNone]	full_word	auto[0]	3500722	1			T1	92		T2	136		T3	2445
auto[TlIntgErrNone]	full_word	auto[1]	4987071	1			T1	15		T2	116		T3	231
auto[TlIntgErrCmd]	partial	auto[0]	33	1			T257	3		T258	1		T265	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1			T257	4		T258	5		T259	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T257	1		T333	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T258	1		T266	1		T335	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T257	1		T258	3		T259	1
auto[TlIntgErrData]	partial	auto[1]	42	1			T257	6		T258	3		T259	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T258	1		T335	2		T334	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T258	1		T259	1		T334	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T257	2		T258	2		T265	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T257	2		T258	3		T259	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T336	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T257	1		T259	1		T266	1