Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26642558

1

T1

640

T2

1938

T3

6182

full_word

8694098

1

T1

234

T2

1716

T3

1452

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35336316	1			T1	874		T2	3654		T3	7634
auto[TlIntgErrCmd]	120	1			T232	4		T233	8		T234	7
auto[TlIntgErrData]	103	1			T232	4		T233	4		T234	5
auto[TlIntgErrBoth]	117	1			T232	2		T233	8		T234	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9833244

1

T1

580

T2

3056

T3

6833

auto[1]

25503412

1

T1

294

T2

598

T3

801

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6161659	1			T1	465		T2	1622		T3	5706
auto[TlIntgErrNone]	partial	auto[1]	20480589	1			T1	175		T2	316		T3	476
auto[TlIntgErrNone]	full_word	auto[0]	3671422	1			T1	115		T2	1434		T3	1127
auto[TlIntgErrNone]	full_word	auto[1]	5022646	1			T1	119		T2	282		T3	325
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T232	1		T233	1		T234	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T232	2		T233	5		T234	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T232	1		T233	1		T234	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T233	1		T318	1		T319	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T232	2		T233	3		T234	3
auto[TlIntgErrData]	partial	auto[1]	49	1			T232	1		T233	1		T239	7
auto[TlIntgErrData]	full_word	auto[0]	9	1			T232	1		T234	2		T318	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T233	7		T234	3		T239	3
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T232	2		T233	1		T234	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T234	2		T320	1		T321	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T321	1		T322	1		T318	1