Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.16		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	488407071	8691972	0	0
check_regwen_rd_A	488407071	3588	0	0
check_timeout_rd_A	488407071	3400	0	0
check_trigger_regwen_rd_A	488407071	3543	0	0
consistency_check_period_rd_A	488407071	3796	0	0
creator_sw_cfg_read_lock_rd_A	488407071	3495	0	0
direct_access_address_rd_A	488407071	2542	0	0
direct_access_wdata_0_rd_A	488407071	1501	0	0
direct_access_wdata_1_rd_A	488407071	1749	0	0
integrity_check_period_rd_A	488407071	3715	0	0
intr_enable_rd_A	488407071	4416	0	0
owner_sw_cfg_read_lock_rd_A	488407071	3273	0	0
rot_creator_auth_codesign_read_lock_rd_A	488407071	3456	0	0
rot_creator_auth_state_read_lock_rd_A	488407071	3315	0	0
vendor_test_read_lock_rd_A	488407071	3513	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	8691972	0	0
T9	740502	139355	0	0
T14	0	180060	0	0
T15	0	139333	0	0
T16	457596	0	0	0
T17	0	29867	0	0
T18	0	69398	0	0
T50	58704	0	0	0
T59	95816	0	0	0
T65	581278	0	0	0
T66	9176	0	0	0
T72	0	176734	0	0
T96	79505	0	0	0
T97	153294	0	0	0
T116	81727	0	0	0
T189	11302	0	0	0
T196	0	134754	0	0
T224	0	33099	0	0
T240	0	111096	0	0
T241	0	58220	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3588	0	0
T14	112758	239	0	0
T15	927616	0	0	0
T17	0	32	0	0
T18	0	86	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	87	0	0
T132	13872	0	0	0
T196	0	120	0	0
T206	49687	0	0	0
T218	0	49	0	0
T284	0	61	0	0
T298	0	54	0	0
T304	0	49	0	0
T305	0	37	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3400	0	0
T14	112758	200	0	0
T15	927616	0	0	0
T17	0	70	0	0
T18	0	110	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	143	0	0
T132	13872	0	0	0
T196	0	191	0	0
T206	49687	0	0	0
T218	0	49	0	0
T284	0	83	0	0
T298	0	26	0	0
T304	0	79	0	0
T305	0	29	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3543	0	0
T14	112758	183	0	0
T15	927616	0	0	0
T17	0	44	0	0
T18	0	81	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	136	0	0
T132	13872	0	0	0
T196	0	170	0	0
T206	49687	0	0	0
T218	0	13	0	0
T284	0	79	0	0
T298	0	19	0	0
T304	0	60	0	0
T305	0	20	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3796	0	0
T14	112758	217	0	0
T15	927616	0	0	0
T17	0	26	0	0
T18	0	148	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	124	0	0
T132	13872	0	0	0
T196	0	155	0	0
T206	49687	0	0	0
T218	0	41	0	0
T284	0	126	0	0
T298	0	57	0	0
T304	0	27	0	0
T305	0	40	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3495	0	0
T14	112758	272	0	0
T15	927616	0	0	0
T17	0	32	0	0
T18	0	95	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	170	0	0
T132	13872	0	0	0
T196	0	152	0	0
T206	49687	0	0	0
T218	0	34	0	0
T284	0	106	0	0
T298	0	35	0	0
T304	0	49	0	0
T305	0	28	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	2542	0	0
T14	112758	221	0	0
T15	927616	0	0	0
T17	0	65	0	0
T18	0	132	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	149	0	0
T132	13872	0	0	0
T196	0	230	0	0
T206	49687	0	0	0
T218	0	42	0	0
T284	0	92	0	0
T298	0	40	0	0
T304	0	56	0	0
T305	0	33	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	1501	0	0
T14	112758	160	0	0
T15	927616	0	0	0
T17	0	3	0	0
T18	0	88	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	65	0	0
T132	13872	0	0	0
T196	0	127	0	0
T206	49687	0	0	0
T218	0	8	0	0
T284	0	58	0	0
T298	0	24	0	0
T304	0	49	0	0
T305	0	7	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	1749	0	0
T14	112758	168	0	0
T15	927616	0	0	0
T17	0	23	0	0
T18	0	68	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	118	0	0
T132	13872	0	0	0
T196	0	136	0	0
T206	49687	0	0	0
T218	0	9	0	0
T284	0	81	0	0
T298	0	50	0	0
T304	0	39	0	0
T305	0	21	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3715	0	0
T14	112758	205	0	0
T15	927616	0	0	0
T17	0	39	0	0
T18	0	104	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	132	0	0
T132	13872	0	0	0
T196	0	164	0	0
T206	49687	0	0	0
T218	0	34	0	0
T284	0	56	0	0
T298	0	49	0	0
T304	0	45	0	0
T305	0	50	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	4416	0	0
T14	112758	187	0	0
T15	927616	0	0	0
T17	0	80	0	0
T18	0	98	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	141	0	0
T132	13872	0	0	0
T186	0	22	0	0
T196	0	227	0	0
T206	49687	0	0	0
T218	0	47	0	0
T298	0	47	0	0
T304	0	87	0	0
T305	0	36	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3273	0	0
T14	112758	192	0	0
T15	927616	0	0	0
T17	0	54	0	0
T18	0	86	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	174	0	0
T132	13872	0	0	0
T196	0	141	0	0
T206	49687	0	0	0
T218	0	31	0	0
T284	0	71	0	0
T298	0	21	0	0
T304	0	57	0	0
T305	0	36	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3456	0	0
T14	112758	229	0	0
T15	927616	0	0	0
T17	0	63	0	0
T18	0	65	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	203	0	0
T132	13872	0	0	0
T196	0	174	0	0
T206	49687	0	0	0
T218	0	41	0	0
T284	0	90	0	0
T298	0	62	0	0
T304	0	77	0	0
T305	0	36	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3315	0	0
T14	112758	144	0	0
T15	927616	0	0	0
T17	0	46	0	0
T18	0	111	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	132	0	0
T132	13872	0	0	0
T196	0	224	0	0
T206	49687	0	0	0
T218	0	36	0	0
T284	0	90	0	0
T298	0	31	0	0
T304	0	56	0	0
T305	0	33	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	488407071	3513	0	0
T14	112758	190	0	0
T15	927616	0	0	0
T17	0	39	0	0
T18	0	96	0	0
T33	147097	0	0	0
T67	11722	0	0	0
T73	14059	0	0	0
T91	88304	0	0	0
T92	44379	0	0	0
T99	23360	0	0	0
T123	0	153	0	0
T132	13872	0	0	0
T196	0	206	0	0
T206	49687	0	0	0
T218	0	40	0	0
T284	0	87	0	0
T298	0	32	0	0
T304	0	54	0	0
T305	0	48	0	0