Unified Coverage Report :: Module :: otp_ctrl_ecc_reg

Module : otp_ctrl_ecc_reg

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg	93.33	100.00				80.00	100.00
tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00
tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.23	100.00	100.00		90.00	100.00	96.15	gen_partitions[0].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[1].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.75	100.00	97.06		91.67	100.00	100.00	gen_partitions[2].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[3].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.33	100.00				80.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00		100.00		80.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.33	100.00	100.00		91.67	100.00	100.00	gen_partitions[4].gen_unbuffered.u_part_unbuf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.82	97.64	95.24		92.00	96.36	82.86	gen_partitions[5].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.75	95.45	92.86		91.67	90.91	82.86	gen_partitions[6].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[7].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.24	97.33	91.67		88.89	93.85	94.44	gen_partitions[8].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00		100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.65	98.00	93.75		91.67	95.38	94.44	gen_partitions[9].gen_buffered.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	100.00			100.00
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	100.00			100.00
u_prim_secded_inv_72_64_enc	100.00			100.00

---

Module Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.16	100.00		76.65		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	96.91	100.00		90.48	100.00	82.35	gen_partitions[10].gen_lifecycle.u_part_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ecc_dec[0].u_prim_secded_inv_72_64_dec	83.82			83.82
gen_ecc_dec[10].u_prim_secded_inv_72_64_dec	77.94			77.94
gen_ecc_dec[1].u_prim_secded_inv_72_64_dec	86.76			86.76
gen_ecc_dec[2].u_prim_secded_inv_72_64_dec	69.12			69.12
gen_ecc_dec[3].u_prim_secded_inv_72_64_dec	68.38			68.38
gen_ecc_dec[4].u_prim_secded_inv_72_64_dec	76.47			76.47
gen_ecc_dec[5].u_prim_secded_inv_72_64_dec	86.76			86.76
gen_ecc_dec[6].u_prim_secded_inv_72_64_dec	68.38			68.38
gen_ecc_dec[7].u_prim_secded_inv_72_64_dec	69.12			69.12
gen_ecc_dec[8].u_prim_secded_inv_72_64_dec	63.24			63.24
gen_ecc_dec[9].u_prim_secded_inv_72_64_dec	69.85			69.85
u_prim_secded_inv_72_64_enc	100.00			100.00

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=9,Aw=4,EccWidth=8 + Width=64,Depth=2,Aw=1,EccWidth=8 + Width=64,Depth=5,Aw=3,EccWidth=8 + Width=64,Depth=11,Aw=4,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

SCORE	LINE
100.00	100.00

tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Line Coverage for Module : otp_ctrl_ecc_reg ( parameter Width=64,Depth=1,Aw=1,EccWidth=8 )
Line Coverage for Module self-instances :

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

SCORE	LINE
93.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Module : otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T23

---

Assert Coverage for Module : otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	2147483647	0	0
DataOutKnown_A	2147483647	2147483647	0	0
EccErrKnown_A	2147483647	2147483647	0	0
EccKnown_A	2147483647	2147483647	0	0
RDataOutKnown_A	2147483647	2147483647	0	0
WidthMustBe64bit_A	12727	12727	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	172920	169664	0	0
T2	356202	353320	0	0
T3	847627	833734	0	0
T4	125466	122375	0	0
T5	51469	50897	0	0
T6	722073	712492	0	0
T10	110440	107107	0	0
T11	66440	65824	0	0
T12	120054	117799	0	0
T13	108152	105292	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	172920	169664	0	0
T2	356202	353320	0	0
T3	847627	833734	0	0
T4	125466	122375	0	0
T5	51469	50897	0	0
T6	722073	712492	0	0
T10	110440	107107	0	0
T11	66440	65824	0	0
T12	120054	117799	0	0
T13	108152	105292	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	172920	169664	0	0
T2	356202	353320	0	0
T3	847627	833734	0	0
T4	125466	122375	0	0
T5	51469	50897	0	0
T6	722073	712492	0	0
T10	110440	107107	0	0
T11	66440	65824	0	0
T12	120054	117799	0	0
T13	108152	105292	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	172920	169664	0	0
T2	356202	353320	0	0
T3	847627	833734	0	0
T4	125466	122375	0	0
T5	51469	50897	0	0
T6	722073	712492	0	0
T10	110440	107107	0	0
T11	66440	65824	0	0
T12	120054	117799	0	0
T13	108152	105292	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	172920	169664	0	0
T2	356202	353320	0	0
T3	847627	833734	0	0
T4	125466	122375	0	0
T5	51469	50897	0	0
T6	722073	712492	0	0
T10	110440	107107	0	0
T11	66440	65824	0	0
T12	120054	117799	0	0
T13	108152	105292	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12727	12727	0	0
T1	11	11	0	0
T2	11	11	0	0
T3	11	11	0	0
T4	11	11	0	0
T5	11	11	0	0
T6	11	11	0	0
T10	11	11	0	0
T11	11	11	0	0
T12	11	11	0	0
T13	11	11	0	0

Line Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	46	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
46	1	1
47	1	1
48	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	4	80.00
IF	90	2	2	100.00
IF	65	3	2	66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Not Covered

---

Assert Coverage for Instance : tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf.gen_ecc_reg.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T23

---

Assert Coverage for Instance : tb.dut.gen_partitions[5].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			==> MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	90	2	2	100.00
IF	65	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Excluded		VC_COV_UNR

---

Assert Coverage for Instance : tb.dut.gen_partitions[6].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T23

---

Assert Coverage for Instance : tb.dut.gen_partitions[7].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T23

---

Assert Coverage for Instance : tb.dut.gen_partitions[8].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T23

---

Assert Coverage for Instance : tb.dut.gen_partitions[9].gen_buffered.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	60	8	8	100.00
CONT_ASSIGN	87	1	1	100.00
ALWAYS	90	5	5	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
61	1	1
62	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
			MISSING_ELSE
			MISSING_ELSE
87	1	1
90	1	1
91	1	1
92	1	1
94	1	1
95	1	1

---

Branch Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	90	2	2	100.00
IF	65	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_ecc_reg.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	90	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	65	if ((32'(addr_i) < Depth))
-2-:	67	if (wren_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
0	-	Covered	T23

---

Assert Coverage for Instance : tb.dut.gen_partitions[10].gen_lifecycle.u_part_buf.u_otp_ctrl_ecc_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	485267964	484436711	0	0
DataOutKnown_A	485267964	484436711	0	0
EccErrKnown_A	485267964	484436711	0	0
EccKnown_A	485267964	484436711	0	0
RDataOutKnown_A	485267964	484436711	0	0
WidthMustBe64bit_A	1157	1157	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

DataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

EccKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

RDataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485267964	484436711	0	0
T1	15720	15424	0	0
T2	32382	32120	0	0
T3	77057	75794	0	0
T4	11406	11125	0	0
T5	4679	4627	0	0
T6	65643	64772	0	0
T10	10040	9737	0	0
T11	6040	5984	0	0
T12	10914	10709	0	0
T13	9832	9572	0	0

WidthMustBe64bit_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1157	1157	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0