Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23528523

1

T1

10171

T2

400989

T3

567

full_word

7769364

1

T1

7389

T2

112858

T3

226

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31297577	1			T1	17560		T2	513847		T3	793
auto[TlIntgErrCmd]	91	1			T256	2		T257	4		T258	7
auto[TlIntgErrData]	112	1			T256	9		T257	3		T258	7
auto[TlIntgErrBoth]	107	1			T256	9		T257	13		T258	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9273195

1

T1

14994

T2

91208

T3

714

auto[1]

22024692

1

T1

2566

T2

422639

T3

79

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5851067	1			T1	8753		T2	56022		T3	518
auto[TlIntgErrNone]	partial	auto[1]	17677163	1			T1	1418		T2	344967		T3	49
auto[TlIntgErrNone]	full_word	auto[0]	3421979	1			T1	6241		T2	35186		T3	196
auto[TlIntgErrNone]	full_word	auto[1]	4347368	1			T1	1148		T2	77672		T3	30
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T256	2		T257	2		T348	1
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T257	2		T258	7		T348	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T352	1		T353	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T348	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T256	4		T257	1		T258	4
auto[TlIntgErrData]	partial	auto[1]	55	1			T256	5		T257	2		T258	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T351	1		T352	1		T353	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T264	1		T351	1		T354	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T256	3		T257	8		T258	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T256	6		T257	5		T258	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T355	1		T352	1		T263	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T264	2		T356	1		T263	1