Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.18	94.16	96.15	97.00		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	439258479	7430962	0	0
check_regwen_rd_A	439258479	2255	0	0
check_timeout_rd_A	439258479	1421	0	0
check_trigger_regwen_rd_A	439258479	2410	0	0
consistency_check_period_rd_A	439258479	2541	0	0
creator_sw_cfg_read_lock_rd_A	439258479	1309	0	0
direct_access_address_rd_A	439258479	1352	0	0
direct_access_wdata_0_rd_A	439258479	770	0	0
direct_access_wdata_1_rd_A	439258479	841	0	0
integrity_check_period_rd_A	439258479	2320	0	0
intr_enable_rd_A	439258479	3073	0	0
owner_sw_cfg_read_lock_rd_A	439258479	1261	0	0
rot_creator_auth_codesign_read_lock_rd_A	439258479	1343	0	0
rot_creator_auth_state_read_lock_rd_A	439258479	1137	0	0
vendor_test_read_lock_rd_A	439258479	1297	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	7430962	0	0
T2	591032	147598	0	0
T3	10119	0	0	0
T4	208103	63560	0	0
T5	40605	0	0	0
T6	58847	0	0	0
T7	9847	0	0	0
T8	48110	0	0	0
T9	13328	0	0	0
T10	20096	0	0	0
T11	0	162554	0	0
T14	215520	0	0	0
T15	0	102767	0	0
T16	0	228163	0	0
T31	0	105296	0	0
T132	0	206572	0	0
T133	0	186534	0	0
T223	0	40047	0	0
T248	0	38254	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	2255	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	46	0	0
T248	257359	60	0	0
T249	0	78	0	0
T250	0	23	0	0
T271	0	78	0	0
T321	0	99	0	0
T323	0	31	0	0
T326	0	105	0	0
T327	0	41	0	0
T328	0	33	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1421	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	82	0	0
T248	257359	63	0	0
T249	0	48	0	0
T250	0	9	0	0
T271	0	37	0	0
T321	0	110	0	0
T323	0	57	0	0
T326	0	62	0	0
T327	0	34	0	0
T328	0	52	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	2410	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	35	0	0
T248	257359	38	0	0
T249	0	61	0	0
T250	0	13	0	0
T271	0	45	0	0
T321	0	56	0	0
T323	0	41	0	0
T326	0	121	0	0
T327	0	63	0	0
T328	0	32	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	2541	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	28	0	0
T248	257359	66	0	0
T249	0	79	0	0
T250	0	33	0	0
T271	0	79	0	0
T321	0	77	0	0
T323	0	29	0	0
T326	0	120	0	0
T327	0	49	0	0
T328	0	83	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1309	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	47	0	0
T248	257359	35	0	0
T249	0	96	0	0
T250	0	18	0	0
T271	0	44	0	0
T321	0	110	0	0
T323	0	46	0	0
T326	0	69	0	0
T327	0	28	0	0
T328	0	82	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1352	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	50	0	0
T248	257359	48	0	0
T249	0	101	0	0
T250	0	62	0	0
T271	0	77	0	0
T321	0	106	0	0
T323	0	57	0	0
T326	0	77	0	0
T327	0	40	0	0
T328	0	89	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	770	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	41	0	0
T248	257359	24	0	0
T249	0	52	0	0
T250	0	13	0	0
T271	0	37	0	0
T321	0	73	0	0
T323	0	18	0	0
T326	0	58	0	0
T327	0	48	0	0
T328	0	26	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	841	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	34	0	0
T248	257359	30	0	0
T249	0	30	0	0
T250	0	27	0	0
T271	0	40	0	0
T321	0	97	0	0
T323	0	36	0	0
T326	0	62	0	0
T327	0	13	0	0
T328	0	60	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	2320	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	54	0	0
T248	257359	76	0	0
T249	0	75	0	0
T250	0	27	0	0
T271	0	48	0	0
T321	0	38	0	0
T323	0	24	0	0
T326	0	67	0	0
T327	0	47	0	0
T328	0	49	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	3073	0	0
T40	16894	0	0	0
T55	222238	0	0	0
T56	778234	0	0	0
T62	11271	0	0	0
T90	735474	7	0	0
T91	344467	0	0	0
T93	0	13	0	0
T163	12478	0	0	0
T165	52266	0	0	0
T196	0	17	0	0
T198	0	35	0	0
T202	10879	0	0	0
T248	0	70	0	0
T249	0	52	0	0
T250	0	22	0	0
T323	0	44	0	0
T334	0	20	0	0
T335	0	18	0	0
T336	54564	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1261	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	43	0	0
T248	257359	28	0	0
T249	0	90	0	0
T250	0	36	0	0
T271	0	32	0	0
T321	0	114	0	0
T323	0	42	0	0
T326	0	63	0	0
T327	0	35	0	0
T328	0	55	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1343	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	63	0	0
T248	257359	80	0	0
T249	0	69	0	0
T250	0	52	0	0
T271	0	47	0	0
T321	0	60	0	0
T323	0	32	0	0
T326	0	96	0	0
T327	0	33	0	0
T328	0	69	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1137	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	26	0	0
T248	257359	26	0	0
T249	0	79	0	0
T250	0	33	0	0
T271	0	36	0	0
T321	0	71	0	0
T323	0	16	0	0
T326	0	43	0	0
T327	0	50	0	0
T328	0	33	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	439258479	1297	0	0
T117	12607	0	0	0
T211	12626	0	0	0
T212	9198	0	0	0
T219	12987	0	0	0
T237	0	64	0	0
T248	257359	50	0	0
T249	0	78	0	0
T250	0	42	0	0
T271	0	57	0	0
T321	0	72	0	0
T323	0	58	0	0
T326	0	49	0	0
T327	0	68	0	0
T328	0	65	0	0
T329	30555	0	0	0
T330	134583	0	0	0
T331	17317	0	0	0
T332	28267	0	0	0
T333	85056	0	0	0