Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.13	94.16	96.15	96.71		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	463333632	7812010	0	0
check_regwen_rd_A	463333632	3078	0	0
check_timeout_rd_A	463333632	2332	0	0
check_trigger_regwen_rd_A	463333632	3264	0	0
consistency_check_period_rd_A	463333632	3490	0	0
creator_sw_cfg_read_lock_rd_A	463333632	2043	0	0
direct_access_address_rd_A	463333632	1818	0	0
direct_access_wdata_0_rd_A	463333632	1291	0	0
direct_access_wdata_1_rd_A	463333632	1437	0	0
integrity_check_period_rd_A	463333632	3325	0	0
intr_enable_rd_A	463333632	4276	0	0
owner_sw_cfg_read_lock_rd_A	463333632	2105	0	0
rot_creator_auth_codesign_read_lock_rd_A	463333632	2265	0	0
rot_creator_auth_state_read_lock_rd_A	463333632	1943	0	0
vendor_test_read_lock_rd_A	463333632	2228	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	7812010	0	0
T2	935256	210538	0	0
T3	15086	0	0	0
T4	99939	0	0	0
T5	440148	81593	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T12	0	139911	0	0
T13	0	109244	0	0
T14	0	40059	0	0
T31	13575	0	0	0
T120	0	155777	0	0
T145	0	32206	0	0
T206	0	68217	0	0
T283	0	108990	0	0
T284	0	99807	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	3078	0	0
T5	440148	81	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	49	0	0
T206	0	37	0	0
T228	0	38	0	0
T253	0	4	0	0
T284	0	74	0	0
T287	0	64	0	0
T288	0	56	0	0
T342	0	59	0	0
T343	0	84	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	2332	0	0
T5	440148	125	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	79	0	0
T206	0	101	0	0
T228	0	55	0	0
T253	0	29	0	0
T284	0	62	0	0
T287	0	133	0	0
T288	0	92	0	0
T342	0	47	0	0
T343	0	91	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	3264	0	0
T5	440148	115	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	45	0	0
T206	0	43	0	0
T228	0	56	0	0
T253	0	21	0	0
T284	0	87	0	0
T287	0	95	0	0
T288	0	76	0	0
T342	0	105	0	0
T343	0	90	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	3490	0	0
T5	440148	99	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	33	0	0
T206	0	32	0	0
T228	0	77	0	0
T253	0	18	0	0
T284	0	84	0	0
T287	0	74	0	0
T288	0	76	0	0
T342	0	138	0	0
T343	0	103	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	2043	0	0
T5	440148	89	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	19	0	0
T206	0	48	0	0
T228	0	68	0	0
T253	0	22	0	0
T284	0	102	0	0
T287	0	102	0	0
T288	0	50	0	0
T342	0	84	0	0
T343	0	98	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	1818	0	0
T5	440148	126	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	62	0	0
T206	0	32	0	0
T228	0	60	0	0
T253	0	22	0	0
T284	0	37	0	0
T287	0	73	0	0
T288	0	61	0	0
T342	0	122	0	0
T343	0	87	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	1291	0	0
T5	440148	69	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	34	0	0
T206	0	19	0	0
T228	0	68	0	0
T253	0	27	0	0
T284	0	72	0	0
T287	0	43	0	0
T288	0	20	0	0
T342	0	76	0	0
T343	0	30	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	1437	0	0
T5	440148	87	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	43	0	0
T206	0	47	0	0
T228	0	86	0	0
T253	0	34	0	0
T284	0	89	0	0
T287	0	37	0	0
T288	0	64	0	0
T342	0	38	0	0
T343	0	25	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	3325	0	0
T5	440148	108	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	41	0	0
T206	0	44	0	0
T228	0	65	0	0
T253	0	15	0	0
T284	0	80	0	0
T287	0	114	0	0
T288	0	47	0	0
T342	0	90	0	0
T343	0	90	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	4276	0	0
T5	440148	142	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	44	0	0
T206	0	105	0	0
T212	0	19	0	0
T228	0	51	0	0
T241	0	11	0	0
T253	0	67	0	0
T284	0	90	0	0
T287	0	98	0	0
T344	0	61	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	2105	0	0
T5	440148	142	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	59	0	0
T206	0	51	0	0
T228	0	58	0	0
T253	0	26	0	0
T284	0	49	0	0
T287	0	100	0	0
T288	0	53	0	0
T342	0	74	0	0
T343	0	118	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	2265	0	0
T5	440148	147	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	45	0	0
T206	0	48	0	0
T228	0	71	0	0
T253	0	32	0	0
T284	0	105	0	0
T287	0	114	0	0
T288	0	65	0	0
T342	0	72	0	0
T343	0	107	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	1943	0	0
T5	440148	127	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	42	0	0
T206	0	33	0	0
T228	0	92	0	0
T253	0	7	0	0
T284	0	66	0	0
T287	0	100	0	0
T288	0	46	0	0
T342	0	72	0	0
T343	0	65	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463333632	2228	0	0
T5	440148	161	0	0
T6	120871	0	0	0
T7	62862	0	0	0
T8	13768	0	0	0
T9	82484	0	0	0
T10	20012	0	0	0
T11	9427	0	0	0
T24	110506	0	0	0
T31	13575	0	0	0
T84	9935	0	0	0
T145	0	52	0	0
T206	0	54	0	0
T228	0	58	0	0
T253	0	12	0	0
T284	0	90	0	0
T287	0	67	0	0
T288	0	61	0	0
T342	0	44	0	0
T343	0	85	0	0