Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25641825

1

T1

760

T2

411

T3

7545

full_word

8423789

1

T1

374

T2

215

T3

1311

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34065344	1			T1	1134		T2	626		T3	8856
auto[TlIntgErrCmd]	89	1			T253	4		T254	5		T255	5
auto[TlIntgErrData]	90	1			T253	1		T254	7		T255	8
auto[TlIntgErrBoth]	91	1			T253	5		T254	8		T255	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9525254

1

T1

1004

T2

539

T3

8410

auto[1]

24540360

1

T1

130

T2

87

T3

446

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5951339	1			T1	687		T2	367		T3	7279
auto[TlIntgErrNone]	partial	auto[1]	19690240	1			T1	73		T2	44		T3	266
auto[TlIntgErrNone]	full_word	auto[0]	3573777	1			T1	317		T2	172		T3	1131
auto[TlIntgErrNone]	full_word	auto[1]	4849988	1			T1	57		T2	43		T3	180
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T253	3		T254	3		T255	3
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T253	1		T254	2		T255	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T355	1		T356	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T260	1		T354	2		T357	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T254	3		T255	3		T355	2
auto[TlIntgErrData]	partial	auto[1]	36	1			T253	1		T254	4		T255	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T255	1		T354	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T255	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T253	4		T254	5		T255	3
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T253	1		T254	3		T255	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T355	1		T359	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T255	1		T360	1		T354	1