Unified Coverage Report :: Module :: otp_ctrl_part_unbuf

Module : otp_ctrl_part_unbuf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.82	98.49	96.36		64.71	94.57	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf	96.23	100.00	100.00		85.00	100.00	96.15
tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf	97.75	100.00	97.06		91.67	100.00	100.00
tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00
tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf	98.33	100.00	100.00		91.67	100.00	100.00

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
96.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		93	86	92.47
CONT_ASSIGN	138	1	1	100.00
ALWAYS	153	3	3	100.00
ALWAYS	164	68	61	89.71
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
153	1	1
154	1	1
156	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			==> MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	0	1
			MISSING_ELSE
224	0	1
225	0	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	0	1
			MISSING_ELSE
276	0	1
277	0	1
279	0	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
339	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134594644,DigestOffset=424,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=906698836,DigestOffset=1136,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
97.75	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Line Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Line Coverage for Module self-instances :

SCORE	LINE
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
TOTAL		91	91	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	164	68	68	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	395	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
ALWAYS	461	3	3	100.00
ALWAYS	464	8	8	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	1	1
149	1	1
164	1	1
167	1	1
170	1	1
171	1	1
174	1	1
175	1	1
176	1	1
179	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
193	1	1
194	1	1
196		unreachable
			MISSING_ELSE
205	1	1
206	1	1
207	1	1
			MISSING_ELSE
215	1	1
216	1	1
217	1	1
218	1	1
220	1	1
221	1	1
			MISSING_ELSE
224	1	1
225	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
			MISSING_ELSE
246	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
			MISSING_ELSE
255	1	1
256	1	1
257	1	1
258	1	1
266	1	1
267	1	1
268	1	1
269	1	1
270	1	1
272	1	1
273	1	1
			MISSING_ELSE
276	1	1
277	1	1
279	1	1
			MISSING_ELSE
288	1	1
289	1	1
			MISSING_ELSE
293	1	1
294	1	1
295	1	1
296	1	1
297	1	1
298	1	1
			MISSING_ELSE
314	1	1
315	1	1
316	1	1
317	1	1
			MISSING_ELSE
			MISSING_ELSE
321	1	1
322	1	1
323	1	1
324	1	1
325	1	1
			MISSING_ELSE
			MISSING_ELSE
334	1	1
336	1	1
342	1	1
349	1	1
350	1	1
354	1	1
358	1	1
395	1	1
420	1	1
454	1	1
461	3	3
464	1	1
465	1	1
466	1	1
467	1	1
469	1	1
470	1	1
471	1	1
472	1	1
			MISSING_ELSE

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1608,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T59,T69,T109

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T33,T40,T61

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T127,T128
1	Covered	T74,T127,T128

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T7,T11,T12

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b10001111000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
96.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	31	29	93.55
Logical	31	29	93.55
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Not Covered

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T75,T127
1	Covered	T74,T75,T127

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T6,T7,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134594644,DigestOffset=424,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T59,T69

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T37,T129,T61

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T128,T130
1	Covered	T128,T130

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T6,T7,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00001000000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=906698836,DigestOffset=1136,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
97.75	97.06

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T13

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T33,T40,T61

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T127,T131,T132
1	Covered	T127,T131,T132

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T6,T7,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T11,T8
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b00110110000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T37,T20

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T37,T20

---

Cond Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=-1,DigestOffset=1648,StateWidth=10 )
Cond Coverage for Module self-instances :

SCORE	COND
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Total	Covered	Percent
Conditions	34	33	97.06
Logical	34	33	97.06
Non-Logical	0	0
Event	0	0

 LINE       220
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T68,T59

 LINE       272
 EXPRESSION (otp_err != NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T37,T33,T129

 LINE       288
 EXPRESSION (error_q == NoError)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T26,T27,T28

 LINE       316
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T74,T75,T127
1	Covered	T74,T75,T127

 LINE       324
 EXPRESSION (state_q != ErrorSt)
            ----------1---------

-1-	Status	Tests
0	Covered	T6,T7,T11
1	Covered	T6,T7,T11

 LINE       336
 EXPRESSION ((tlul_rvalid_o && (tlul_rerror_o == '0)) ? otp_rdata_i[31:0] : '0)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rvalid_o && (tlul_rerror_o == '0))
                 ------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T1,T3,T6

 LINE       336
 SUB-EXPRESSION (tlul_rerror_o == '0)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       342
 EXPRESSION (({tlul_addr_q, 2'b0} >= 11'b11001010000) && ({1'b0, tlul_addr_q, 2'b0} < PartEnd))
             --------------------1-------------------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T5

 LINE       349
 EXPRESSION ((otp_addr_sel == DigestAddrSel) ? DigestOffset : ({tlul_addr_q, 2'b0}))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       349
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (otp_addr_sel == DigestAddrSel) ? (2'((unsigned'(((otp_ctrl_pkg::ScrmblBlockWidth / otp_ctrl_pkg::OtpWidth) - 1))))) : (2'((unsigned'(((32 / otp_ctrl_pkg::OtpWidth) - 1))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       358
 SUB-EXPRESSION (otp_addr_sel == DigestAddrSel)
                ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       395
 EXPRESSION (((~init_done_o)) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       420
 EXPRESSION ((digest_o != '0) ? MuBi8True : MuBi8False)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T32

 LINE       420
 SUB-EXPRESSION (digest_o != '0)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T5,T32

---

FSM Coverage for Module : otp_ctrl_part_unbuf

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
ErrorSt	224	Covered	T6,T7,T11
IdleSt	196	Covered	T1,T2,T3
InitSt	194	Covered	T1,T2,T3
InitWaitSt	207	Covered	T1,T2,T3
ReadSt	236	Covered	T1,T3,T5
ReadWaitSt	252	Covered	T1,T3,T6
ResetSt	190	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->ErrorSt	315	Covered	T6,T7,T11
IdleSt->ReadSt	236	Covered	T1,T3,T5
InitSt->ErrorSt	315	Covered	T112,T133,T134
InitSt->InitWaitSt	207	Covered	T1,T2,T3
InitWaitSt->ErrorSt	224	Covered	T112,T133,T134
InitWaitSt->IdleSt	218	Covered	T1,T2,T3
ReadSt->ErrorSt	315	Not Covered
ReadSt->IdleSt	255	Covered	T3,T5,T8
ReadSt->ReadWaitSt	252	Covered	T1,T3,T6
ReadWaitSt->ErrorSt	276	Covered	T129,T135,T136
ReadWaitSt->IdleSt	270	Covered	T1,T3,T6
ResetSt->ErrorSt	315	Covered	T74,T75,T76
ResetSt->IdleSt	196	Not Covered
ResetSt->InitSt	194	Covered	T1,T2,T3

Summary for FSM :: error_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	20	10	50.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: error_q

---

states	Line No.	Covered	Tests
AccessError	256	Covered	T3,T5,T8
CheckFailError	317	Covered	T74,T75,T127
FsmStateError	289	Covered	T6,T7,T11
MacroEccCorrError	221	Covered	T6,T7,T13
NoError	235	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AccessError->CheckFailError	317	Not Covered
AccessError->FsmStateError	325	Covered	T8,T9,T10
AccessError->MacroEccCorrError	221	Not Covered
AccessError->NoError	235	Covered	T3,T5,T8
CheckFailError->AccessError	256	Not Covered
CheckFailError->FsmStateError	325	Not Covered
CheckFailError->MacroEccCorrError	221	Not Covered
CheckFailError->NoError	235	Covered	T74,T75,T127
FsmStateError->AccessError	256	Not Covered
FsmStateError->CheckFailError	317	Not Covered
FsmStateError->MacroEccCorrError	221	Not Covered
FsmStateError->NoError	235	Covered	T6,T7,T11
MacroEccCorrError->AccessError	256	Not Covered
MacroEccCorrError->CheckFailError	317	Not Covered
MacroEccCorrError->FsmStateError	325	Covered	T6,T7,T13
MacroEccCorrError->NoError	235	Covered	T37,T33,T129
NoError->AccessError	256	Covered	T3,T5,T8
NoError->CheckFailError	317	Covered	T74,T75,T127
NoError->FsmStateError	289	Covered	T6,T7,T11
NoError->MacroEccCorrError	221	Covered	T6,T7,T13

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=65616,DigestOffset=56,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
96.23	100.00

tb.dut.gen_partitions[0].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		46	41	89.13
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	18	78.26
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00
IF	153	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T10,T16,T67
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Not Covered
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T11,T9,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T11,T9,T10
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T6,T7,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T75,T127
1	0	Covered	T74,T75,T127
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T7,T11
1	0	Covered	T6,T7,T11
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	153	if ((otp_err_e'(otp_err_i) inside {MacroEccCorrError, MacroEccUncorrError}))

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T13
0	Covered	T1,T2,T3

---

Branch Coverage for Module : otp_ctrl_part_unbuf ( parameter Info=134594644,DigestOffset=424,StateWidth=10 + Info=906698836,DigestOffset=1136,StateWidth=10 + Info=-1,DigestOffset=1608,StateWidth=10 + Info=-1,DigestOffset=1648,StateWidth=10 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[1].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
97.75	100.00

tb.dut.gen_partitions[2].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[3].gen_unbuffered.u_part_unbuf

SCORE	BRANCH
98.33	100.00

tb.dut.gen_partitions[4].gen_unbuffered.u_part_unbuf

	Line No.	Total	Covered	Percent
Branches		44	44	100.00
TERNARY	336	2	2	100.00
TERNARY	349	2	2	100.00
TERNARY	358	2	2	100.00
TERNARY	395	2	2	100.00
TERNARY	420	2	2	100.00
CASE	186	23	23	100.00
IF	314	3	3	100.00
IF	321	3	3	100.00
IF	461	2	2	100.00
IF	464	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv' or '../src/lowrisc_ip_otp_ctrl_1.0/rtl/otp_ctrl_part_unbuf.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	336	((tlul_rvalid_o && (tlul_rerror_o == '0))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	349	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	358	((otp_addr_sel == DigestAddrSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	395	((~init_done_o)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	420	((digest_o != '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	191	if (init_req_i)
-3-:	193	if (1'b1)
-4-:	206	if (otp_gnt_i)
-5-:	215	if (otp_rvalid_i)
-6-:	217	if ((otp_err inside {NoError, MacroEccCorrError}))
-7-:	220	if ((otp_err != NoError))
-8-:	234	if (tlul_req_i)
-9-:	248	if ((tlul_addr_in_range && prim_mubi_pkg::mubi8_test_false_strict(access_o.read_lock)))
-10-:	251	if (otp_gnt_i)
-11-:	267	if (otp_rvalid_i)
-12-:	269	if ((otp_err inside {NoError, MacroEccCorrError}))
-13-:	272	if ((otp_err != NoError))
-14-:	288	if ((error_q == NoError))
-15-:	293	if (pending_tlul_error_q)
-16-:	296	if (tlul_req_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
ResetSt	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ResetSt	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Unreachable
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitSt	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T13
InitWaitSt	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
InitWaitSt	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	Covered	T6,T112,T133
InitWaitSt	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
ReadSt	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	Covered	T1,T3,T6
ReadSt	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	Covered	T9,T10,T98
ReadSt	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T3,T5,T8
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	Covered	T37,T33,T129
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	Covered	T1,T3,T6
ReadWaitSt	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	Covered	T129,T135,T136
ReadWaitSt	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T6
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T27,T28
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	Covered	T6,T7,T11
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T11,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	Covered	T11,T9,T37
ErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	Covered	T6,T7,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28

	LineNo.	Expression
-1-:	314	if (ecc_err)
-2-:	316	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T74,T75,T127
1	0	Covered	T74,T75,T127
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(escalate_en_i))
-2-:	324	if ((state_q != ErrorSt))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6,T7,T11
1	0	Covered	T6,T7,T11
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	461	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	464	if ((!rst_ni))
-2-:	471	if (tlul_gnt_o)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : otp_ctrl_part_unbuf

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	26	26	100.00	26	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	26	26	100.00	26	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccessKnown_A	2147483647	2147483647	0	0
DigestKnown_A	2147483647	2147483647	0	0
DigestOffsetMustBeRepresentable_A	5730	5730	0	0
EccErrorState_A	2147483647	80425	0	0
ErrorKnown_A	2147483647	2147483647	0	0
FsmStateKnown_A	2147483647	2147483647	0	0
InitDoneKnown_A	2147483647	2147483647	0	0
InitReadLocksPartition_A	2147483647	500823793	0	0
InitWriteLocksPartition_A	2147483647	500823793	0	0
OffsetMustBeBlockAligned_A	5730	5730	0	0
OtpAddrKnown_A	2147483647	2147483647	0	0
OtpCmdKnown_A	2147483647	2147483647	0	0
OtpErrorState_A	2147483647	205	0	0
OtpReqKnown_A	2147483647	2147483647	0	0
OtpSizeKnown_A	2147483647	2147483647	0	0
OtpWdataKnown_A	2147483647	2147483647	0	0
ReadLockPropagation_A	2147483647	937363402	0	0
SizeMustBeBlockAligned_A	5730	5730	0	0
TlulGntKnown_A	2147483647	2147483647	0	0
TlulRdataKnown_A	2147483647	2147483647	0	0
TlulReadOnReadLock_A	2147483647	39043	0	0
TlulRerrorKnown_A	2147483647	2147483647	0	0
TlulRvalidKnown_A	2147483647	2147483647	0	0
WriteLockPropagation_A	2147483647	10022729	0	0
gen_digest_write_lock.DigestWriteLocksPartition_A	2147483647	119261817	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccessKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

DigestKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

DigestOffsetMustBeRepresentable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5730	5730	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0
T14	5	5	0	0

EccErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	80425	0	0
T33	41048	0	0	0
T74	8965	9360	0	0
T75	0	5436	0	0
T98	72990	0	0	0
T99	84913	0	0	0
T107	21245	0	0	0
T109	10639	0	0	0
T127	13383	12828	0	0
T128	11197	7136	0	0
T129	149654	0	0	0
T130	0	7776	0	0
T131	0	6906	0	0
T132	0	3139	0	0
T133	12338	0	0	0
T134	11200	0	0	0
T137	0	11742	0	0
T138	0	11592	0	0
T139	0	4510	0	0
T140	8847	0	0	0
T141	4241	0	0	0
T142	23047	0	0	0
T143	69032	0	0	0
T144	19135	0	0	0
T145	63289	0	0	0
T146	14560	0	0	0
T147	46604	0	0	0
T148	26797	0	0	0
T149	80729	0	0	0

ErrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

FsmStateKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

InitDoneKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

InitReadLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	500823793	0	0
T1	185220	1355	0	0
T2	66445	3245	0	0
T3	312880	7505	0	0
T5	132645	2750	0	0
T6	76740	19058	0	0
T7	65775	24095	0	0
T11	61925	20945	0	0
T12	74725	23925	0	0
T13	49770	15915	0	0
T14	65320	17473	0	0

InitWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	500823793	0	0
T1	185220	1355	0	0
T2	66445	3245	0	0
T3	312880	7505	0	0
T5	132645	2750	0	0
T6	76740	19058	0	0
T7	65775	24095	0	0
T11	61925	20945	0	0
T12	74725	23925	0	0
T13	49770	15915	0	0
T14	65320	17473	0	0

OffsetMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5730	5730	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0
T14	5	5	0	0

OtpAddrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

OtpCmdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

OtpErrorState_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	205	0	0
T6	15348	1	0	0
T9	465048	0	0	0
T10	294643	0	0	0
T17	9363	0	0	0
T33	41048	0	0	0
T36	81122	0	0	0
T37	37452	0	0	0
T68	10686	0	0	0
T91	0	1	0	0
T92	0	1	0	0
T98	72990	0	0	0
T99	84913	0	0	0
T100	72699	0	0	0
T103	11634	0	0	0
T104	41809	0	0	0
T105	9510	0	0	0
T107	21245	0	0	0
T109	10639	0	0	0
T112	19976	1	0	0
T129	149654	2	0	0
T133	12338	1	0	0
T134	11200	1	0	0
T135	0	4	0	0
T140	8847	0	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

OtpReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

OtpSizeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

OtpWdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

ReadLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	937363402	0	0
T1	111132	4220	0	0
T2	39867	14995	0	0
T3	312880	15117	0	0
T5	132645	23220	0	0
T6	76740	0	0	0
T7	65775	0	0	0
T8	481988	909471	0	0
T9	0	903026	0	0
T10	0	971469	0	0
T11	61925	0	0	0
T12	74725	0	0	0
T13	49770	0	0	0
T14	65320	0	0	0
T15	0	122028	0	0
T20	0	123836	0	0
T32	0	47102	0	0
T37	0	4770	0	0
T96	0	15319	0	0
T101	8102	0	0	0
T105	0	4778	0	0

SizeMustBeBlockAligned_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5730	5730	0	0
T1	5	5	0	0
T2	5	5	0	0
T3	5	5	0	0
T5	5	5	0	0
T6	5	5	0	0
T7	5	5	0	0
T11	5	5	0	0
T12	5	5	0	0
T13	5	5	0	0
T14	5	5	0	0

TlulGntKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

TlulRdataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

TlulReadOnReadLock_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39043	0	0
T3	250304	7	0	0
T5	132645	20	0	0
T6	76740	0	0	0
T7	65775	0	0	0
T8	1204970	85	0	0
T9	0	73	0	0
T10	0	187	0	0
T11	61925	36	0	0
T12	74725	0	0	0
T13	49770	0	0	0
T14	65320	0	0	0
T15	0	22	0	0
T20	0	35	0	0
T26	0	266	0	0
T37	0	2	0	0
T96	0	8	0	0
T101	20255	0	0	0
T105	0	8	0	0
T112	9988	0	0	0

TlulRerrorKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

TlulRvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0

WriteLockPropagation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	10022729	0	0
T3	250304	7459	0	0
T5	106116	2976	0	0
T6	61392	0	0	0
T7	52620	0	0	0
T8	963976	0	0	0
T11	49540	0	0	0
T12	59780	0	0	0
T13	39816	0	0	0
T14	52256	0	0	0
T16	0	350545	0	0
T20	74377	18067	0	0
T32	362162	18767	0	0
T33	0	3227	0	0
T40	0	16969	0	0
T41	0	2537	0	0
T59	12096	0	0	0
T61	0	4953	0	0
T67	0	82312	0	0
T69	16337	0	0	0
T73	0	22529	0	0
T74	8965	0	0	0
T96	34413	6642	0	0
T97	75255	14267	0	0
T98	0	4699	0	0
T99	0	30530	0	0
T100	0	10130	0	0
T101	16204	0	0	0
T102	0	9515	0	0
T113	11287	0	0	0
T163	0	4641	0	0
T164	0	9957	0	0
T165	0	4960	0	0
T166	0	907	0	0
T167	5991	0	0	0
T168	16578	0	0	0

gen_digest_write_lock.DigestWriteLocksPartition_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	119261817	0	0
T1	148176	101464	0	0
T2	53156	0	0	0
T3	312880	194530	0	0
T5	132645	66520	0	0
T6	76740	2493	0	0
T7	65775	3327	0	0
T8	240994	0	0	0
T11	61925	0	0	0
T12	74725	0	0	0
T13	49770	2148	0	0
T14	65320	2326	0	0
T20	0	230076	0	0
T32	0	1003529	0	0
T37	0	50539	0	0
T40	0	35579	0	0
T68	0	4429	0	0
T93	0	2411	0	0
T96	0	98708	0	0
T97	0	170757	0	0
T98	0	153258	0	0
T99	0	74081	0	0
T100	0	52484	0	0
T101	4051	0	0	0
T112	0	3585	0	0
T129	0	11392	0	0
T133	0	2253	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	185220	183795	0	0
T2	66445	63535	0	0
T3	312880	305410	0	0
T5	132645	129745	0	0
T6	76740	75425	0	0
T7	65775	64610	0	0
T11	61925	60690	0	0
T12	74725	73250	0	0
T13	49770	48470	0	0
T14	65320	64060	0	0