Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

23900081

1

T1

698

T2

2374

T3

1702

full_word

7872238

1

T1

639

T2

1096

T3

1233

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31772049	1			T1	1337		T2	3470		T3	2935
auto[TlIntgErrCmd]	86	1			T270	6		T271	5		T272	1
auto[TlIntgErrData]	94	1			T270	3		T271	7		T272	5
auto[TlIntgErrBoth]	90	1			T270	1		T271	8		T272	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9270469

1

T1

1136

T2

3163

T3

2591

auto[1]

22501850

1

T1

201

T2

307

T3

344

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5845254	1			T1	585		T2	2207		T3	1511
auto[TlIntgErrNone]	partial	auto[1]	18054581	1			T1	113		T2	167		T3	191
auto[TlIntgErrNone]	full_word	auto[0]	3425092	1			T1	551		T2	956		T3	1080
auto[TlIntgErrNone]	full_word	auto[1]	4447122	1			T1	88		T2	140		T3	153
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T270	2		T271	2		T272	1
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T270	4		T271	3		T335	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T340	1		T341	1		T342	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T335	2		T277	1		T336	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T270	1		T271	2		T272	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T270	1		T271	4		T272	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T270	1		T271	1		T272	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T338	1		T336	2		T343	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T271	2		T272	1		T335	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T270	1		T271	6		T272	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T335	1		T339	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T338	1		T344	1		-	-