Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25633164

1

T1

348

T2

724

T3

1386

full_word

8531779

1

T1

174

T2

239

T3

904

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34164623	1			T1	522		T2	963		T3	2290
auto[TlIntgErrCmd]	97	1			T274	6		T275	5		T276	7
auto[TlIntgErrData]	108	1			T274	7		T275	2		T276	8
auto[TlIntgErrBoth]	115	1			T274	7		T275	3		T276	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10184573

1

T1

317

T2

668

T3

2020

auto[1]

23980370

1

T1

205

T2

295

T3

270

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6410489	1			T1	242		T2	564		T3	1226
auto[TlIntgErrNone]	partial	auto[1]	19222386	1			T1	106		T2	160		T3	160
auto[TlIntgErrNone]	full_word	auto[0]	3773943	1			T1	75		T2	104		T3	794
auto[TlIntgErrNone]	full_word	auto[1]	4757805	1			T1	99		T2	135		T3	110
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T274	2		T275	1		T276	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T274	3		T275	4		T276	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T274	1		T352	1		T279	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T354	1		T280	1		T355	2
auto[TlIntgErrData]	partial	auto[0]	46	1			T274	2		T275	1		T276	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T274	5		T275	1		T276	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T352	1		T354	1		T280	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T276	1		T352	2		T355	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T274	3		T276	3		T350	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T274	3		T275	3		T276	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T274	1		T350	1		T355	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T350	1		T352	1		T356	1