Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

25483596

1

T1

3299

T2

765

T3

264196

full_word

8333572

1

T1

2917

T2

190

T3

79387

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33816868	1			T1	6216		T2	955		T3	343583
auto[TlIntgErrCmd]	108	1			T261	2		T262	9		T263	5
auto[TlIntgErrData]	91	1			T261	2		T262	3		T263	2
auto[TlIntgErrBoth]	101	1			T261	6		T262	8		T263	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9920062

1

T1

5207

T2

744

T3

38388

auto[1]

23897106

1

T1

1009

T2

211

T3

305195

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6313524	1			T1	2735		T2	642		T3	19359
auto[TlIntgErrNone]	partial	auto[1]	19169805	1			T1	564		T2	123		T3	244837
auto[TlIntgErrNone]	full_word	auto[0]	3606406	1			T1	2472		T2	102		T3	19029
auto[TlIntgErrNone]	full_word	auto[1]	4727133	1			T1	445		T2	88		T3	60358
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T262	3		T263	1		T271	3
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T261	2		T262	6		T263	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T263	1		T341	1		T342	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T343	1		T344	1		T345	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T262	1		T271	5		T341	3
auto[TlIntgErrData]	partial	auto[1]	41	1			T261	2		T262	1		T263	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T262	1		T270	1		T344	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T339	1		T346	1		T345	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T261	5		T262	3		T341	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T261	1		T262	5		T263	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T344	1		T347	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T271	1		T348	1		T349	1