Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	485849095	8096182	0	0
check_regwen_rd_A	485849095	2356	0	0
check_timeout_rd_A	485849095	2579	0	0
check_trigger_regwen_rd_A	485849095	2322	0	0
consistency_check_period_rd_A	485849095	2742	0	0
creator_sw_cfg_read_lock_rd_A	485849095	2255	0	0
direct_access_address_rd_A	485849095	1981	0	0
direct_access_wdata_0_rd_A	485849095	1359	0	0
direct_access_wdata_1_rd_A	485849095	1587	0	0
integrity_check_period_rd_A	485849095	2408	0	0
intr_enable_rd_A	485849095	3006	0	0
owner_sw_cfg_read_lock_rd_A	485849095	2222	0	0
rot_creator_auth_codesign_read_lock_rd_A	485849095	2300	0	0
rot_creator_auth_state_read_lock_rd_A	485849095	2106	0	0
vendor_test_read_lock_rd_A	485849095	2048	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	8096182	0	0
T3	623106	110333	0	0
T4	514427	100712	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	34490	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	173806	0	0
T12	0	85131	0	0
T65	0	17156	0	0
T110	11959	0	0	0
T111	0	96487	0	0
T162	0	54099	0	0
T163	0	102646	0	0
T207	0	159221	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2356	0	0
T3	623106	108	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	56	0	0
T65	0	39	0	0
T103	0	46	0	0
T110	11959	0	0	0
T207	0	73	0	0
T316	0	37	0	0
T322	0	68	0	0
T323	0	47	0	0
T324	0	38	0	0
T325	0	137	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2579	0	0
T3	623106	120	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	54	0	0
T65	0	20	0	0
T103	0	110	0	0
T110	11959	0	0	0
T207	0	88	0	0
T316	0	52	0	0
T322	0	121	0	0
T323	0	33	0	0
T324	0	26	0	0
T325	0	173	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2322	0	0
T3	623106	95	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	51	0	0
T65	0	6	0	0
T103	0	43	0	0
T110	11959	0	0	0
T207	0	74	0	0
T316	0	37	0	0
T322	0	76	0	0
T323	0	55	0	0
T324	0	32	0	0
T325	0	130	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2742	0	0
T3	623106	147	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	50	0	0
T65	0	33	0	0
T103	0	43	0	0
T110	11959	0	0	0
T207	0	114	0	0
T316	0	35	0	0
T322	0	95	0	0
T323	0	38	0	0
T324	0	39	0	0
T325	0	200	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2255	0	0
T3	623106	135	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	48	0	0
T65	0	26	0	0
T103	0	72	0	0
T110	11959	0	0	0
T207	0	141	0	0
T316	0	29	0	0
T322	0	135	0	0
T323	0	19	0	0
T324	0	36	0	0
T325	0	181	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	1981	0	0
T3	623106	106	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	52	0	0
T65	0	13	0	0
T103	0	67	0	0
T110	11959	0	0	0
T207	0	83	0	0
T316	0	53	0	0
T322	0	89	0	0
T323	0	27	0	0
T324	0	28	0	0
T325	0	145	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	1359	0	0
T3	623106	108	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	13	0	0
T65	0	6	0	0
T103	0	49	0	0
T110	11959	0	0	0
T207	0	50	0	0
T316	0	28	0	0
T322	0	41	0	0
T323	0	56	0	0
T324	0	41	0	0
T325	0	76	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	1587	0	0
T3	623106	113	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	27	0	0
T65	0	9	0	0
T103	0	23	0	0
T110	11959	0	0	0
T207	0	74	0	0
T316	0	43	0	0
T322	0	76	0	0
T323	0	25	0	0
T324	0	9	0	0
T325	0	77	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2408	0	0
T3	623106	121	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	58	0	0
T65	0	6	0	0
T103	0	69	0	0
T110	11959	0	0	0
T207	0	64	0	0
T316	0	44	0	0
T322	0	116	0	0
T323	0	54	0	0
T324	0	38	0	0
T325	0	123	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	3006	0	0
T3	623106	126	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	41	0	0
T31	0	16	0	0
T65	0	14	0	0
T99	0	17	0	0
T103	0	89	0	0
T110	11959	0	0	0
T149	0	5	0	0
T207	0	105	0	0
T290	0	57	0	0
T322	0	119	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2222	0	0
T3	623106	121	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	53	0	0
T65	0	23	0	0
T103	0	51	0	0
T110	11959	0	0	0
T207	0	88	0	0
T316	0	52	0	0
T322	0	92	0	0
T323	0	30	0	0
T324	0	30	0	0
T325	0	150	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2300	0	0
T3	623106	144	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	50	0	0
T65	0	12	0	0
T103	0	42	0	0
T110	11959	0	0	0
T207	0	150	0	0
T316	0	32	0	0
T322	0	161	0	0
T323	0	31	0	0
T324	0	20	0	0
T325	0	174	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2106	0	0
T3	623106	108	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	33	0	0
T65	0	33	0	0
T103	0	68	0	0
T110	11959	0	0	0
T207	0	120	0	0
T316	0	46	0	0
T322	0	88	0	0
T323	0	32	0	0
T324	0	29	0	0
T325	0	139	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	485849095	2048	0	0
T3	623106	109	0	0
T4	514427	0	0	0
T5	72843	0	0	0
T6	43455	0	0	0
T7	479739	0	0	0
T8	14970	0	0	0
T9	6063	0	0	0
T10	21202	0	0	0
T11	114571	0	0	0
T12	0	41	0	0
T65	0	12	0	0
T103	0	58	0	0
T110	11959	0	0	0
T207	0	72	0	0
T316	0	29	0	0
T322	0	118	0	0
T323	0	33	0	0
T324	0	59	0	0
T325	0	119	0	0