Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

24067033

1

T1

103430

T2

987

T3

973

full_word

7894562

1

T1

30150

T2

810

T3

269

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31961325	1			T1	133580		T2	1797		T3	1242
auto[TlIntgErrCmd]	89	1			T256	1		T257	3		T258	8
auto[TlIntgErrData]	94	1			T256	6		T257	4		T258	2
auto[TlIntgErrBoth]	87	1			T256	3		T257	3		T258	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9139322

1

T1

18693

T2

1555

T3

952

auto[1]

22822273

1

T1

114887

T2

242

T3

290

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	5751331	1			T1	10301		T2	847		T3	806
auto[TlIntgErrNone]	partial	auto[1]	18315453	1			T1	93129		T2	140		T3	167
auto[TlIntgErrNone]	full_word	auto[0]	3387857	1			T1	8392		T2	708		T3	146
auto[TlIntgErrNone]	full_word	auto[1]	4506684	1			T1	21758		T2	102		T3	123
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T258	5		T352	1		T266	3
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T256	1		T257	3		T258	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T266	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T354	1		T266	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T256	3		T257	2		T258	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T256	2		T257	2		T354	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T258	1		T354	1		T352	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T256	1		T356	1		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T256	3		T257	2		T258	4
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T257	1		T258	5		T354	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T258	1		T359	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T354	1		T266	1		T262	1