Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.02		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	449683628	7755167	0	0
check_regwen_rd_A	449683628	2572	0	0
check_timeout_rd_A	449683628	1930	0	0
check_trigger_regwen_rd_A	449683628	2740	0	0
consistency_check_period_rd_A	449683628	2778	0	0
creator_sw_cfg_read_lock_rd_A	449683628	1849	0	0
direct_access_address_rd_A	449683628	1655	0	0
direct_access_wdata_0_rd_A	449683628	1159	0	0
direct_access_wdata_1_rd_A	449683628	1198	0	0
integrity_check_period_rd_A	449683628	2756	0	0
intr_enable_rd_A	449683628	3784	0	0
owner_sw_cfg_read_lock_rd_A	449683628	1821	0	0
rot_creator_auth_codesign_read_lock_rd_A	449683628	1958	0	0
rot_creator_auth_state_read_lock_rd_A	449683628	1967	0	0
vendor_test_read_lock_rd_A	449683628	1772	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	7755167	0	0
T1	210721	41564	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T7	0	87818	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	222754	0	0
T16	0	179405	0	0
T86	0	94553	0	0
T136	0	156731	0	0
T204	0	133977	0	0
T237	0	73077	0	0
T247	0	399598	0	0
T268	0	171482	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	2572	0	0
T1	210721	21	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	242	0	0
T204	0	183	0	0
T276	0	150	0	0
T278	0	186	0	0
T333	0	20	0	0
T334	0	75	0	0
T335	0	49	0	0
T336	0	74	0	0
T337	0	56	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1930	0	0
T1	210721	72	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	252	0	0
T204	0	184	0	0
T276	0	113	0	0
T278	0	216	0	0
T333	0	33	0	0
T334	0	107	0	0
T335	0	40	0	0
T336	0	95	0	0
T337	0	60	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	2740	0	0
T1	210721	52	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	203	0	0
T204	0	169	0	0
T276	0	93	0	0
T278	0	186	0	0
T333	0	34	0	0
T334	0	63	0	0
T335	0	17	0	0
T336	0	96	0	0
T337	0	37	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	2778	0	0
T1	210721	73	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	207	0	0
T204	0	190	0	0
T276	0	131	0	0
T278	0	184	0	0
T333	0	27	0	0
T334	0	86	0	0
T335	0	36	0	0
T336	0	125	0	0
T337	0	83	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1849	0	0
T1	210721	28	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	255	0	0
T204	0	156	0	0
T276	0	129	0	0
T278	0	126	0	0
T333	0	39	0	0
T334	0	118	0	0
T335	0	56	0	0
T336	0	80	0	0
T337	0	106	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1655	0	0
T1	210721	32	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	240	0	0
T204	0	162	0	0
T276	0	144	0	0
T278	0	201	0	0
T333	0	19	0	0
T334	0	93	0	0
T335	0	27	0	0
T336	0	156	0	0
T337	0	82	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1159	0	0
T1	210721	43	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	184	0	0
T204	0	100	0	0
T276	0	92	0	0
T278	0	176	0	0
T333	0	3	0	0
T334	0	78	0	0
T335	0	4	0	0
T336	0	60	0	0
T337	0	43	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1198	0	0
T1	210721	31	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	209	0	0
T204	0	122	0	0
T276	0	127	0	0
T278	0	157	0	0
T333	0	10	0	0
T334	0	74	0	0
T335	0	28	0	0
T336	0	96	0	0
T337	0	37	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	2756	0	0
T1	210721	64	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	199	0	0
T204	0	175	0	0
T276	0	138	0	0
T278	0	150	0	0
T333	0	34	0	0
T334	0	105	0	0
T335	0	29	0	0
T336	0	84	0	0
T337	0	30	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	3784	0	0
T1	210721	90	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	290	0	0
T203	0	33	0	0
T204	0	126	0	0
T276	0	130	0	0
T278	0	262	0	0
T333	0	41	0	0
T334	0	99	0	0
T338	0	47	0	0
T339	0	15	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1821	0	0
T1	210721	28	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	224	0	0
T204	0	187	0	0
T276	0	108	0	0
T278	0	211	0	0
T333	0	12	0	0
T334	0	91	0	0
T335	0	20	0	0
T336	0	123	0	0
T337	0	66	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1958	0	0
T1	210721	48	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	274	0	0
T204	0	157	0	0
T276	0	113	0	0
T278	0	174	0	0
T333	0	37	0	0
T334	0	105	0	0
T335	0	39	0	0
T336	0	115	0	0
T337	0	73	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1967	0	0
T1	210721	62	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	307	0	0
T204	0	221	0	0
T276	0	117	0	0
T278	0	164	0	0
T333	0	28	0	0
T334	0	93	0	0
T335	0	34	0	0
T336	0	103	0	0
T337	0	40	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449683628	1772	0	0
T1	210721	58	0	0
T2	40924	0	0	0
T3	9081	0	0	0
T4	16049	0	0	0
T5	38663	0	0	0
T6	32483	0	0	0
T8	10823	0	0	0
T9	106712	0	0	0
T10	54564	0	0	0
T11	17872	0	0	0
T12	0	188	0	0
T204	0	139	0	0
T276	0	135	0	0
T278	0	161	0	0
T333	0	46	0	0
T334	0	90	0	0
T335	0	46	0	0
T336	0	139	0	0
T337	0	37	0	0