Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

26451961

1

T1

1050

T2

1266

T3

308

full_word

8579100

1

T1

575

T2

174

T3

153

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35030751	1			T1	1625		T2	1440		T3	461
auto[TlIntgErrCmd]	106	1			T274	2		T275	5		T276	3
auto[TlIntgErrData]	97	1			T274	6		T275	8		T276	5
auto[TlIntgErrBoth]	107	1			T274	2		T275	7		T276	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9978576

1

T1

1444

T2

1387

T3

275

auto[1]

25052485

1

T1

181

T2

53

T3

186

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6329856	1			T1	948		T2	1238		T3	196
auto[TlIntgErrNone]	partial	auto[1]	20121817	1			T1	102		T2	28		T3	112
auto[TlIntgErrNone]	full_word	auto[0]	3648586	1			T1	496		T2	149		T3	79
auto[TlIntgErrNone]	full_word	auto[1]	4930492	1			T1	79		T2	25		T3	74
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T274	1		T276	2		T282	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T274	1		T275	5		T276	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T282	1		T367	1		T369	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T370	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1			T274	3		T275	4		T276	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T274	2		T275	4		T276	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T274	1		T369	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T367	1		T371	1		T370	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T274	1		T275	3		T276	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T274	1		T275	3		T282	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T282	2		T280	1		T371	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T275	1		T368	1		T366	1