Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.14	94.16	96.15	96.75		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	455936558	8508493	0	0
check_regwen_rd_A	455936558	2488	0	0
check_timeout_rd_A	455936558	2221	0	0
check_trigger_regwen_rd_A	455936558	2495	0	0
consistency_check_period_rd_A	455936558	2929	0	0
creator_sw_cfg_read_lock_rd_A	455936558	2216	0	0
direct_access_address_rd_A	455936558	1401	0	0
direct_access_wdata_0_rd_A	455936558	928	0	0
direct_access_wdata_1_rd_A	455936558	1123	0	0
integrity_check_period_rd_A	455936558	2619	0	0
intr_enable_rd_A	455936558	3062	0	0
owner_sw_cfg_read_lock_rd_A	455936558	2230	0	0
rot_creator_auth_codesign_read_lock_rd_A	455936558	2244	0	0
rot_creator_auth_state_read_lock_rd_A	455936558	2168	0	0
vendor_test_read_lock_rd_A	455936558	2105	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	8508493	0	0
T8	375272	70727	0	0
T9	246333	42303	0	0
T14	0	293799	0	0
T15	0	291733	0	0
T29	17932	0	0	0
T38	40463	0	0	0
T43	10933	0	0	0
T91	64567	0	0	0
T109	23261	0	0	0
T133	0	62084	0	0
T134	0	51997	0	0
T141	0	79314	0	0
T152	0	158685	0	0
T185	14903	0	0	0
T205	27005	0	0	0
T261	0	45849	0	0
T283	0	3619	0	0
T284	18724	0	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2488	0	0
T18	0	27	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	88	0	0
T152	539574	0	0	0
T181	0	89	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	32	0	0
T340	0	202	0	0
T341	0	79	0	0
T342	0	114	0	0
T343	0	32	0	0
T344	0	204	0	0
T345	0	155	0	0
T346	24700	0	0	0
T347	4091	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2221	0	0
T18	0	29	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	110	0	0
T152	539574	0	0	0
T181	0	54	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	50	0	0
T340	0	165	0	0
T341	0	97	0	0
T342	0	190	0	0
T343	0	47	0	0
T344	0	326	0	0
T345	0	143	0	0
T346	24700	0	0	0
T347	4091	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2495	0	0
T18	0	26	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	84	0	0
T152	539574	0	0	0
T181	0	76	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	25	0	0
T340	0	170	0	0
T341	0	90	0	0
T342	0	134	0	0
T343	0	38	0	0
T344	0	299	0	0
T345	0	127	0	0
T346	24700	0	0	0
T347	4091	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2929	0	0
T18	0	26	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	99	0	0
T152	539574	0	0	0
T181	0	83	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	38	0	0
T340	0	218	0	0
T341	0	113	0	0
T342	0	204	0	0
T343	0	85	0	0
T344	0	352	0	0
T345	0	127	0	0
T346	24700	0	0	0
T347	4091	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2216	0	0
T18	0	41	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	122	0	0
T152	539574	0	0	0
T181	0	47	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	55	0	0
T340	0	157	0	0
T341	0	94	0	0
T342	0	105	0	0
T343	0	49	0	0
T344	0	395	0	0
T345	0	146	0	0
T346	24700	0	0	0
T347	4091	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	1401	0	0
T18	0	38	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	117	0	0
T152	539574	0	0	0
T181	0	50	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	37	0	0
T340	0	244	0	0
T341	0	136	0	0
T342	0	170	0	0
T343	0	34	0	0
T344	0	305	0	0
T345	0	173	0	0
T346	24700	0	0	0
T347	4091	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	928	0	0
T18	0	35	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	66	0	0
T152	539574	0	0	0
T181	0	48	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	27	0	0
T340	0	137	0	0
T341	0	91	0	0
T342	0	139	0	0
T343	0	39	0	0
T344	0	230	0	0
T345	0	91	0	0
T346	24700	0	0	0
T347	4091	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	1123	0	0
T18	0	13	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	63	0	0
T152	539574	0	0	0
T181	0	60	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	28	0	0
T340	0	252	0	0
T341	0	108	0	0
T342	0	157	0	0
T343	0	9	0	0
T344	0	286	0	0
T345	0	108	0	0
T346	24700	0	0	0
T347	4091	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2619	0	0
T18	0	43	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	104	0	0
T152	539574	0	0	0
T181	0	69	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	34	0	0
T340	0	167	0	0
T341	0	90	0	0
T342	0	189	0	0
T343	0	11	0	0
T344	0	262	0	0
T345	0	142	0	0
T346	24700	0	0	0
T347	4091	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	3062	0	0
T7	856755	0	0	0
T12	604215	17	0	0
T13	21946	0	0	0
T18	0	35	0	0
T59	0	36	0	0
T61	10604	0	0	0
T97	0	24	0	0
T99	13939	0	0	0
T100	10567	0	0	0
T101	15062	0	0	0
T102	9605	0	0	0
T103	16565	0	0	0
T104	25441	0	0	0
T134	0	108	0	0
T136	0	8	0	0
T237	0	13	0	0
T340	0	205	0	0
T341	0	79	0	0
T348	0	10	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2230	0	0
T18	0	42	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	86	0	0
T152	539574	0	0	0
T181	0	68	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	32	0	0
T340	0	162	0	0
T341	0	173	0	0
T342	0	148	0	0
T343	0	38	0	0
T344	0	267	0	0
T345	0	171	0	0
T346	24700	0	0	0
T347	4091	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2244	0	0
T18	0	47	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	84	0	0
T152	539574	0	0	0
T181	0	92	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	59	0	0
T340	0	224	0	0
T341	0	146	0	0
T342	0	188	0	0
T343	0	27	0	0
T344	0	295	0	0
T345	0	143	0	0
T346	24700	0	0	0
T347	4091	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2168	0	0
T18	0	37	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	67	0	0
T152	539574	0	0	0
T181	0	39	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	28	0	0
T340	0	229	0	0
T341	0	117	0	0
T342	0	120	0	0
T343	0	28	0	0
T344	0	289	0	0
T345	0	99	0	0
T346	24700	0	0	0
T347	4091	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455936558	2105	0	0
T18	0	35	0	0
T30	12115	0	0	0
T71	10131	0	0	0
T72	16160	0	0	0
T134	349708	101	0	0
T152	539574	0	0	0
T181	0	51	0	0
T200	89356	0	0	0
T219	20940	0	0	0
T250	26767	0	0	0
T294	0	34	0	0
T340	0	182	0	0
T341	0	105	0	0
T342	0	158	0	0
T343	0	45	0	0
T344	0	276	0	0
T345	0	127	0	0
T346	24700	0	0	0
T347	4091	0	0	0