Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.22	94.16	96.15	97.20		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	93256249	297242	0	0
check_regwen_rd_A	93256249	2477	0	0
check_timeout_rd_A	93256249	787	0	0
check_trigger_regwen_rd_A	93256249	2432	0	0
consistency_check_period_rd_A	93256249	2625	0	0
creator_sw_cfg_read_lock_rd_A	93256249	643	0	0
direct_access_address_rd_A	93256249	394	0	0
direct_access_wdata_0_rd_A	93256249	74	0	0
direct_access_wdata_1_rd_A	93256249	42	0	0
integrity_check_period_rd_A	93256249	2498	0	0
intr_enable_rd_A	93256249	3461	0	0
owner_sw_cfg_read_lock_rd_A	93256249	726	0	0
rot_creator_auth_codesign_read_lock_rd_A	93256249	694	0	0
rot_creator_auth_state_read_lock_rd_A	93256249	753	0	0
vendor_test_read_lock_rd_A	93256249	724	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	297242	0	0
T5	143472	2792	0	0
T7	0	6275	0	0
T8	0	7464	0	0
T9	0	9409	0	0
T10	0	5918	0	0
T11	0	2814	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T26	0	8946	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T269	0	1597	0	0
T270	0	3528	0	0
T271	0	7714	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	2477	0	0
T5	143472	23	0	0
T9	0	21	0	0
T10	0	40	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	20	0	0
T43	0	21	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	34	0	0
T138	0	43	0	0
T270	0	13	0	0
T305	0	69	0	0
T306	0	1	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	787	0	0
T5	143472	29	0	0
T9	0	21	0	0
T10	0	48	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	17	0	0
T43	0	23	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	32	0	0
T138	0	47	0	0
T270	0	31	0	0
T305	0	57	0	0
T306	0	20	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	2432	0	0
T5	143472	27	0	0
T9	0	30	0	0
T10	0	63	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	20	0	0
T43	0	21	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	42	0	0
T138	0	38	0	0
T270	0	18	0	0
T305	0	52	0	0
T306	0	7	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	2625	0	0
T5	143472	25	0	0
T9	0	16	0	0
T10	0	44	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	18	0	0
T43	0	23	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	29	0	0
T138	0	40	0	0
T270	0	24	0	0
T305	0	45	0	0
T306	0	27	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	643	0	0
T5	143472	16	0	0
T9	0	40	0	0
T10	0	38	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T43	0	19	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	25	0	0
T138	0	28	0	0
T270	0	15	0	0
T305	0	40	0	0
T306	0	12	0	0
T307	0	4	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	394	0	0
T5	143472	37	0	0
T9	0	14	0	0
T10	0	40	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	1	0	0
T43	0	19	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	7	0	0
T138	0	25	0	0
T270	0	17	0	0
T305	0	61	0	0
T306	0	22	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	74	0	0
T5	143472	4	0	0
T9	0	3	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	2	0	0
T138	0	4	0	0
T270	0	5	0	0
T305	0	10	0	0
T306	0	7	0	0
T308	0	14	0	0
T309	0	16	0	0
T310	0	9	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	42	0	0
T9	447081	8	0	0
T10	0	8	0	0
T36	0	7	0	0
T43	0	2	0	0
T120	13595	0	0	0
T138	0	12	0	0
T308	0	5	0	0
T311	40274	0	0	0
T312	145982	0	0	0
T313	10853	0	0	0
T314	14868	0	0	0
T315	103582	0	0	0
T316	5957	0	0	0
T317	32284	0	0	0
T318	15722	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	2498	0	0
T5	143472	24	0	0
T9	0	44	0	0
T10	0	54	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	12	0	0
T43	0	23	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	21	0	0
T138	0	58	0	0
T270	0	22	0	0
T305	0	52	0	0
T306	0	18	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	3461	0	0
T5	143472	41	0	0
T9	0	58	0	0
T10	0	76	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T43	0	23	0	0
T69	0	9	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T121	0	12	0	0
T270	0	21	0	0
T319	0	7	0	0
T320	0	9	0	0
T321	0	20	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	726	0	0
T5	143472	28	0	0
T9	0	21	0	0
T10	0	51	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	12	0	0
T43	0	25	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	41	0	0
T138	0	44	0	0
T270	0	18	0	0
T305	0	40	0	0
T306	0	16	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	694	0	0
T5	143472	19	0	0
T9	0	32	0	0
T10	0	52	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	9	0	0
T43	0	26	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	21	0	0
T138	0	36	0	0
T270	0	15	0	0
T305	0	37	0	0
T306	0	13	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	753	0	0
T5	143472	32	0	0
T9	0	27	0	0
T10	0	31	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	17	0	0
T43	0	22	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	31	0	0
T138	0	50	0	0
T270	0	18	0	0
T305	0	56	0	0
T306	0	18	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93256249	724	0	0
T5	143472	18	0	0
T9	0	12	0	0
T10	0	48	0	0
T15	165698	0	0	0
T16	13178	0	0	0
T17	74651	0	0	0
T18	17078	0	0	0
T19	10920	0	0	0
T36	0	9	0	0
T43	0	22	0	0
T100	22306	0	0	0
T108	61828	0	0	0
T109	137767	0	0	0
T111	16838	0	0	0
T136	0	21	0	0
T138	0	52	0	0
T270	0	29	0	0
T305	0	39	0	0
T306	0	3	0	0