Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4939127

1

T1

5506

T2

33456

T3

609

full_word

2404893

1

T1

4936

T2

11508

T3

275

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7343710	1			T1	10442		T2	44964		T3	884
auto[TlIntgErrCmd]	104	1			T250	6		T251	4		T252	8
auto[TlIntgErrData]	101	1			T250	8		T251	4		T252	3
auto[TlIntgErrBoth]	105	1			T250	6		T251	2		T252	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5626157

1

T1

9484

T2

14850

T3

564

auto[1]

1717863

1

T1

958

T2

30114

T3

320

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3745744	1			T1	4943		T2	9880		T3	425
auto[TlIntgErrNone]	partial	auto[1]	1193095	1			T1	563		T2	23576		T3	184
auto[TlIntgErrNone]	full_word	auto[0]	1880282	1			T1	4541		T2	4970		T3	139
auto[TlIntgErrNone]	full_word	auto[1]	524589	1			T1	395		T2	6538		T3	136
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T250	3		T251	1		T252	3
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T250	3		T251	3		T252	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T256	1		T332	1		T328	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T256	1		T333	1		T325	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T250	5		T251	3		T252	1
auto[TlIntgErrData]	partial	auto[1]	50	1			T250	2		T251	1		T252	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T326	1		T334	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T250	1		T325	1		T326	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T250	2		T251	1		T252	3
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T250	4		T251	1		T252	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T252	2		T325	1		T330	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T327	1		-	-		-	-