Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.20	94.16	96.15	97.08		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	92591523	310506	0	0
check_regwen_rd_A	92591523	1303	0	0
check_timeout_rd_A	92591523	543	0	0
check_trigger_regwen_rd_A	92591523	1367	0	0
consistency_check_period_rd_A	92591523	1439	0	0
creator_sw_cfg_read_lock_rd_A	92591523	462	0	0
direct_access_address_rd_A	92591523	146	0	0
direct_access_wdata_0_rd_A	92591523	28	0	0
direct_access_wdata_1_rd_A	92591523	53	0	0
integrity_check_period_rd_A	92591523	1359	0	0
intr_enable_rd_A	92591523	1744	0	0
owner_sw_cfg_read_lock_rd_A	92591523	674	0	0
rot_creator_auth_codesign_read_lock_rd_A	92591523	519	0	0
rot_creator_auth_state_read_lock_rd_A	92591523	605	0	0
vendor_test_read_lock_rd_A	92591523	513	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	310506	0	0
T2	426325	10760	0	0
T3	14362	0	0	0
T4	43173	0	0	0
T5	302685	6565	0	0
T6	78468	0	0	0
T7	18058	0	0	0
T8	38850	0	0	0
T9	18148	0	0	0
T10	12099	0	0	0
T11	10219	0	0	0
T12	0	3400	0	0
T17	0	9332	0	0
T18	0	6952	0	0
T28	0	2861	0	0
T56	0	6334	0	0
T57	0	5646	0	0
T147	0	3675	0	0
T231	0	8591	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	1303	0	0
T14	34159	0	0	0
T28	192533	7	0	0
T40	0	46	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	35	0	0
T202	24113	0	0	0
T254	0	444	0	0
T255	0	15	0	0
T274	0	17	0	0
T291	0	19	0	0
T292	0	29	0	0
T293	0	19	0	0
T294	0	6	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	543	0	0
T14	34159	0	0	0
T28	192533	4	0	0
T40	0	55	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	16	0	0
T202	24113	0	0	0
T255	0	3	0	0
T274	0	13	0	0
T291	0	28	0	0
T292	0	25	0	0
T293	0	20	0	0
T295	0	7	0	0
T296	0	4	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	1367	0	0
T40	0	41	0	0
T92	32366	0	0	0
T187	188152	33	0	0
T206	16366	0	0	0
T252	0	90	0	0
T254	0	459	0	0
T255	0	5	0	0
T259	57228	0	0	0
T260	12312	0	0	0
T261	102240	0	0	0
T274	0	10	0	0
T289	31011	0	0	0
T291	0	18	0	0
T292	0	18	0	0
T293	0	29	0	0
T294	0	7	0	0
T297	3361	0	0	0
T298	53043	0	0	0
T299	35062	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	1439	0	0
T14	34159	0	0	0
T28	192533	11	0	0
T40	0	60	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	32	0	0
T202	24113	0	0	0
T254	0	448	0	0
T255	0	1	0	0
T274	0	7	0	0
T291	0	13	0	0
T292	0	21	0	0
T293	0	36	0	0
T294	0	5	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	462	0	0
T14	34159	0	0	0
T28	192533	19	0	0
T40	0	36	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	12	0	0
T202	24113	0	0	0
T255	0	2	0	0
T274	0	5	0	0
T291	0	17	0	0
T292	0	17	0	0
T293	0	13	0	0
T294	0	3	0	0
T296	0	3	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	146	0	0
T14	34159	0	0	0
T28	192533	7	0	0
T40	0	34	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	34	0	0
T202	24113	0	0	0
T255	0	1	0	0
T291	0	16	0	0
T292	0	24	0	0
T293	0	7	0	0
T294	0	2	0	0
T296	0	2	0	0
T300	0	3	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	28	0	0
T40	0	9	0	0
T92	32366	0	0	0
T187	188152	3	0	0
T206	16366	0	0	0
T259	57228	0	0	0
T260	12312	0	0	0
T261	102240	0	0	0
T289	31011	0	0	0
T292	0	1	0	0
T293	0	11	0	0
T297	3361	0	0	0
T298	53043	0	0	0
T299	35062	0	0	0
T301	0	4	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	53	0	0
T14	34159	0	0	0
T28	192533	6	0	0
T40	0	8	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T202	24113	0	0	0
T255	0	2	0	0
T291	0	4	0	0
T292	0	13	0	0
T293	0	19	0	0
T300	0	1	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	1359	0	0
T14	34159	0	0	0
T28	192533	13	0	0
T40	0	20	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	30	0	0
T202	24113	0	0	0
T254	0	431	0	0
T255	0	12	0	0
T274	0	28	0	0
T291	0	15	0	0
T292	0	23	0	0
T293	0	24	0	0
T295	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	1744	0	0
T14	34159	0	0	0
T28	192533	15	0	0
T40	0	72	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	33	0	0
T202	24113	0	0	0
T291	0	46	0	0
T292	0	30	0	0
T302	0	24	0	0
T303	0	12	0	0
T304	0	11	0	0
T305	0	25	0	0
T306	0	26	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	674	0	0
T14	34159	0	0	0
T28	192533	18	0	0
T40	0	60	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	24	0	0
T202	24113	0	0	0
T255	0	7	0	0
T274	0	51	0	0
T291	0	10	0	0
T292	0	25	0	0
T293	0	17	0	0
T294	0	6	0	0
T296	0	1	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	519	0	0
T14	34159	0	0	0
T28	192533	24	0	0
T40	0	24	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	33	0	0
T202	24113	0	0	0
T267	0	4	0	0
T274	0	21	0	0
T291	0	3	0	0
T292	0	13	0	0
T293	0	44	0	0
T294	0	8	0	0
T296	0	9	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	605	0	0
T14	34159	0	0	0
T28	192533	15	0	0
T40	0	53	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	16	0	0
T202	24113	0	0	0
T255	0	8	0	0
T274	0	39	0	0
T291	0	20	0	0
T292	0	29	0	0
T293	0	19	0	0
T294	0	4	0	0
T296	0	9	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92591523	513	0	0
T14	34159	0	0	0
T28	192533	2	0	0
T40	0	34	0	0
T56	324412	0	0	0
T68	65806	0	0	0
T119	32921	0	0	0
T120	12328	0	0	0
T145	51660	0	0	0
T173	14296	0	0	0
T179	12699	0	0	0
T187	0	32	0	0
T202	24113	0	0	0
T267	0	7	0	0
T268	0	40	0	0
T274	0	15	0	0
T291	0	29	0	0
T292	0	22	0	0
T293	0	25	0	0
T294	0	3	0	0