Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

35701

1

T1

1038

T3

12

T4

173

full_word

42822

1

T1

164

T2

1

T3

10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	78213	1			T1	1202		T2	1		T3	22
auto[TlIntgErrCmd]	107	1			T4	5		T6	8		T17	8
auto[TlIntgErrData]	112	1			T4	3		T6	3		T17	6
auto[TlIntgErrBoth]	91	1			T4	2		T6	9		T17	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22685

1

T1

109

T2

1

T3

11

auto[1]

55838

1

T1

1093

T3

11

T4

473

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9909	1			T1	72		T3	4		T4	52
auto[TlIntgErrNone]	partial	auto[1]	25509	1			T1	966		T3	8		T4	111
auto[TlIntgErrNone]	full_word	auto[0]	12640	1			T1	37		T2	1		T3	7
auto[TlIntgErrNone]	full_word	auto[1]	30155	1			T1	127		T3	3		T4	358
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T4	4		T6	4		T17	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T4	1		T6	3		T17	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T47	1		T82	1		T86	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T6	1		T17	1		T87	1
auto[TlIntgErrData]	partial	auto[0]	54	1			T4	1		T6	2		T17	2
auto[TlIntgErrData]	partial	auto[1]	47	1			T4	2		T6	1		T17	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T17	1		T26	1		T27	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T26	1		T27	1		T36	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T4	1		T6	5		T17	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T4	1		T6	3		T17	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T88	1		T87	1		T86	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T6	1		T25	2		T82	1