Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5489727

1

T1

36

T2

2081

T3

177

full_word

2627290

1

T1

15

T2

1117

T3

86

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8116717	1			T1	51		T2	3198		T3	263
auto[TlIntgErrCmd]	78	1			T256	3		T257	4		T258	5
auto[TlIntgErrData]	108	1			T256	3		T257	10		T258	8
auto[TlIntgErrBoth]	114	1			T256	4		T257	6		T258	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6208427

1

T1

1

T2

2858

T3

233

auto[1]

1908590

1

T1

50

T2

340

T3

30

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	4152521	1			T1	1		T2	1885		T3	158
auto[TlIntgErrNone]	partial	auto[1]	1336936	1			T1	35		T2	196		T3	19
auto[TlIntgErrNone]	full_word	auto[0]	2055765	1			T2	973		T3	75		T4	34551
auto[TlIntgErrNone]	full_word	auto[1]	571495	1			T1	15		T2	144		T3	11
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T257	2		T258	2		T264	3
auto[TlIntgErrCmd]	partial	auto[1]	39	1			T256	2		T257	2		T258	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T321	1		T325	1		T327	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T256	1		T323	1		T263	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T256	1		T257	4		T258	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T256	2		T257	3		T258	3
auto[TlIntgErrData]	full_word	auto[0]	11	1			T257	3		T264	1		T320	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T326	1		T328	2		T329	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T256	2		T257	2		T258	4
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T256	2		T257	4		T258	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T321	1		T330	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T320	1		T321	1		T323	1