Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

4832701

1

T1

532

T2

371

T3

750

full_word

2421973

1

T1

239

T2

186

T3

259

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7254364	1			T1	771		T2	557		T3	1009
auto[TlIntgErrCmd]	105	1			T251	3		T252	4		T253	4
auto[TlIntgErrData]	92	1			T251	4		T252	3		T253	4
auto[TlIntgErrBoth]	113	1			T251	3		T252	3		T253	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5538353

1

T1

477

T2

333

T3

688

auto[1]

1716321

1

T1

294

T2

224

T3

321

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3637122	1			T1	368		T2	238		T3	557
auto[TlIntgErrNone]	partial	auto[1]	1195294	1			T1	164		T2	133		T3	193
auto[TlIntgErrNone]	full_word	auto[0]	1901110	1			T1	109		T2	95		T3	131
auto[TlIntgErrNone]	full_word	auto[1]	520838	1			T1	130		T2	91		T3	128
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T251	2		T252	1		T253	1
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T251	1		T252	1		T253	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T259	1		T334	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T252	2		T331	1		T330	1
auto[TlIntgErrData]	partial	auto[0]	28	1			T251	3		T253	1		T259	1
auto[TlIntgErrData]	partial	auto[1]	55	1			T251	1		T252	3		T253	3
auto[TlIntgErrData]	full_word	auto[0]	6	1			T332	1		T335	1		T336	3
auto[TlIntgErrData]	full_word	auto[1]	3	1			T334	1		T337	1		T338	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T251	2		T252	1		T259	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T251	1		T252	2		T253	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T259	1		T333	1		T337	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T331	2		-	-		-	-