Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.19	94.16	96.15	97.04		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	94222298	316044	0	0
check_regwen_rd_A	94222298	1151	0	0
check_timeout_rd_A	94222298	548	0	0
check_trigger_regwen_rd_A	94222298	1088	0	0
consistency_check_period_rd_A	94222298	1209	0	0
creator_sw_cfg_read_lock_rd_A	94222298	593	0	0
direct_access_address_rd_A	94222298	384	0	0
direct_access_wdata_0_rd_A	94222298	18	0	0
direct_access_wdata_1_rd_A	94222298	13	0	0
integrity_check_period_rd_A	94222298	1132	0	0
intr_enable_rd_A	94222298	1941	0	0
owner_sw_cfg_read_lock_rd_A	94222298	619	0	0
rot_creator_auth_codesign_read_lock_rd_A	94222298	597	0	0
rot_creator_auth_state_read_lock_rd_A	94222298	561	0	0
vendor_test_read_lock_rd_A	94222298	569	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	316044	0	0
T7	365646	6494	0	0
T8	464936	12109	0	0
T14	0	5057	0	0
T16	0	14143	0	0
T17	0	12917	0	0
T18	0	4456	0	0
T33	0	2640	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T261	0	7642	0	0
T262	0	4214	0	0
T263	0	3700	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	1151	0	0
T7	365646	52	0	0
T8	464936	0	0	0
T18	0	14	0	0
T19	0	21	0	0
T33	0	25	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	33	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	34	0	0
T306	0	29	0	0
T307	0	12	0	0
T308	0	21	0	0
T309	0	15	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	548	0	0
T7	365646	38	0	0
T8	464936	0	0	0
T18	0	26	0	0
T19	0	13	0	0
T33	0	26	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	27	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	13	0	0
T306	0	20	0	0
T307	0	5	0	0
T308	0	14	0	0
T309	0	19	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	1088	0	0
T7	365646	34	0	0
T8	464936	0	0	0
T18	0	18	0	0
T19	0	7	0	0
T33	0	23	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	20	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	7	0	0
T306	0	24	0	0
T307	0	16	0	0
T308	0	16	0	0
T309	0	21	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	1209	0	0
T7	365646	57	0	0
T8	464936	0	0	0
T18	0	14	0	0
T19	0	9	0	0
T33	0	21	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	27	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	19	0	0
T306	0	13	0	0
T307	0	8	0	0
T308	0	13	0	0
T309	0	34	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	593	0	0
T7	365646	34	0	0
T8	464936	0	0	0
T18	0	25	0	0
T19	0	27	0	0
T33	0	13	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	19	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	15	0	0
T306	0	30	0	0
T307	0	4	0	0
T308	0	19	0	0
T309	0	28	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	384	0	0
T7	365646	41	0	0
T8	464936	0	0	0
T18	0	27	0	0
T19	0	47	0	0
T33	0	38	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	33	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	12	0	0
T306	0	26	0	0
T307	0	17	0	0
T308	0	16	0	0
T309	0	32	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	18	0	0
T7	365646	7	0	0
T8	464936	0	0	0
T18	0	6	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T306	0	2	0	0
T310	0	2	0	0
T311	0	1	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	13	0	0
T7	365646	3	0	0
T8	464936	0	0	0
T18	0	7	0	0
T33	0	1	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T311	0	2	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	1132	0	0
T7	365646	36	0	0
T8	464936	0	0	0
T18	0	10	0	0
T19	0	26	0	0
T33	0	19	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	3	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	27	0	0
T306	0	20	0	0
T307	0	10	0	0
T308	0	4	0	0
T309	0	37	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	1941	0	0
T7	365646	110	0	0
T8	464936	0	0	0
T15	0	53	0	0
T18	0	50	0	0
T19	0	35	0	0
T33	0	40	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T143	0	11	0	0
T144	0	1	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	19	0	0
T312	0	10	0	0
T313	0	42	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	619	0	0
T7	365646	35	0	0
T8	464936	0	0	0
T18	0	40	0	0
T19	0	12	0	0
T33	0	20	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	14	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	21	0	0
T306	0	23	0	0
T307	0	4	0	0
T308	0	9	0	0
T309	0	28	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	597	0	0
T7	365646	44	0	0
T8	464936	0	0	0
T18	0	33	0	0
T19	0	32	0	0
T33	0	15	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	11	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	28	0	0
T306	0	20	0	0
T307	0	18	0	0
T308	0	8	0	0
T309	0	17	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	561	0	0
T7	365646	45	0	0
T8	464936	0	0	0
T18	0	26	0	0
T19	0	23	0	0
T33	0	26	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	21	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	23	0	0
T306	0	17	0	0
T307	0	2	0	0
T308	0	13	0	0
T309	0	16	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94222298	569	0	0
T7	365646	58	0	0
T8	464936	0	0	0
T18	0	24	0	0
T19	0	19	0	0
T33	0	11	0	0
T76	17277	0	0	0
T142	7417	0	0	0
T144	0	25	0	0
T163	9872	0	0	0
T164	17085	0	0	0
T177	7983	0	0	0
T178	16167	0	0	0
T179	10365	0	0	0
T187	17268	0	0	0
T305	0	22	0	0
T306	0	7	0	0
T307	0	11	0	0
T308	0	20	0	0
T309	0	16	0	0