Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5337706

1

T1

990

T2

9

T3

261

full_word

2589382

1

T1

244

T2

2

T3

60

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7926838	1			T1	1234		T2	11		T3	321
auto[TlIntgErrCmd]	89	1			T256	4		T257	4		T258	9
auto[TlIntgErrData]	83	1			T256	1		T257	3		T258	8
auto[TlIntgErrBoth]	78	1			T256	5		T257	3		T258	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6011162

1

T1

942

T2

1

T3

302

auto[1]

1915926

1

T1

292

T2

10

T3

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3990403	1			T1	806		T2	1		T3	249
auto[TlIntgErrNone]	partial	auto[1]	1347073	1			T1	184		T2	8		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	2020633	1			T1	136		T3	53		T4	115
auto[TlIntgErrNone]	full_word	auto[1]	568729	1			T1	108		T2	2		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T256	2		T258	4		T268	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T256	2		T257	3		T258	5
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T257	1		T344	1		T347	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T345	1		T348	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T256	1		T257	1		T258	4
auto[TlIntgErrData]	partial	auto[1]	38	1			T257	2		T258	4		T268	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T346	1		T343	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1			T347	1		T348	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T256	1		T257	1		T258	1
auto[TlIntgErrBoth]	partial	auto[1]	37	1			T256	4		T257	1		T258	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T258	1		T263	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T257	1		T344	1		T341	1