Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.21	94.16	96.15	97.14		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	97064673	374333	0	0
check_regwen_rd_A	97064673	905	0	0
check_timeout_rd_A	97064673	410	0	0
check_trigger_regwen_rd_A	97064673	905	0	0
consistency_check_period_rd_A	97064673	909	0	0
creator_sw_cfg_read_lock_rd_A	97064673	478	0	0
direct_access_address_rd_A	97064673	212	0	0
direct_access_wdata_0_rd_A	97064673	40	0	0
direct_access_wdata_1_rd_A	97064673	47	0	0
integrity_check_period_rd_A	97064673	973	0	0
intr_enable_rd_A	97064673	1622	0	0
owner_sw_cfg_read_lock_rd_A	97064673	469	0	0
rot_creator_auth_codesign_read_lock_rd_A	97064673	390	0	0
rot_creator_auth_state_read_lock_rd_A	97064673	445	0	0
vendor_test_read_lock_rd_A	97064673	400	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	374333	0	0
T6	79384	1185	0	0
T7	158618	4838	0	0
T9	7620	0	0	0
T10	10700	0	0	0
T11	93479	0	0	0
T12	20957	0	0	0
T13	0	5129	0	0
T15	0	3027	0	0
T16	0	7557	0	0
T17	0	13809	0	0
T28	24798	0	0	0
T38	0	4527	0	0
T39	0	2974	0	0
T71	160353	0	0	0
T72	16431	0	0	0
T131	4407	0	0	0
T245	0	5633	0	0
T269	0	653	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	905	0	0
T15	152758	43	0	0
T39	191639	26	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	21	0	0
T311	0	13	0	0
T312	0	13	0	0
T313	0	7	0	0
T314	0	21	0	0
T315	0	24	0	0
T316	0	13	0	0
T317	0	7	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	410	0	0
T15	152758	19	0	0
T39	191639	29	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	23	0	0
T311	0	18	0	0
T312	0	20	0	0
T313	0	16	0	0
T314	0	25	0	0
T315	0	10	0	0
T316	0	30	0	0
T317	0	9	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	905	0	0
T15	152758	31	0	0
T39	191639	15	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	15	0	0
T311	0	28	0	0
T312	0	20	0	0
T313	0	14	0	0
T314	0	25	0	0
T315	0	25	0	0
T316	0	14	0	0
T317	0	19	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	909	0	0
T15	152758	12	0	0
T39	191639	22	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	18	0	0
T311	0	18	0	0
T312	0	28	0	0
T313	0	9	0	0
T314	0	7	0	0
T315	0	22	0	0
T316	0	29	0	0
T317	0	21	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	478	0	0
T15	152758	14	0	0
T39	191639	22	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	30	0	0
T311	0	11	0	0
T312	0	11	0	0
T313	0	8	0	0
T314	0	29	0	0
T315	0	59	0	0
T316	0	24	0	0
T317	0	3	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	212	0	0
T15	152758	21	0	0
T39	191639	20	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	26	0	0
T311	0	17	0	0
T312	0	24	0	0
T313	0	15	0	0
T314	0	21	0	0
T315	0	19	0	0
T316	0	10	0	0
T317	0	13	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	40	0	0
T15	152758	5	0	0
T39	191639	3	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	9	0	0
T313	0	6	0	0
T315	0	9	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0
T322	0	8	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	47	0	0
T15	152758	4	0	0
T39	191639	0	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	15	0	0
T312	0	2	0	0
T313	0	7	0	0
T314	0	14	0	0
T317	0	5	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	973	0	0
T15	152758	33	0	0
T39	191639	35	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	15	0	0
T311	0	34	0	0
T312	0	28	0	0
T313	0	16	0	0
T314	0	17	0	0
T315	0	19	0	0
T316	0	17	0	0
T317	0	12	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	1622	0	0
T15	0	42	0	0
T38	143124	0	0	0
T39	0	16	0	0
T70	332967	25	0	0
T83	13765	0	0	0
T108	540781	0	0	0
T109	119338	0	0	0
T114	310728	0	0	0
T126	0	14	0	0
T127	0	27	0	0
T161	10366	0	0	0
T245	0	53	0	0
T311	0	13	0	0
T312	0	35	0	0
T323	0	17	0	0
T324	0	16	0	0
T325	7008	0	0	0
T326	45336	0	0	0
T327	16051	0	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	469	0	0
T15	152758	15	0	0
T39	191639	23	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	25	0	0
T311	0	21	0	0
T312	0	7	0	0
T313	0	13	0	0
T314	0	19	0	0
T315	0	20	0	0
T316	0	17	0	0
T317	0	23	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	390	0	0
T15	152758	29	0	0
T39	191639	15	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	45	0	0
T311	0	20	0	0
T312	0	22	0	0
T313	0	2	0	0
T314	0	20	0	0
T315	0	22	0	0
T316	0	20	0	0
T317	0	9	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	445	0	0
T15	152758	19	0	0
T39	191639	30	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	24	0	0
T311	0	15	0	0
T312	0	20	0	0
T313	0	20	0	0
T314	0	18	0	0
T315	0	34	0	0
T316	0	16	0	0
T317	0	25	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97064673	400	0	0
T15	152758	24	0	0
T39	191639	21	0	0
T163	14062	0	0	0
T172	121302	0	0	0
T173	215095	0	0	0
T225	146920	0	0	0
T245	0	19	0	0
T311	0	27	0	0
T312	0	10	0	0
T313	0	21	0	0
T314	0	16	0	0
T315	0	24	0	0
T316	0	35	0	0
T317	0	16	0	0
T318	21192	0	0	0
T319	36785	0	0	0
T320	67885	0	0	0
T321	10246	0	0	0