Unified Coverage Report :: Module :: otp_ctrl_core_csr_assert_fpv

Module : otp_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_otp_ctrl_csr_assert_0/otp_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.otp_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.otp_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.12	94.16	96.15	96.65		96.43	97.18	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : otp_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	99362529	432221	0	0
check_regwen_rd_A	99362529	1871	0	0
check_timeout_rd_A	99362529	1434	0	0
check_trigger_regwen_rd_A	99362529	1897	0	0
consistency_check_period_rd_A	99362529	2088	0	0
creator_sw_cfg_read_lock_rd_A	99362529	1305	0	0
direct_access_address_rd_A	99362529	545	0	0
direct_access_wdata_0_rd_A	99362529	54	0	0
direct_access_wdata_1_rd_A	99362529	48	0	0
integrity_check_period_rd_A	99362529	1914	0	0
intr_enable_rd_A	99362529	2858	0	0
owner_sw_cfg_read_lock_rd_A	99362529	1345	0	0
rot_creator_auth_codesign_read_lock_rd_A	99362529	1435	0	0
rot_creator_auth_state_read_lock_rd_A	99362529	1460	0	0
vendor_test_read_lock_rd_A	99362529	1348	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	432221	0	0
T6	186370	4596	0	0
T12	299710	6399	0	0
T13	0	5730	0	0
T14	110009	0	0	0
T17	0	5152	0	0
T18	0	2483	0	0
T19	0	4308	0	0
T27	0	14568	0	0
T28	0	11195	0	0
T43	12035	0	0	0
T48	14609	0	0	0
T69	93426	0	0	0
T106	21364	0	0	0
T107	38995	0	0	0
T180	12329	0	0	0
T201	0	2506	0	0
T233	26232	0	0	0
T265	0	2617	0	0

check_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1871	0	0
T13	355794	34	0	0
T19	0	26	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	28	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	8	0	0
T265	0	9	0	0
T308	0	44	0	0
T309	0	17	0	0
T310	0	19	0	0
T311	0	46	0	0
T312	0	21	0	0

check_timeout_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1434	0	0
T13	355794	11	0	0
T19	0	21	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	27	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	37	0	0
T265	0	24	0	0
T308	0	43	0	0
T309	0	31	0	0
T310	0	8	0	0
T311	0	56	0	0
T312	0	21	0	0

check_trigger_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1897	0	0
T13	355794	31	0	0
T19	0	17	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	34	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	6	0	0
T265	0	24	0	0
T308	0	30	0	0
T309	0	9	0	0
T310	0	9	0	0
T311	0	53	0	0
T312	0	11	0	0

consistency_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	2088	0	0
T13	355794	21	0	0
T19	0	51	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	12	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	11	0	0
T265	0	29	0	0
T308	0	36	0	0
T309	0	14	0	0
T310	0	9	0	0
T311	0	29	0	0
T312	0	22	0	0

creator_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1305	0	0
T13	355794	21	0	0
T19	0	22	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	6	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	9	0	0
T265	0	17	0	0
T308	0	40	0	0
T309	0	35	0	0
T310	0	11	0	0
T311	0	51	0	0
T312	0	24	0	0

direct_access_address_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	545	0	0
T13	355794	28	0	0
T19	0	28	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	19	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	15	0	0
T265	0	31	0	0
T308	0	70	0	0
T309	0	12	0	0
T310	0	37	0	0
T311	0	56	0	0
T312	0	22	0	0

direct_access_wdata_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	54	0	0
T34	16694	0	0	0
T144	0	6	0	0
T174	17832	0	0	0
T195	14186	0	0	0
T225	5512	0	0	0
T257	0	6	0	0
T265	166414	12	0	0
T308	0	5	0	0
T309	0	1	0	0
T311	0	13	0	0
T312	0	6	0	0
T313	0	5	0	0
T314	12650	0	0	0
T315	113855	0	0	0
T316	78108	0	0	0
T317	43110	0	0	0
T318	45250	0	0	0

direct_access_wdata_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	48	0	0
T13	355794	2	0	0
T19	0	12	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	7	0	0
T308	0	2	0	0
T311	0	8	0	0
T313	0	3	0	0
T319	0	1	0	0
T320	0	6	0	0
T321	0	2	0	0
T322	0	5	0	0

integrity_check_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1914	0	0
T13	355794	32	0	0
T19	0	14	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	19	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	14	0	0
T265	0	23	0	0
T308	0	39	0	0
T309	0	22	0	0
T310	0	15	0	0
T311	0	60	0	0
T312	0	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	2858	0	0
T13	355794	32	0	0
T19	0	33	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T172	0	11	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T206	0	16	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T265	0	38	0	0
T308	0	76	0	0
T309	0	51	0	0
T310	0	21	0	0
T323	0	69	0	0
T324	0	24	0	0

owner_sw_cfg_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1345	0	0
T13	355794	24	0	0
T19	0	28	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	39	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	24	0	0
T265	0	23	0	0
T308	0	32	0	0
T309	0	16	0	0
T310	0	26	0	0
T311	0	33	0	0
T312	0	31	0	0

rot_creator_auth_codesign_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1435	0	0
T13	355794	22	0	0
T19	0	15	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	47	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	3	0	0
T265	0	35	0	0
T308	0	37	0	0
T309	0	20	0	0
T310	0	27	0	0
T311	0	46	0	0
T312	0	1	0	0

rot_creator_auth_state_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1460	0	0
T13	355794	16	0	0
T19	0	25	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	24	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	24	0	0
T265	0	21	0	0
T308	0	39	0	0
T309	0	27	0	0
T310	0	32	0	0
T311	0	45	0	0
T312	0	23	0	0

vendor_test_read_lock_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99362529	1348	0	0
T13	355794	15	0	0
T19	0	33	0	0
T55	16793	0	0	0
T71	186759	0	0	0
T102	94958	0	0	0
T144	0	28	0	0
T173	24840	0	0	0
T203	65218	0	0	0
T227	69730	0	0	0
T228	49286	0	0	0
T232	22273	0	0	0
T255	44968	0	0	0
T257	0	6	0	0
T265	0	21	0	0
T308	0	44	0	0
T309	0	14	0	0
T310	0	20	0	0
T311	0	44	0	0
T312	0	21	0	0