Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[otp_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

5029957

1

T1

2121

T2

5526

T3

579

full_word

2525950

1

T1

1477

T2

2846

T3

374

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7555607	1			T1	3598		T2	8372		T3	953
auto[TlIntgErrCmd]	99	1			T265	3		T266	4		T267	7
auto[TlIntgErrData]	101	1			T265	5		T266	2		T267	7
auto[TlIntgErrBoth]	100	1			T265	2		T266	4		T267	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5781926

1

T1

3179

T2

7642

T3

833

auto[1]

1773981

1

T1

419

T2

730

T3

120

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3797305	1			T1	1871		T2	5089		T3	517
auto[TlIntgErrNone]	partial	auto[1]	1232382	1			T1	250		T2	437		T3	62
auto[TlIntgErrNone]	full_word	auto[0]	1984470	1			T1	1308		T2	2553		T3	316
auto[TlIntgErrNone]	full_word	auto[1]	541450	1			T1	169		T2	293		T3	58
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T265	1		T266	3		T267	3
auto[TlIntgErrCmd]	partial	auto[1]	40	1			T265	2		T266	1		T267	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T272	1		T338	1		T339	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T272	1		T338	1		T336	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T265	1		T272	1		T338	3
auto[TlIntgErrData]	partial	auto[1]	42	1			T265	4		T266	2		T267	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T267	1		T336	2		T340	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T267	1		T271	1		T341	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T266	1		T267	1		T272	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T265	2		T266	2		T267	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T266	1		T267	1		T333	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T267	1		T335	1		T342	1